root / target-sh4 / op.c @ 559dd74d
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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static inline void set_t(void) |
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{
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env->sr |= SR_T; |
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} |
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static inline void clr_t(void) |
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{
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env->sr &= ~SR_T; |
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} |
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static inline void cond_t(int cond) |
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{
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if (cond)
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set_t(); |
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else
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clr_t(); |
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} |
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|
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void OPPROTO op_cmp_eq_imm_T0(void) |
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{
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cond_t((int32_t) T0 == (int32_t) PARAM1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_bf_s(void) |
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{
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env->delayed_pc = PARAM1; |
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if (!(env->sr & SR_T)) {
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env->flags |= DELAY_SLOT_TRUE; |
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} |
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RETURN(); |
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} |
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|
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void OPPROTO op_bt_s(void) |
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{
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env->delayed_pc = PARAM1; |
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if (env->sr & SR_T) {
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env->flags |= DELAY_SLOT_TRUE; |
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} |
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RETURN(); |
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} |
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|
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void OPPROTO op_store_flags(void) |
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{
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env->flags &= DELAY_SLOT_TRUE; |
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env->flags |= PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bra(void) |
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{
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env->delayed_pc = PARAM1; |
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RETURN(); |
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} |
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|
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void OPPROTO op_braf_T0(void) |
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{
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env->delayed_pc = PARAM1 + T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bsr(void) |
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{
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env->pr = PARAM1; |
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env->delayed_pc = PARAM2; |
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RETURN(); |
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} |
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|
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void OPPROTO op_bsrf_T0(void) |
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{
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env->pr = PARAM1; |
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env->delayed_pc = PARAM1 + T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_jsr_T0(void) |
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{
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env->pr = PARAM1; |
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env->delayed_pc = T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_rts(void) |
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{
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env->delayed_pc = env->pr; |
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RETURN(); |
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} |
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|
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void OPPROTO op_clrmac(void) |
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{
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env->mach = env->macl = 0;
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RETURN(); |
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} |
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void OPPROTO op_clrs(void) |
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{
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env->sr &= ~SR_S; |
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RETURN(); |
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} |
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void OPPROTO op_clrt(void) |
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{
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env->sr &= ~SR_T; |
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RETURN(); |
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} |
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void OPPROTO op_ldtlb(void) |
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{
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helper_ldtlb(); |
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RETURN(); |
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} |
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void OPPROTO op_sets(void) |
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{
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env->sr |= SR_S; |
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RETURN(); |
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} |
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void OPPROTO op_sett(void) |
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{
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env->sr |= SR_T; |
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RETURN(); |
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} |
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void OPPROTO op_frchg(void) |
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{
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env->fpscr ^= FPSCR_FR; |
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RETURN(); |
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} |
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|
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void OPPROTO op_fschg(void) |
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{
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env->fpscr ^= FPSCR_SZ; |
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RETURN(); |
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} |
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void OPPROTO op_rte(void) |
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{
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env->sr = env->ssr; |
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env->delayed_pc = env->spc; |
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RETURN(); |
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} |
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void OPPROTO op_addc_T0_T1(void) |
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{
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helper_addc_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_addv_T0_T1(void) |
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{
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helper_addv_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_eq_T0_T1(void) |
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{
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cond_t(T1 == T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_ge_T0_T1(void) |
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{
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cond_t((int32_t) T1 >= (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_gt_T0_T1(void) |
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{
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cond_t((int32_t) T1 > (int32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hi_T0_T1(void) |
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{
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cond_t((uint32_t) T1 > (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_hs_T0_T1(void) |
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{
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cond_t((uint32_t) T1 >= (uint32_t) T0); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_str_T0_T1(void) |
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{
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cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
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(T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
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(T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
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(T0 & 0xff000000) == (T1 & 0xff000000)); |
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RETURN(); |
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} |
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void OPPROTO op_tst_T0_T1(void) |
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{
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cond_t((T1 & T0) == 0);
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RETURN(); |
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} |
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void OPPROTO op_div0s_T0_T1(void) |
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{
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if (T1 & 0x80000000) |
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env->sr |= SR_Q; |
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else
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env->sr &= ~SR_Q; |
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if (T0 & 0x80000000) |
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env->sr |= SR_M; |
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else
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env->sr &= ~SR_M; |
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cond_t((T1 ^ T0) & 0x80000000);
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RETURN(); |
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} |
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void OPPROTO op_div0u(void) |
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{
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env->sr &= ~(SR_M | SR_Q | SR_T); |
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RETURN(); |
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} |
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void OPPROTO op_div1_T0_T1(void) |
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{
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helper_div1_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_dmulsl_T0_T1(void) |
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{
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helper_dmulsl_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_dmulul_T0_T1(void) |
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{
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helper_dmulul_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_macl_T0_T1(void) |
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{
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helper_macl_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_macw_T0_T1(void) |
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{
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helper_macw_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_mull_T0_T1(void) |
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{
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env->macl = (T0 * T1) & 0xffffffff;
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RETURN(); |
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} |
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void OPPROTO op_mulsw_T0_T1(void) |
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{
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env->macl = (int32_t)(int16_t) T0 *(int32_t)(int16_t) T1; |
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RETURN(); |
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} |
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void OPPROTO op_muluw_T0_T1(void) |
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{
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env->macl = (uint32_t)(uint16_t) T0 *(uint32_t)(uint16_t) T1; |
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RETURN(); |
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} |
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void OPPROTO op_negc_T0(void) |
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{
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helper_negc_T0(); |
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RETURN(); |
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} |
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|
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void OPPROTO op_shad_T0_T1(void) |
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{
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = (T1 & 0x80000000)? 0xffffffff : 0; |
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else
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T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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|
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void OPPROTO op_shld_T0_T1(void) |
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{
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if ((T0 & 0x80000000) == 0) |
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T1 <<= (T0 & 0x1f);
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else if ((T0 & 0x1f) == 0) |
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T1 = 0;
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else
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T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
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RETURN(); |
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} |
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void OPPROTO op_subc_T0_T1(void) |
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{
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helper_subc_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_subv_T0_T1(void) |
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{
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helper_subv_T0_T1(); |
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RETURN(); |
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} |
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void OPPROTO op_trapa(void) |
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{
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env->tra = PARAM1 << 2;
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env->exception_index = 0x160;
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do_raise_exception(); |
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RETURN(); |
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} |
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void OPPROTO op_cmp_pl_T0(void) |
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{
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cond_t((int32_t) T0 > 0);
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RETURN(); |
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} |
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|
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void OPPROTO op_cmp_pz_T0(void) |
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{
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cond_t((int32_t) T0 >= 0);
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RETURN(); |
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} |
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|
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void OPPROTO op_jmp_T0(void) |
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{
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env->delayed_pc = T0; |
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RETURN(); |
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} |
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|
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void OPPROTO op_ldcl_rMplus_rN_bank(void) |
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{
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env->gregs[PARAM2] = env->gregs[PARAM1]; |
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env->gregs[PARAM1] += 4;
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RETURN(); |
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} |
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void OPPROTO op_ldc_T0_sr(void) |
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{
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env->sr = T0 & 0x700083f3;
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RETURN(); |
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} |
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|
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void OPPROTO op_stc_sr_T0(void) |
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{
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T0 = env->sr; |
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RETURN(); |
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} |
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|
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#define LDSTOPS(target,load,store) \
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void OPPROTO op_##load##_T0_##target (void) \ |
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{ env ->target = T0; RETURN(); \
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} \ |
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void OPPROTO op_##store##_##target##_T0 (void) \ |
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{ T0 = env->target; RETURN(); \
|
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} \ |
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|
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LDSTOPS(gbr, ldc, stc) |
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LDSTOPS(vbr, ldc, stc) |
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LDSTOPS(ssr, ldc, stc) |
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LDSTOPS(spc, ldc, stc) |
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LDSTOPS(sgr, ldc, stc) |
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LDSTOPS(dbr, ldc, stc) |
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LDSTOPS(mach, lds, sts) |
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LDSTOPS(macl, lds, sts) |
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LDSTOPS(pr, lds, sts) |
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LDSTOPS(fpul, lds, sts) |
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|
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void OPPROTO op_lds_T0_fpscr(void) |
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{
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env->fpscr = T0 & 0x003fffff;
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env->fp_status.float_rounding_mode = T0 & 0x01 ?
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float_round_to_zero : float_round_nearest_even; |
| 399 |
|
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RETURN(); |
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} |
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|
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void OPPROTO op_sts_fpscr_T0(void) |
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{
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T0 = env->fpscr & 0x003fffff;
|
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RETURN(); |
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} |
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|
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void OPPROTO op_movt_rN(void) |
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{
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env->gregs[PARAM1] = env->sr & SR_T; |
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RETURN(); |
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} |
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|
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void OPPROTO op_rotcl_Rn(void) |
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{
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helper_rotcl(&env->gregs[PARAM1]); |
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RETURN(); |
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} |
| 420 |
|
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void OPPROTO op_rotcr_Rn(void) |
| 422 |
{
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helper_rotcr(&env->gregs[PARAM1]); |
| 424 |
RETURN(); |
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} |
| 426 |
|
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void OPPROTO op_rotl_Rn(void) |
| 428 |
{
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cond_t(env->gregs[PARAM1] & 0x80000000);
|
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env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
|
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RETURN(); |
| 432 |
} |
| 433 |
|
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void OPPROTO op_rotr_Rn(void) |
| 435 |
{
|
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cond_t(env->gregs[PARAM1] & 1);
|
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env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
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((env->sr & SR_T) ? 0x80000000 : 0); |
| 439 |
RETURN(); |
| 440 |
} |
| 441 |
|
| 442 |
void OPPROTO op_shal_Rn(void) |
| 443 |
{
|
| 444 |
cond_t(env->gregs[PARAM1] & 0x80000000);
|
| 445 |
env->gregs[PARAM1] <<= 1;
|
| 446 |
RETURN(); |
| 447 |
} |
| 448 |
|
| 449 |
void OPPROTO op_shar_Rn(void) |
| 450 |
{
|
| 451 |
cond_t(env->gregs[PARAM1] & 1);
|
| 452 |
*(int32_t *)&env->gregs[PARAM1] >>= 1;
|
| 453 |
RETURN(); |
| 454 |
} |
| 455 |
|
| 456 |
void OPPROTO op_shlr_Rn(void) |
| 457 |
{
|
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cond_t(env->gregs[PARAM1] & 1);
|
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env->gregs[PARAM1] >>= 1;
|
| 460 |
RETURN(); |
| 461 |
} |
| 462 |
|
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void OPPROTO op_fmov_frN_FT0(void) |
| 464 |
{
|
| 465 |
FT0 = env->fregs[PARAM1]; |
| 466 |
RETURN(); |
| 467 |
} |
| 468 |
|
| 469 |
void OPPROTO op_fmov_drN_DT0(void) |
| 470 |
{
|
| 471 |
CPU_DoubleU d; |
| 472 |
|
| 473 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
| 474 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
| 475 |
DT0 = d.d; |
| 476 |
RETURN(); |
| 477 |
} |
| 478 |
|
| 479 |
void OPPROTO op_fmov_frN_FT1(void) |
| 480 |
{
|
| 481 |
FT1 = env->fregs[PARAM1]; |
| 482 |
RETURN(); |
| 483 |
} |
| 484 |
|
| 485 |
void OPPROTO op_fmov_drN_DT1(void) |
| 486 |
{
|
| 487 |
CPU_DoubleU d; |
| 488 |
|
| 489 |
d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
| 490 |
d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
| 491 |
DT1 = d.d; |
| 492 |
RETURN(); |
| 493 |
} |
| 494 |
|
| 495 |
void OPPROTO op_fmov_FT0_frN(void) |
| 496 |
{
|
| 497 |
env->fregs[PARAM1] = FT0; |
| 498 |
RETURN(); |
| 499 |
} |
| 500 |
|
| 501 |
void OPPROTO op_fmov_DT0_drN(void) |
| 502 |
{
|
| 503 |
CPU_DoubleU d; |
| 504 |
|
| 505 |
d.d = DT0; |
| 506 |
*(uint32_t *)&env->fregs[PARAM1] = d.l.upper; |
| 507 |
*(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
|
| 508 |
RETURN(); |
| 509 |
} |
| 510 |
|
| 511 |
void OPPROTO op_fadd_FT(void) |
| 512 |
{
|
| 513 |
FT0 = float32_add(FT0, FT1, &env->fp_status); |
| 514 |
RETURN(); |
| 515 |
} |
| 516 |
|
| 517 |
void OPPROTO op_fadd_DT(void) |
| 518 |
{
|
| 519 |
DT0 = float64_add(DT0, DT1, &env->fp_status); |
| 520 |
RETURN(); |
| 521 |
} |
| 522 |
|
| 523 |
void OPPROTO op_fsub_FT(void) |
| 524 |
{
|
| 525 |
FT0 = float32_sub(FT0, FT1, &env->fp_status); |
| 526 |
RETURN(); |
| 527 |
} |
| 528 |
|
| 529 |
void OPPROTO op_fsub_DT(void) |
| 530 |
{
|
| 531 |
DT0 = float64_sub(DT0, DT1, &env->fp_status); |
| 532 |
RETURN(); |
| 533 |
} |
| 534 |
|
| 535 |
void OPPROTO op_fmul_FT(void) |
| 536 |
{
|
| 537 |
FT0 = float32_mul(FT0, FT1, &env->fp_status); |
| 538 |
RETURN(); |
| 539 |
} |
| 540 |
|
| 541 |
void OPPROTO op_fmul_DT(void) |
| 542 |
{
|
| 543 |
DT0 = float64_mul(DT0, DT1, &env->fp_status); |
| 544 |
RETURN(); |
| 545 |
} |
| 546 |
|
| 547 |
void OPPROTO op_fdiv_FT(void) |
| 548 |
{
|
| 549 |
FT0 = float32_div(FT0, FT1, &env->fp_status); |
| 550 |
RETURN(); |
| 551 |
} |
| 552 |
|
| 553 |
void OPPROTO op_fdiv_DT(void) |
| 554 |
{
|
| 555 |
DT0 = float64_div(DT0, DT1, &env->fp_status); |
| 556 |
RETURN(); |
| 557 |
} |
| 558 |
|
| 559 |
void OPPROTO op_fcmp_eq_FT(void) |
| 560 |
{
|
| 561 |
cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);
|
| 562 |
RETURN(); |
| 563 |
} |
| 564 |
|
| 565 |
void OPPROTO op_fcmp_eq_DT(void) |
| 566 |
{
|
| 567 |
cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);
|
| 568 |
RETURN(); |
| 569 |
} |
| 570 |
|
| 571 |
void OPPROTO op_fcmp_gt_FT(void) |
| 572 |
{
|
| 573 |
cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);
|
| 574 |
RETURN(); |
| 575 |
} |
| 576 |
|
| 577 |
void OPPROTO op_fcmp_gt_DT(void) |
| 578 |
{
|
| 579 |
cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);
|
| 580 |
RETURN(); |
| 581 |
} |
| 582 |
|
| 583 |
void OPPROTO op_float_FT(void) |
| 584 |
{
|
| 585 |
FT0 = int32_to_float32(env->fpul, &env->fp_status); |
| 586 |
RETURN(); |
| 587 |
} |
| 588 |
|
| 589 |
void OPPROTO op_float_DT(void) |
| 590 |
{
|
| 591 |
DT0 = int32_to_float64(env->fpul, &env->fp_status); |
| 592 |
RETURN(); |
| 593 |
} |
| 594 |
|
| 595 |
void OPPROTO op_ftrc_FT(void) |
| 596 |
{
|
| 597 |
env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status); |
| 598 |
RETURN(); |
| 599 |
} |
| 600 |
|
| 601 |
void OPPROTO op_ftrc_DT(void) |
| 602 |
{
|
| 603 |
env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status); |
| 604 |
RETURN(); |
| 605 |
} |
| 606 |
|
| 607 |
void OPPROTO op_fneg_frN(void) |
| 608 |
{
|
| 609 |
env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]); |
| 610 |
RETURN(); |
| 611 |
} |
| 612 |
|
| 613 |
void OPPROTO op_fabs_FT(void) |
| 614 |
{
|
| 615 |
FT0 = float32_abs(FT0); |
| 616 |
RETURN(); |
| 617 |
} |
| 618 |
|
| 619 |
void OPPROTO op_fabs_DT(void) |
| 620 |
{
|
| 621 |
DT0 = float64_abs(DT0); |
| 622 |
RETURN(); |
| 623 |
} |
| 624 |
|
| 625 |
void OPPROTO op_fcnvsd_FT_DT(void) |
| 626 |
{
|
| 627 |
DT0 = float32_to_float64(FT0, &env->fp_status); |
| 628 |
RETURN(); |
| 629 |
} |
| 630 |
|
| 631 |
void OPPROTO op_fcnvds_DT_FT(void) |
| 632 |
{
|
| 633 |
FT0 = float64_to_float32(DT0, &env->fp_status); |
| 634 |
RETURN(); |
| 635 |
} |
| 636 |
|
| 637 |
void OPPROTO op_fsqrt_FT(void) |
| 638 |
{
|
| 639 |
FT0 = float32_sqrt(FT0, &env->fp_status); |
| 640 |
RETURN(); |
| 641 |
} |
| 642 |
|
| 643 |
void OPPROTO op_fsqrt_DT(void) |
| 644 |
{
|
| 645 |
DT0 = float64_sqrt(DT0, &env->fp_status); |
| 646 |
RETURN(); |
| 647 |
} |
| 648 |
|
| 649 |
void OPPROTO op_fmov_T0_frN(void) |
| 650 |
{
|
| 651 |
*(uint32_t *)&env->fregs[PARAM1] = T0; |
| 652 |
RETURN(); |
| 653 |
} |
| 654 |
|
| 655 |
void OPPROTO op_dt_rN(void) |
| 656 |
{
|
| 657 |
cond_t((--env->gregs[PARAM1]) == 0);
|
| 658 |
RETURN(); |
| 659 |
} |
| 660 |
|
| 661 |
void OPPROTO op_tst_imm_rN(void) |
| 662 |
{
|
| 663 |
cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
| 664 |
RETURN(); |
| 665 |
} |
| 666 |
|
| 667 |
void OPPROTO op_movl_fpul_FT0(void) |
| 668 |
{
|
| 669 |
FT0 = *(float32 *)&env->fpul; |
| 670 |
RETURN(); |
| 671 |
} |
| 672 |
|
| 673 |
void OPPROTO op_movl_FT0_fpul(void) |
| 674 |
{
|
| 675 |
*(float32 *)&env->fpul = FT0; |
| 676 |
RETURN(); |
| 677 |
} |
| 678 |
|
| 679 |
void OPPROTO op_movl_imm_PC(void) |
| 680 |
{
|
| 681 |
env->pc = PARAM1; |
| 682 |
RETURN(); |
| 683 |
} |
| 684 |
|
| 685 |
void OPPROTO op_jT(void) |
| 686 |
{
|
| 687 |
if (env->sr & SR_T)
|
| 688 |
GOTO_LABEL_PARAM(1);
|
| 689 |
RETURN(); |
| 690 |
} |
| 691 |
|
| 692 |
void OPPROTO op_jdelayed(void) |
| 693 |
{
|
| 694 |
if (env->flags & DELAY_SLOT_TRUE) {
|
| 695 |
env->flags &= ~DELAY_SLOT_TRUE; |
| 696 |
GOTO_LABEL_PARAM(1);
|
| 697 |
} |
| 698 |
RETURN(); |
| 699 |
} |
| 700 |
|
| 701 |
void OPPROTO op_movl_delayed_pc_PC(void) |
| 702 |
{
|
| 703 |
env->pc = env->delayed_pc; |
| 704 |
RETURN(); |
| 705 |
} |
| 706 |
|
| 707 |
void OPPROTO op_addl_GBR_T0(void) |
| 708 |
{
|
| 709 |
T0 += env->gbr; |
| 710 |
RETURN(); |
| 711 |
} |
| 712 |
|
| 713 |
void OPPROTO op_tst_imm_T0(void) |
| 714 |
{
|
| 715 |
cond_t((T0 & PARAM1) == 0);
|
| 716 |
RETURN(); |
| 717 |
} |
| 718 |
|
| 719 |
void OPPROTO op_raise_illegal_instruction(void) |
| 720 |
{
|
| 721 |
env->exception_index = 0x180;
|
| 722 |
do_raise_exception(); |
| 723 |
RETURN(); |
| 724 |
} |
| 725 |
|
| 726 |
void OPPROTO op_raise_slot_illegal_instruction(void) |
| 727 |
{
|
| 728 |
env->exception_index = 0x1a0;
|
| 729 |
do_raise_exception(); |
| 730 |
RETURN(); |
| 731 |
} |
| 732 |
|
| 733 |
void OPPROTO op_debug(void) |
| 734 |
{
|
| 735 |
env->exception_index = EXCP_DEBUG; |
| 736 |
cpu_loop_exit(); |
| 737 |
} |
| 738 |
|
| 739 |
void OPPROTO op_sleep(void) |
| 740 |
{
|
| 741 |
env->halted = 1;
|
| 742 |
env->exception_index = EXCP_HLT; |
| 743 |
cpu_loop_exit(); |
| 744 |
} |
| 745 |
|
| 746 |
/* Load and store */
|
| 747 |
#define MEMSUFFIX _raw
|
| 748 |
#include "op_mem.c" |
| 749 |
#undef MEMSUFFIX
|
| 750 |
#if !defined(CONFIG_USER_ONLY)
|
| 751 |
#define MEMSUFFIX _user
|
| 752 |
#include "op_mem.c" |
| 753 |
#undef MEMSUFFIX
|
| 754 |
|
| 755 |
#define MEMSUFFIX _kernel
|
| 756 |
#include "op_mem.c" |
| 757 |
#undef MEMSUFFIX
|
| 758 |
#endif
|