Revision 563e3c6e
| b/hw/parallel.c | ||
|---|---|---|
| 129 | 129 |
{
|
| 130 | 130 |
ParallelState *s = opaque; |
| 131 | 131 |
uint8_t parm = val; |
| 132 |
int dir; |
|
| 132 | 133 |
|
| 133 | 134 |
/* Sometimes programs do several writes for timing purposes on old |
| 134 | 135 |
HW. Take care not to waste time on writes that do nothing. */ |
| ... | ... | |
| 154 | 155 |
if (s->control == val) |
| 155 | 156 |
return; |
| 156 | 157 |
pdebug("wc%02x\n", val);
|
| 158 |
|
|
| 159 |
if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
|
|
| 160 |
if (val & PARA_CTR_DIR) {
|
|
| 161 |
dir = 1; |
|
| 162 |
} else {
|
|
| 163 |
dir = 0; |
|
| 164 |
} |
|
| 165 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
|
| 166 |
parm &= ~PARA_CTR_DIR; |
|
| 167 |
} |
|
| 168 |
|
|
| 157 | 169 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
| 158 | 170 |
s->control = val; |
| 159 | 171 |
break; |
| b/qemu-char.h | ||
|---|---|---|
| 27 | 27 |
#define CHR_IOCTL_PP_EPP_READ 9 |
| 28 | 28 |
#define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 |
| 29 | 29 |
#define CHR_IOCTL_PP_EPP_WRITE 11 |
| 30 |
#define CHR_IOCTL_PP_DATA_DIR 12 |
|
| 30 | 31 |
|
| 31 | 32 |
#define CHR_IOCTL_SERIAL_SET_TIOCM 12 |
| 32 | 33 |
#define CHR_IOCTL_SERIAL_GET_TIOCM 13 |
| b/vl.c | ||
|---|---|---|
| 2835 | 2835 |
return -ENOTSUP; |
| 2836 | 2836 |
*(uint8_t *)arg = b; |
| 2837 | 2837 |
break; |
| 2838 |
case CHR_IOCTL_PP_DATA_DIR: |
|
| 2839 |
if (ioctl(fd, PPDATADIR, (int *)arg) < 0) |
|
| 2840 |
return -ENOTSUP; |
|
| 2841 |
break; |
|
| 2838 | 2842 |
case CHR_IOCTL_PP_EPP_READ_ADDR: |
| 2839 | 2843 |
if (pp_hw_mode(drv, IEEE1284_MODE_EPP|IEEE1284_ADDR)) {
|
| 2840 | 2844 |
struct ParallelIOArg *parg = arg; |
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