root / tcg / sparc / tcg-target.c @ 56f4927e
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1 | 8289b279 | blueswir1 | /*
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2 | 8289b279 | blueswir1 | * Tiny Code Generator for QEMU
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3 | 8289b279 | blueswir1 | *
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4 | 8289b279 | blueswir1 | * Copyright (c) 2008 Fabrice Bellard
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5 | 8289b279 | blueswir1 | *
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6 | 8289b279 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8289b279 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 8289b279 | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 8289b279 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8289b279 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 8289b279 | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 8289b279 | blueswir1 | *
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13 | 8289b279 | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 8289b279 | blueswir1 | * all copies or substantial portions of the Software.
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15 | 8289b279 | blueswir1 | *
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16 | 8289b279 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8289b279 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8289b279 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8289b279 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8289b279 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8289b279 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8289b279 | blueswir1 | * THE SOFTWARE.
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23 | 8289b279 | blueswir1 | */
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24 | 8289b279 | blueswir1 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
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26 | 8289b279 | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | 8289b279 | blueswir1 | "%g0",
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28 | 8289b279 | blueswir1 | "%g1",
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29 | 8289b279 | blueswir1 | "%g2",
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30 | 8289b279 | blueswir1 | "%g3",
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31 | 8289b279 | blueswir1 | "%g4",
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32 | 8289b279 | blueswir1 | "%g5",
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33 | 8289b279 | blueswir1 | "%g6",
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34 | 8289b279 | blueswir1 | "%g7",
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35 | 8289b279 | blueswir1 | "%o0",
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36 | 8289b279 | blueswir1 | "%o1",
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37 | 8289b279 | blueswir1 | "%o2",
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38 | 8289b279 | blueswir1 | "%o3",
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39 | 8289b279 | blueswir1 | "%o4",
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40 | 8289b279 | blueswir1 | "%o5",
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41 | 8289b279 | blueswir1 | "%o6",
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42 | 8289b279 | blueswir1 | "%o7",
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43 | 8289b279 | blueswir1 | "%l0",
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44 | 8289b279 | blueswir1 | "%l1",
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45 | 8289b279 | blueswir1 | "%l2",
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46 | 8289b279 | blueswir1 | "%l3",
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47 | 8289b279 | blueswir1 | "%l4",
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48 | 8289b279 | blueswir1 | "%l5",
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49 | 8289b279 | blueswir1 | "%l6",
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50 | 8289b279 | blueswir1 | "%l7",
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51 | 8289b279 | blueswir1 | "%i0",
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52 | 8289b279 | blueswir1 | "%i1",
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53 | 8289b279 | blueswir1 | "%i2",
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54 | 8289b279 | blueswir1 | "%i3",
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55 | 8289b279 | blueswir1 | "%i4",
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56 | 8289b279 | blueswir1 | "%i5",
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57 | 8289b279 | blueswir1 | "%i6",
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58 | 8289b279 | blueswir1 | "%i7",
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59 | 8289b279 | blueswir1 | }; |
60 | d4a9eb1f | blueswir1 | #endif
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61 | 8289b279 | blueswir1 | |
62 | 0954d0d9 | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
63 | 8289b279 | blueswir1 | TCG_REG_L0, |
64 | 8289b279 | blueswir1 | TCG_REG_L1, |
65 | 8289b279 | blueswir1 | TCG_REG_L2, |
66 | 8289b279 | blueswir1 | TCG_REG_L3, |
67 | 8289b279 | blueswir1 | TCG_REG_L4, |
68 | 8289b279 | blueswir1 | TCG_REG_L5, |
69 | 8289b279 | blueswir1 | TCG_REG_L6, |
70 | 8289b279 | blueswir1 | TCG_REG_L7, |
71 | 8289b279 | blueswir1 | TCG_REG_I0, |
72 | 8289b279 | blueswir1 | TCG_REG_I1, |
73 | 8289b279 | blueswir1 | TCG_REG_I2, |
74 | 8289b279 | blueswir1 | TCG_REG_I3, |
75 | 8289b279 | blueswir1 | TCG_REG_I4, |
76 | 8289b279 | blueswir1 | }; |
77 | 8289b279 | blueswir1 | |
78 | 8289b279 | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
79 | 8289b279 | blueswir1 | TCG_REG_O0, |
80 | 8289b279 | blueswir1 | TCG_REG_O1, |
81 | 8289b279 | blueswir1 | TCG_REG_O2, |
82 | 8289b279 | blueswir1 | TCG_REG_O3, |
83 | 8289b279 | blueswir1 | TCG_REG_O4, |
84 | 8289b279 | blueswir1 | TCG_REG_O5, |
85 | 8289b279 | blueswir1 | }; |
86 | 8289b279 | blueswir1 | |
87 | 8289b279 | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
88 | 8289b279 | blueswir1 | TCG_REG_O0, |
89 | 8289b279 | blueswir1 | TCG_REG_O1, |
90 | 8289b279 | blueswir1 | }; |
91 | 8289b279 | blueswir1 | |
92 | 57e49b40 | blueswir1 | static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
93 | f5ef6aac | blueswir1 | { |
94 | 57e49b40 | blueswir1 | return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
95 | 57e49b40 | blueswir1 | >> (sizeof(tcg_target_long) * 8 - bits)) == val; |
96 | 57e49b40 | blueswir1 | } |
97 | 57e49b40 | blueswir1 | |
98 | 57e49b40 | blueswir1 | static inline int check_fit_i32(uint32_t val, unsigned int bits) |
99 | 57e49b40 | blueswir1 | { |
100 | 57e49b40 | blueswir1 | return ((val << (32 - bits)) >> (32 - bits)) == val; |
101 | f5ef6aac | blueswir1 | } |
102 | f5ef6aac | blueswir1 | |
103 | 8289b279 | blueswir1 | static void patch_reloc(uint8_t *code_ptr, int type, |
104 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
105 | 8289b279 | blueswir1 | { |
106 | f54b3f92 | aurel32 | value += addend; |
107 | 8289b279 | blueswir1 | switch (type) {
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108 | 8289b279 | blueswir1 | case R_SPARC_32:
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109 | 8289b279 | blueswir1 | if (value != (uint32_t)value)
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110 | 8289b279 | blueswir1 | tcg_abort(); |
111 | 8289b279 | blueswir1 | *(uint32_t *)code_ptr = value; |
112 | 8289b279 | blueswir1 | break;
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113 | f5ef6aac | blueswir1 | case R_SPARC_WDISP22:
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114 | f5ef6aac | blueswir1 | value -= (long)code_ptr;
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115 | f5ef6aac | blueswir1 | value >>= 2;
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116 | 57e49b40 | blueswir1 | if (!check_fit_tl(value, 22)) |
117 | f5ef6aac | blueswir1 | tcg_abort(); |
118 | f5ef6aac | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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119 | f5ef6aac | blueswir1 | break;
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120 | 1da92db2 | blueswir1 | case R_SPARC_WDISP19:
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121 | 1da92db2 | blueswir1 | value -= (long)code_ptr;
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122 | 1da92db2 | blueswir1 | value >>= 2;
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123 | 1da92db2 | blueswir1 | if (!check_fit_tl(value, 19)) |
124 | 1da92db2 | blueswir1 | tcg_abort(); |
125 | 1da92db2 | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
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126 | 1da92db2 | blueswir1 | break;
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127 | 8289b279 | blueswir1 | default:
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128 | 8289b279 | blueswir1 | tcg_abort(); |
129 | 8289b279 | blueswir1 | } |
130 | 8289b279 | blueswir1 | } |
131 | 8289b279 | blueswir1 | |
132 | 8289b279 | blueswir1 | /* maximum number of register used for input function arguments */
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133 | 8289b279 | blueswir1 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
134 | 8289b279 | blueswir1 | { |
135 | 8289b279 | blueswir1 | return 6; |
136 | 8289b279 | blueswir1 | } |
137 | 8289b279 | blueswir1 | |
138 | 8289b279 | blueswir1 | /* parse target specific constraints */
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139 | 8289b279 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
140 | 8289b279 | blueswir1 | { |
141 | 8289b279 | blueswir1 | const char *ct_str; |
142 | 8289b279 | blueswir1 | |
143 | 8289b279 | blueswir1 | ct_str = *pct_str; |
144 | 8289b279 | blueswir1 | switch (ct_str[0]) { |
145 | 8289b279 | blueswir1 | case 'r': |
146 | 8289b279 | blueswir1 | case 'L': /* qemu_ld/st constraint */ |
147 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_REG; |
148 | 8289b279 | blueswir1 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
149 | 53c37487 | blueswir1 | // Helper args
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150 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
151 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); |
152 | 53c37487 | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); |
153 | 8289b279 | blueswir1 | break;
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154 | 8289b279 | blueswir1 | case 'I': |
155 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S11; |
156 | 8289b279 | blueswir1 | break;
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157 | 8289b279 | blueswir1 | case 'J': |
158 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S13; |
159 | 8289b279 | blueswir1 | break;
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160 | 8289b279 | blueswir1 | default:
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161 | 8289b279 | blueswir1 | return -1; |
162 | 8289b279 | blueswir1 | } |
163 | 8289b279 | blueswir1 | ct_str++; |
164 | 8289b279 | blueswir1 | *pct_str = ct_str; |
165 | 8289b279 | blueswir1 | return 0; |
166 | 8289b279 | blueswir1 | } |
167 | 8289b279 | blueswir1 | |
168 | 8289b279 | blueswir1 | /* test if a constant matches the constraint */
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169 | 8289b279 | blueswir1 | static inline int tcg_target_const_match(tcg_target_long val, |
170 | 8289b279 | blueswir1 | const TCGArgConstraint *arg_ct)
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171 | 8289b279 | blueswir1 | { |
172 | 8289b279 | blueswir1 | int ct;
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173 | 8289b279 | blueswir1 | |
174 | 8289b279 | blueswir1 | ct = arg_ct->ct; |
175 | 8289b279 | blueswir1 | if (ct & TCG_CT_CONST)
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176 | 8289b279 | blueswir1 | return 1; |
177 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) |
178 | 8289b279 | blueswir1 | return 1; |
179 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) |
180 | 8289b279 | blueswir1 | return 1; |
181 | 8289b279 | blueswir1 | else
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182 | 8289b279 | blueswir1 | return 0; |
183 | 8289b279 | blueswir1 | } |
184 | 8289b279 | blueswir1 | |
185 | 8289b279 | blueswir1 | #define INSN_OP(x) ((x) << 30) |
186 | 8289b279 | blueswir1 | #define INSN_OP2(x) ((x) << 22) |
187 | 8289b279 | blueswir1 | #define INSN_OP3(x) ((x) << 19) |
188 | 8289b279 | blueswir1 | #define INSN_OPF(x) ((x) << 5) |
189 | 8289b279 | blueswir1 | #define INSN_RD(x) ((x) << 25) |
190 | 8289b279 | blueswir1 | #define INSN_RS1(x) ((x) << 14) |
191 | 8289b279 | blueswir1 | #define INSN_RS2(x) (x)
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192 | 8384dd67 | blueswir1 | #define INSN_ASI(x) ((x) << 5) |
193 | 8289b279 | blueswir1 | |
194 | 8289b279 | blueswir1 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
195 | 1da92db2 | blueswir1 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
196 | b3db8758 | blueswir1 | #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
197 | 8289b279 | blueswir1 | |
198 | b3db8758 | blueswir1 | #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
199 | cf7c2ca5 | blueswir1 | #define COND_N 0x0 |
200 | cf7c2ca5 | blueswir1 | #define COND_E 0x1 |
201 | cf7c2ca5 | blueswir1 | #define COND_LE 0x2 |
202 | cf7c2ca5 | blueswir1 | #define COND_L 0x3 |
203 | cf7c2ca5 | blueswir1 | #define COND_LEU 0x4 |
204 | cf7c2ca5 | blueswir1 | #define COND_CS 0x5 |
205 | cf7c2ca5 | blueswir1 | #define COND_NEG 0x6 |
206 | cf7c2ca5 | blueswir1 | #define COND_VS 0x7 |
207 | b3db8758 | blueswir1 | #define COND_A 0x8 |
208 | cf7c2ca5 | blueswir1 | #define COND_NE 0x9 |
209 | cf7c2ca5 | blueswir1 | #define COND_G 0xa |
210 | cf7c2ca5 | blueswir1 | #define COND_GE 0xb |
211 | cf7c2ca5 | blueswir1 | #define COND_GU 0xc |
212 | cf7c2ca5 | blueswir1 | #define COND_CC 0xd |
213 | cf7c2ca5 | blueswir1 | #define COND_POS 0xe |
214 | cf7c2ca5 | blueswir1 | #define COND_VC 0xf |
215 | b3db8758 | blueswir1 | #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
216 | 8289b279 | blueswir1 | |
217 | 8289b279 | blueswir1 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
218 | 8289b279 | blueswir1 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
219 | 8289b279 | blueswir1 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
220 | 9a7f3228 | blueswir1 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
221 | 8289b279 | blueswir1 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
222 | f5ef6aac | blueswir1 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
223 | f5ef6aac | blueswir1 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
224 | 8289b279 | blueswir1 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
225 | 8289b279 | blueswir1 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
226 | 8289b279 | blueswir1 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
227 | 8289b279 | blueswir1 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
228 | 8289b279 | blueswir1 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
229 | 8289b279 | blueswir1 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
230 | 8289b279 | blueswir1 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
231 | 8289b279 | blueswir1 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
232 | 8289b279 | blueswir1 | |
233 | 8289b279 | blueswir1 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
234 | 8289b279 | blueswir1 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
235 | 8289b279 | blueswir1 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
236 | 8289b279 | blueswir1 | |
237 | 8289b279 | blueswir1 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
238 | 8289b279 | blueswir1 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
239 | 8289b279 | blueswir1 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
240 | 8289b279 | blueswir1 | |
241 | 8289b279 | blueswir1 | #define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
242 | 8289b279 | blueswir1 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
243 | 8289b279 | blueswir1 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
244 | 8289b279 | blueswir1 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
245 | 8289b279 | blueswir1 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
246 | 8289b279 | blueswir1 | #define CALL INSN_OP(1) |
247 | 8289b279 | blueswir1 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
248 | 8289b279 | blueswir1 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
249 | 8289b279 | blueswir1 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
250 | 8289b279 | blueswir1 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
251 | 8289b279 | blueswir1 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
252 | 8289b279 | blueswir1 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
253 | 8289b279 | blueswir1 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
254 | 8289b279 | blueswir1 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
255 | 8289b279 | blueswir1 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
256 | 8289b279 | blueswir1 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
257 | 8289b279 | blueswir1 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
258 | 8384dd67 | blueswir1 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
259 | 8384dd67 | blueswir1 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
260 | 8384dd67 | blueswir1 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
261 | 8384dd67 | blueswir1 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
262 | 8384dd67 | blueswir1 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
263 | 8384dd67 | blueswir1 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
264 | 8384dd67 | blueswir1 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
265 | 8384dd67 | blueswir1 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
266 | 8384dd67 | blueswir1 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
267 | 8384dd67 | blueswir1 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
268 | 8384dd67 | blueswir1 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
269 | 8384dd67 | blueswir1 | |
270 | 8384dd67 | blueswir1 | #ifndef ASI_PRIMARY_LITTLE
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271 | 8384dd67 | blueswir1 | #define ASI_PRIMARY_LITTLE 0x88 |
272 | 8384dd67 | blueswir1 | #endif
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273 | 8289b279 | blueswir1 | |
274 | 26cc915c | blueswir1 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
275 | 26cc915c | blueswir1 | int op)
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276 | 26cc915c | blueswir1 | { |
277 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
278 | 26cc915c | blueswir1 | INSN_RS2(rs2)); |
279 | 26cc915c | blueswir1 | } |
280 | 26cc915c | blueswir1 | |
281 | 6f41b777 | blueswir1 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, |
282 | 6f41b777 | blueswir1 | uint32_t offset, int op)
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283 | 26cc915c | blueswir1 | { |
284 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
285 | 26cc915c | blueswir1 | INSN_IMM13(offset)); |
286 | 26cc915c | blueswir1 | } |
287 | 26cc915c | blueswir1 | |
288 | 8289b279 | blueswir1 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
289 | 8289b279 | blueswir1 | { |
290 | 26cc915c | blueswir1 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
291 | 26cc915c | blueswir1 | } |
292 | 26cc915c | blueswir1 | |
293 | 26cc915c | blueswir1 | static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
294 | 26cc915c | blueswir1 | { |
295 | 26cc915c | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
296 | 8289b279 | blueswir1 | } |
297 | 8289b279 | blueswir1 | |
298 | b101234a | blueswir1 | static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
299 | b101234a | blueswir1 | { |
300 | b101234a | blueswir1 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
301 | b101234a | blueswir1 | } |
302 | b101234a | blueswir1 | |
303 | b101234a | blueswir1 | static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) |
304 | 8289b279 | blueswir1 | { |
305 | 4a09aa89 | Richard Henderson | if (check_fit_tl(arg, 13)) |
306 | b101234a | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
307 | 8289b279 | blueswir1 | else {
|
308 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
309 | 8289b279 | blueswir1 | if (arg & 0x3ff) |
310 | b101234a | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
311 | 8289b279 | blueswir1 | } |
312 | 8289b279 | blueswir1 | } |
313 | 8289b279 | blueswir1 | |
314 | b101234a | blueswir1 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
315 | b101234a | blueswir1 | int ret, tcg_target_long arg)
|
316 | b101234a | blueswir1 | { |
317 | 43172207 | Richard Henderson | /* All 32-bit constants, as well as 64-bit constants with
|
318 | 43172207 | Richard Henderson | no high bits set go through movi_imm32. */
|
319 | 43172207 | Richard Henderson | if (TCG_TARGET_REG_BITS == 32 |
320 | 43172207 | Richard Henderson | || type == TCG_TYPE_I32 |
321 | 43172207 | Richard Henderson | || (arg & ~(tcg_target_long)0xffffffff) == 0) { |
322 | 43172207 | Richard Henderson | tcg_out_movi_imm32(s, ret, arg); |
323 | 43172207 | Richard Henderson | } else if (check_fit_tl(arg, 13)) { |
324 | 43172207 | Richard Henderson | /* A 13-bit constant sign-extended to 64-bits. */
|
325 | 43172207 | Richard Henderson | tcg_out_movi_imm13(s, ret, arg); |
326 | 43172207 | Richard Henderson | } else if (check_fit_tl(arg, 32)) { |
327 | 43172207 | Richard Henderson | /* A 32-bit constant sign-extended to 64-bits. */
|
328 | 43172207 | Richard Henderson | tcg_out_sethi(s, ret, ~arg); |
329 | 43172207 | Richard Henderson | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); |
330 | 43172207 | Richard Henderson | } else {
|
331 | 43172207 | Richard Henderson | tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
|
332 | d795eb86 | blueswir1 | tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
|
333 | b101234a | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
334 | d795eb86 | blueswir1 | tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR); |
335 | 6f41b777 | blueswir1 | } |
336 | b101234a | blueswir1 | } |
337 | b101234a | blueswir1 | |
338 | 8289b279 | blueswir1 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
339 | 8289b279 | blueswir1 | tcg_target_long arg) |
340 | 8289b279 | blueswir1 | { |
341 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
342 | 8289b279 | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
343 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
344 | 8289b279 | blueswir1 | } |
345 | 8289b279 | blueswir1 | |
346 | b3db8758 | blueswir1 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
347 | b3db8758 | blueswir1 | tcg_target_long arg) |
348 | b3db8758 | blueswir1 | { |
349 | b101234a | blueswir1 | if (!check_fit_tl(arg, 10)) |
350 | b101234a | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
|
351 | a212ea75 | Richard Henderson | if (TCG_TARGET_REG_BITS == 64) { |
352 | a212ea75 | Richard Henderson | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
353 | a212ea75 | Richard Henderson | INSN_IMM13(arg & 0x3ff));
|
354 | a212ea75 | Richard Henderson | } else {
|
355 | a212ea75 | Richard Henderson | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
356 | a212ea75 | Richard Henderson | INSN_IMM13(arg & 0x3ff));
|
357 | a212ea75 | Richard Henderson | } |
358 | b3db8758 | blueswir1 | } |
359 | b3db8758 | blueswir1 | |
360 | 8289b279 | blueswir1 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
361 | 8289b279 | blueswir1 | { |
362 | 57e49b40 | blueswir1 | if (check_fit_tl(offset, 13)) |
363 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
364 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
365 | cf7c2ca5 | blueswir1 | else {
|
366 | cf7c2ca5 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
367 | cf7c2ca5 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
368 | cf7c2ca5 | blueswir1 | INSN_RS2(addr)); |
369 | cf7c2ca5 | blueswir1 | } |
370 | 8289b279 | blueswir1 | } |
371 | 8289b279 | blueswir1 | |
372 | 8384dd67 | blueswir1 | static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr, |
373 | 8384dd67 | blueswir1 | int offset, int op, int asi) |
374 | 8384dd67 | blueswir1 | { |
375 | 8384dd67 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
376 | 8384dd67 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
377 | 8384dd67 | blueswir1 | INSN_ASI(asi) | INSN_RS2(addr)); |
378 | 8384dd67 | blueswir1 | } |
379 | 8384dd67 | blueswir1 | |
380 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
381 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
382 | 8289b279 | blueswir1 | { |
383 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
384 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDUW); |
385 | 7d551702 | blueswir1 | else
|
386 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDX); |
387 | 8289b279 | blueswir1 | } |
388 | 8289b279 | blueswir1 | |
389 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
390 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
391 | 8289b279 | blueswir1 | { |
392 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
393 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STW); |
394 | 7d551702 | blueswir1 | else
|
395 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STX); |
396 | 8289b279 | blueswir1 | } |
397 | 8289b279 | blueswir1 | |
398 | 8289b279 | blueswir1 | static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
399 | 8289b279 | blueswir1 | { |
400 | 8289b279 | blueswir1 | if (val == 0 || val == -1) |
401 | 8289b279 | blueswir1 | tcg_out32(s, WRY | INSN_IMM13(val)); |
402 | 8289b279 | blueswir1 | else
|
403 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
404 | 8289b279 | blueswir1 | } |
405 | 8289b279 | blueswir1 | |
406 | 8289b279 | blueswir1 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
407 | 8289b279 | blueswir1 | { |
408 | 8289b279 | blueswir1 | if (val != 0) { |
409 | 57e49b40 | blueswir1 | if (check_fit_tl(val, 13)) |
410 | 8289b279 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
411 | f5ef6aac | blueswir1 | else {
|
412 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val); |
413 | f5ef6aac | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD); |
414 | f5ef6aac | blueswir1 | } |
415 | 8289b279 | blueswir1 | } |
416 | 8289b279 | blueswir1 | } |
417 | 8289b279 | blueswir1 | |
418 | 53c37487 | blueswir1 | static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val) |
419 | 53c37487 | blueswir1 | { |
420 | 53c37487 | blueswir1 | if (val != 0) { |
421 | 53c37487 | blueswir1 | if (check_fit_tl(val, 13)) |
422 | 53c37487 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_AND); |
423 | 53c37487 | blueswir1 | else {
|
424 | 53c37487 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val); |
425 | 53c37487 | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND); |
426 | 53c37487 | blueswir1 | } |
427 | 53c37487 | blueswir1 | } |
428 | 53c37487 | blueswir1 | } |
429 | 53c37487 | blueswir1 | |
430 | 8289b279 | blueswir1 | static inline void tcg_out_nop(TCGContext *s) |
431 | 8289b279 | blueswir1 | { |
432 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_G0, 0);
|
433 | 8289b279 | blueswir1 | } |
434 | 8289b279 | blueswir1 | |
435 | 1da92db2 | blueswir1 | static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index) |
436 | cf7c2ca5 | blueswir1 | { |
437 | cf7c2ca5 | blueswir1 | int32_t val; |
438 | cf7c2ca5 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
439 | cf7c2ca5 | blueswir1 | |
440 | cf7c2ca5 | blueswir1 | if (l->has_value) {
|
441 | cf7c2ca5 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
442 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) |
443 | cf7c2ca5 | blueswir1 | | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); |
444 | f5ef6aac | blueswir1 | } else {
|
445 | f5ef6aac | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
|
446 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0)); |
447 | f5ef6aac | blueswir1 | } |
448 | cf7c2ca5 | blueswir1 | } |
449 | cf7c2ca5 | blueswir1 | |
450 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
451 | 1da92db2 | blueswir1 | static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index) |
452 | 1da92db2 | blueswir1 | { |
453 | 1da92db2 | blueswir1 | int32_t val; |
454 | 1da92db2 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
455 | 1da92db2 | blueswir1 | |
456 | 1da92db2 | blueswir1 | if (l->has_value) {
|
457 | 1da92db2 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
458 | 1da92db2 | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | |
459 | 1da92db2 | blueswir1 | (0x5 << 19) | |
460 | 1da92db2 | blueswir1 | INSN_OFF19(l->u.value - (unsigned long)s->code_ptr))); |
461 | 1da92db2 | blueswir1 | } else {
|
462 | 1da92db2 | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
|
463 | 1da92db2 | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | |
464 | 1da92db2 | blueswir1 | (0x5 << 19) | 0)); |
465 | 1da92db2 | blueswir1 | } |
466 | 1da92db2 | blueswir1 | } |
467 | 1da92db2 | blueswir1 | #endif
|
468 | 1da92db2 | blueswir1 | |
469 | cf7c2ca5 | blueswir1 | static const uint8_t tcg_cond_to_bcond[10] = { |
470 | cf7c2ca5 | blueswir1 | [TCG_COND_EQ] = COND_E, |
471 | cf7c2ca5 | blueswir1 | [TCG_COND_NE] = COND_NE, |
472 | cf7c2ca5 | blueswir1 | [TCG_COND_LT] = COND_L, |
473 | cf7c2ca5 | blueswir1 | [TCG_COND_GE] = COND_GE, |
474 | cf7c2ca5 | blueswir1 | [TCG_COND_LE] = COND_LE, |
475 | cf7c2ca5 | blueswir1 | [TCG_COND_GT] = COND_G, |
476 | cf7c2ca5 | blueswir1 | [TCG_COND_LTU] = COND_CS, |
477 | cf7c2ca5 | blueswir1 | [TCG_COND_GEU] = COND_CC, |
478 | cf7c2ca5 | blueswir1 | [TCG_COND_LEU] = COND_LEU, |
479 | cf7c2ca5 | blueswir1 | [TCG_COND_GTU] = COND_GU, |
480 | cf7c2ca5 | blueswir1 | }; |
481 | cf7c2ca5 | blueswir1 | |
482 | 56f4927e | Richard Henderson | static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const) |
483 | 56f4927e | Richard Henderson | { |
484 | 56f4927e | Richard Henderson | if (c2const)
|
485 | 56f4927e | Richard Henderson | tcg_out_arithi(s, TCG_REG_G0, c1, c2, ARITH_SUBCC); |
486 | 56f4927e | Richard Henderson | else
|
487 | 56f4927e | Richard Henderson | tcg_out_arith(s, TCG_REG_G0, c1, c2, ARITH_SUBCC); |
488 | 56f4927e | Richard Henderson | } |
489 | 56f4927e | Richard Henderson | |
490 | 1da92db2 | blueswir1 | static void tcg_out_brcond_i32(TCGContext *s, int cond, |
491 | 1da92db2 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
492 | 1da92db2 | blueswir1 | int label_index)
|
493 | cf7c2ca5 | blueswir1 | { |
494 | 56f4927e | Richard Henderson | tcg_out_cmp(s, arg1, arg2, const_arg2); |
495 | 1da92db2 | blueswir1 | tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index); |
496 | cf7c2ca5 | blueswir1 | tcg_out_nop(s); |
497 | cf7c2ca5 | blueswir1 | } |
498 | cf7c2ca5 | blueswir1 | |
499 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
500 | 1da92db2 | blueswir1 | static void tcg_out_brcond_i64(TCGContext *s, int cond, |
501 | 1da92db2 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
502 | 1da92db2 | blueswir1 | int label_index)
|
503 | 1da92db2 | blueswir1 | { |
504 | 56f4927e | Richard Henderson | tcg_out_cmp(s, arg1, arg2, const_arg2); |
505 | 1da92db2 | blueswir1 | tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index); |
506 | 1da92db2 | blueswir1 | tcg_out_nop(s); |
507 | 1da92db2 | blueswir1 | } |
508 | 56f4927e | Richard Henderson | #else
|
509 | 56f4927e | Richard Henderson | static void tcg_out_brcond2_i32(TCGContext *s, int cond, |
510 | 56f4927e | Richard Henderson | TCGArg al, TCGArg ah, |
511 | 56f4927e | Richard Henderson | TCGArg bl, int blconst,
|
512 | 56f4927e | Richard Henderson | TCGArg bh, int bhconst, int label_dest) |
513 | 56f4927e | Richard Henderson | { |
514 | 56f4927e | Richard Henderson | int cc, label_next = gen_new_label();
|
515 | 56f4927e | Richard Henderson | |
516 | 56f4927e | Richard Henderson | tcg_out_cmp(s, ah, bh, bhconst); |
517 | 56f4927e | Richard Henderson | |
518 | 56f4927e | Richard Henderson | /* Note that we fill one of the delay slots with the second compare. */
|
519 | 56f4927e | Richard Henderson | switch (cond) {
|
520 | 56f4927e | Richard Henderson | case TCG_COND_EQ:
|
521 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
|
522 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_next); |
523 | 56f4927e | Richard Henderson | tcg_out_cmp(s, al, bl, blconst); |
524 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
|
525 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
526 | 56f4927e | Richard Henderson | break;
|
527 | 56f4927e | Richard Henderson | |
528 | 56f4927e | Richard Henderson | case TCG_COND_NE:
|
529 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
|
530 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
531 | 56f4927e | Richard Henderson | tcg_out_cmp(s, al, bl, blconst); |
532 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
533 | 56f4927e | Richard Henderson | break;
|
534 | 56f4927e | Richard Henderson | |
535 | 56f4927e | Richard Henderson | default:
|
536 | 56f4927e | Richard Henderson | /* ??? One could fairly easily special-case 64-bit unsigned
|
537 | 56f4927e | Richard Henderson | compares against 32-bit zero-extended constants. For instance,
|
538 | 56f4927e | Richard Henderson | we know that (unsigned)AH < 0 is false and need not emit it.
|
539 | 56f4927e | Richard Henderson | Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
|
540 | 56f4927e | Richard Henderson | second branch will never be taken. */
|
541 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
|
542 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
543 | 56f4927e | Richard Henderson | tcg_out_nop(s); |
544 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
|
545 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_next); |
546 | 56f4927e | Richard Henderson | tcg_out_cmp(s, al, bl, blconst); |
547 | 56f4927e | Richard Henderson | cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
|
548 | 56f4927e | Richard Henderson | tcg_out_branch_i32(s, cc, label_dest); |
549 | 56f4927e | Richard Henderson | break;
|
550 | 56f4927e | Richard Henderson | } |
551 | 56f4927e | Richard Henderson | tcg_out_nop(s); |
552 | 56f4927e | Richard Henderson | |
553 | 56f4927e | Richard Henderson | tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr); |
554 | 56f4927e | Richard Henderson | } |
555 | 1da92db2 | blueswir1 | #endif
|
556 | 1da92db2 | blueswir1 | |
557 | 7d551702 | blueswir1 | /* Generate global QEMU prologue and epilogue code */
|
558 | 7d551702 | blueswir1 | void tcg_target_qemu_prologue(TCGContext *s)
|
559 | b3db8758 | blueswir1 | { |
560 | b3db8758 | blueswir1 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
561 | b3db8758 | blueswir1 | INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
562 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | |
563 | 7d551702 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
564 | 7d551702 | blueswir1 | tcg_out_nop(s); |
565 | b3db8758 | blueswir1 | } |
566 | b3db8758 | blueswir1 | |
567 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
568 | f5ef6aac | blueswir1 | |
569 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
570 | f5ef6aac | blueswir1 | |
571 | 9a7f3228 | blueswir1 | static const void * const qemu_ld_helpers[4] = { |
572 | f5ef6aac | blueswir1 | __ldb_mmu, |
573 | f5ef6aac | blueswir1 | __ldw_mmu, |
574 | f5ef6aac | blueswir1 | __ldl_mmu, |
575 | f5ef6aac | blueswir1 | __ldq_mmu, |
576 | f5ef6aac | blueswir1 | }; |
577 | f5ef6aac | blueswir1 | |
578 | 9a7f3228 | blueswir1 | static const void * const qemu_st_helpers[4] = { |
579 | f5ef6aac | blueswir1 | __stb_mmu, |
580 | f5ef6aac | blueswir1 | __stw_mmu, |
581 | f5ef6aac | blueswir1 | __stl_mmu, |
582 | f5ef6aac | blueswir1 | __stq_mmu, |
583 | f5ef6aac | blueswir1 | }; |
584 | f5ef6aac | blueswir1 | #endif
|
585 | f5ef6aac | blueswir1 | |
586 | bffe1431 | blueswir1 | #if TARGET_LONG_BITS == 32 |
587 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDUW
|
588 | bffe1431 | blueswir1 | #else
|
589 | bffe1431 | blueswir1 | #define TARGET_LD_OP LDX
|
590 | bffe1431 | blueswir1 | #endif
|
591 | bffe1431 | blueswir1 | |
592 | 9d0efc88 | blueswir1 | #if TARGET_PHYS_ADDR_BITS == 32 |
593 | 9d0efc88 | blueswir1 | #define TARGET_ADDEND_LD_OP LDUW
|
594 | 9d0efc88 | blueswir1 | #else
|
595 | 9d0efc88 | blueswir1 | #define TARGET_ADDEND_LD_OP LDX
|
596 | 9d0efc88 | blueswir1 | #endif
|
597 | 9d0efc88 | blueswir1 | |
598 | bffe1431 | blueswir1 | #ifdef __arch64__
|
599 | bffe1431 | blueswir1 | #define HOST_LD_OP LDX
|
600 | bffe1431 | blueswir1 | #define HOST_ST_OP STX
|
601 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLLX
|
602 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRAX
|
603 | bffe1431 | blueswir1 | #else
|
604 | bffe1431 | blueswir1 | #define HOST_LD_OP LDUW
|
605 | bffe1431 | blueswir1 | #define HOST_ST_OP STW
|
606 | bffe1431 | blueswir1 | #define HOST_SLL_OP SHIFT_SLL
|
607 | bffe1431 | blueswir1 | #define HOST_SRA_OP SHIFT_SRA
|
608 | bffe1431 | blueswir1 | #endif
|
609 | bffe1431 | blueswir1 | |
610 | f5ef6aac | blueswir1 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
611 | f5ef6aac | blueswir1 | int opc)
|
612 | f5ef6aac | blueswir1 | { |
613 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
614 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
615 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
616 | f5ef6aac | blueswir1 | #endif
|
617 | f5ef6aac | blueswir1 | |
618 | f5ef6aac | blueswir1 | data_reg = *args++; |
619 | f5ef6aac | blueswir1 | addr_reg = *args++; |
620 | f5ef6aac | blueswir1 | mem_index = *args; |
621 | f5ef6aac | blueswir1 | s_bits = opc & 3;
|
622 | f5ef6aac | blueswir1 | |
623 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
624 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
625 | 56fc64df | blueswir1 | arg2 = TCG_REG_O2; |
626 | f5ef6aac | blueswir1 | |
627 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
628 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
629 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
630 | f5ef6aac | blueswir1 | SHIFT_SRL); |
631 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
632 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
633 | f5ef6aac | blueswir1 | ARITH_AND); |
634 | f5ef6aac | blueswir1 | |
635 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
636 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
637 | f5ef6aac | blueswir1 | |
638 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
639 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
640 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_read));
|
641 | 53c37487 | blueswir1 | |
642 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
643 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
644 | f5ef6aac | blueswir1 | |
645 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
646 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
647 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
648 | f5ef6aac | blueswir1 | |
649 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
650 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
651 | f5ef6aac | blueswir1 | |
652 | f5ef6aac | blueswir1 | /* will become:
|
653 | 1da92db2 | blueswir1 | be label1
|
654 | 1da92db2 | blueswir1 | or
|
655 | 1da92db2 | blueswir1 | be,pt %xcc label1 */
|
656 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
657 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
658 | f5ef6aac | blueswir1 | |
659 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
660 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
661 | f5ef6aac | blueswir1 | |
662 | bffe1431 | blueswir1 | /* mov */
|
663 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); |
664 | bffe1431 | blueswir1 | |
665 | f5ef6aac | blueswir1 | /* XXX: move that code at the end of the TB */
|
666 | 53c37487 | blueswir1 | /* qemu_ld_helper[s_bits](arg0, arg1) */
|
667 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] |
668 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
669 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
670 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
671 | bffe1431 | blueswir1 | global registers */
|
672 | bffe1431 | blueswir1 | // delay slot
|
673 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
674 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
675 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
676 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
677 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
678 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
679 | f5ef6aac | blueswir1 | |
680 | 53c37487 | blueswir1 | /* data_reg = sign_extend(arg0) */
|
681 | f5ef6aac | blueswir1 | switch(opc) {
|
682 | f5ef6aac | blueswir1 | case 0 | 4: |
683 | 53c37487 | blueswir1 | /* sll arg0, 24/56, data_reg */
|
684 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8, |
685 | bffe1431 | blueswir1 | HOST_SLL_OP); |
686 | 53c37487 | blueswir1 | /* sra data_reg, 24/56, data_reg */
|
687 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
688 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP); |
689 | f5ef6aac | blueswir1 | break;
|
690 | f5ef6aac | blueswir1 | case 1 | 4: |
691 | 53c37487 | blueswir1 | /* sll arg0, 16/48, data_reg */
|
692 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, arg0, |
693 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP); |
694 | 53c37487 | blueswir1 | /* sra data_reg, 16/48, data_reg */
|
695 | 56fc64df | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, |
696 | bffe1431 | blueswir1 | (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP); |
697 | f5ef6aac | blueswir1 | break;
|
698 | f5ef6aac | blueswir1 | case 2 | 4: |
699 | 53c37487 | blueswir1 | /* sll arg0, 32, data_reg */
|
700 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
|
701 | 53c37487 | blueswir1 | /* sra data_reg, 32, data_reg */
|
702 | bffe1431 | blueswir1 | tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
|
703 | f5ef6aac | blueswir1 | break;
|
704 | f5ef6aac | blueswir1 | case 0: |
705 | f5ef6aac | blueswir1 | case 1: |
706 | f5ef6aac | blueswir1 | case 2: |
707 | f5ef6aac | blueswir1 | case 3: |
708 | f5ef6aac | blueswir1 | default:
|
709 | f5ef6aac | blueswir1 | /* mov */
|
710 | 53c37487 | blueswir1 | tcg_out_mov(s, data_reg, arg0); |
711 | f5ef6aac | blueswir1 | break;
|
712 | f5ef6aac | blueswir1 | } |
713 | f5ef6aac | blueswir1 | |
714 | f5ef6aac | blueswir1 | /* will become:
|
715 | f5ef6aac | blueswir1 | ba label2 */
|
716 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
717 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
718 | f5ef6aac | blueswir1 | |
719 | 53c37487 | blueswir1 | /* nop (delay slot */
|
720 | 53c37487 | blueswir1 | tcg_out_nop(s); |
721 | 53c37487 | blueswir1 | |
722 | f5ef6aac | blueswir1 | /* label1: */
|
723 | 1da92db2 | blueswir1 | #if TARGET_LONG_BITS == 32 |
724 | 1da92db2 | blueswir1 | /* be label1 */
|
725 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
726 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
727 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
728 | 1da92db2 | blueswir1 | #else
|
729 | 1da92db2 | blueswir1 | /* be,pt %xcc label1 */
|
730 | 1da92db2 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) | |
731 | 1da92db2 | blueswir1 | (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr - |
732 | 1da92db2 | blueswir1 | (unsigned long)label1_ptr)); |
733 | 1da92db2 | blueswir1 | #endif
|
734 | f5ef6aac | blueswir1 | |
735 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
736 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
737 | 9d0efc88 | blueswir1 | offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP); |
738 | 90cbed46 | blueswir1 | |
739 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
740 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
741 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
742 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
743 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
744 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
745 | 90cbed46 | blueswir1 | #else
|
746 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
747 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
748 | 90cbed46 | blueswir1 | #endif
|
749 | 90cbed46 | blueswir1 | |
750 | f5ef6aac | blueswir1 | #else
|
751 | 56fc64df | blueswir1 | arg0 = addr_reg; |
752 | f5ef6aac | blueswir1 | #endif
|
753 | f5ef6aac | blueswir1 | |
754 | f5ef6aac | blueswir1 | switch(opc) {
|
755 | f5ef6aac | blueswir1 | case 0: |
756 | 56fc64df | blueswir1 | /* ldub [arg0], data_reg */
|
757 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
|
758 | f5ef6aac | blueswir1 | break;
|
759 | f5ef6aac | blueswir1 | case 0 | 4: |
760 | 56fc64df | blueswir1 | /* ldsb [arg0], data_reg */
|
761 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
|
762 | f5ef6aac | blueswir1 | break;
|
763 | f5ef6aac | blueswir1 | case 1: |
764 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
765 | 56fc64df | blueswir1 | /* lduh [arg0], data_reg */
|
766 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
|
767 | 8384dd67 | blueswir1 | #else
|
768 | 56fc64df | blueswir1 | /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
769 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
770 | 8384dd67 | blueswir1 | #endif
|
771 | f5ef6aac | blueswir1 | break;
|
772 | f5ef6aac | blueswir1 | case 1 | 4: |
773 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
774 | 56fc64df | blueswir1 | /* ldsh [arg0], data_reg */
|
775 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
|
776 | 8384dd67 | blueswir1 | #else
|
777 | 56fc64df | blueswir1 | /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
778 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
779 | 8384dd67 | blueswir1 | #endif
|
780 | f5ef6aac | blueswir1 | break;
|
781 | f5ef6aac | blueswir1 | case 2: |
782 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
783 | 56fc64df | blueswir1 | /* lduw [arg0], data_reg */
|
784 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
|
785 | 8384dd67 | blueswir1 | #else
|
786 | 56fc64df | blueswir1 | /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
787 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
788 | 8384dd67 | blueswir1 | #endif
|
789 | f5ef6aac | blueswir1 | break;
|
790 | f5ef6aac | blueswir1 | case 2 | 4: |
791 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
792 | 56fc64df | blueswir1 | /* ldsw [arg0], data_reg */
|
793 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
|
794 | 8384dd67 | blueswir1 | #else
|
795 | 56fc64df | blueswir1 | /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
796 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
797 | 8384dd67 | blueswir1 | #endif
|
798 | f5ef6aac | blueswir1 | break;
|
799 | f5ef6aac | blueswir1 | case 3: |
800 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
801 | 56fc64df | blueswir1 | /* ldx [arg0], data_reg */
|
802 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, LDX);
|
803 | 8384dd67 | blueswir1 | #else
|
804 | 56fc64df | blueswir1 | /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
|
805 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
806 | 8384dd67 | blueswir1 | #endif
|
807 | f5ef6aac | blueswir1 | break;
|
808 | f5ef6aac | blueswir1 | default:
|
809 | f5ef6aac | blueswir1 | tcg_abort(); |
810 | f5ef6aac | blueswir1 | } |
811 | f5ef6aac | blueswir1 | |
812 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
813 | f5ef6aac | blueswir1 | /* label2: */
|
814 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
815 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
816 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
817 | f5ef6aac | blueswir1 | #endif
|
818 | f5ef6aac | blueswir1 | } |
819 | f5ef6aac | blueswir1 | |
820 | f5ef6aac | blueswir1 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
821 | f5ef6aac | blueswir1 | int opc)
|
822 | f5ef6aac | blueswir1 | { |
823 | 56fc64df | blueswir1 | int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
|
824 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
825 | 53c37487 | blueswir1 | uint32_t *label1_ptr, *label2_ptr; |
826 | f5ef6aac | blueswir1 | #endif
|
827 | f5ef6aac | blueswir1 | |
828 | f5ef6aac | blueswir1 | data_reg = *args++; |
829 | f5ef6aac | blueswir1 | addr_reg = *args++; |
830 | f5ef6aac | blueswir1 | mem_index = *args; |
831 | f5ef6aac | blueswir1 | |
832 | f5ef6aac | blueswir1 | s_bits = opc; |
833 | f5ef6aac | blueswir1 | |
834 | 53c37487 | blueswir1 | arg0 = TCG_REG_O0; |
835 | 53c37487 | blueswir1 | arg1 = TCG_REG_O1; |
836 | 53c37487 | blueswir1 | arg2 = TCG_REG_O2; |
837 | f5ef6aac | blueswir1 | |
838 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
839 | 56fc64df | blueswir1 | /* srl addr_reg, x, arg1 */
|
840 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
841 | f5ef6aac | blueswir1 | SHIFT_SRL); |
842 | 53c37487 | blueswir1 | |
843 | 56fc64df | blueswir1 | /* and addr_reg, x, arg0 */
|
844 | 56fc64df | blueswir1 | tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
845 | f5ef6aac | blueswir1 | ARITH_AND); |
846 | f5ef6aac | blueswir1 | |
847 | 56fc64df | blueswir1 | /* and arg1, x, arg1 */
|
848 | 56fc64df | blueswir1 | tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
849 | f5ef6aac | blueswir1 | |
850 | 56fc64df | blueswir1 | /* add arg1, x, arg1 */
|
851 | 56fc64df | blueswir1 | tcg_out_addi(s, arg1, offsetof(CPUState, |
852 | 56fc64df | blueswir1 | tlb_table[mem_index][0].addr_write));
|
853 | f5ef6aac | blueswir1 | |
854 | 56fc64df | blueswir1 | /* add env, arg1, arg1 */
|
855 | 56fc64df | blueswir1 | tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD); |
856 | f5ef6aac | blueswir1 | |
857 | 56fc64df | blueswir1 | /* ld [arg1], arg2 */
|
858 | bffe1431 | blueswir1 | tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) | |
859 | 56fc64df | blueswir1 | INSN_RS2(TCG_REG_G0)); |
860 | 53c37487 | blueswir1 | |
861 | 56fc64df | blueswir1 | /* subcc arg0, arg2, %g0 */
|
862 | 56fc64df | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC); |
863 | f5ef6aac | blueswir1 | |
864 | f5ef6aac | blueswir1 | /* will become:
|
865 | 1da92db2 | blueswir1 | be label1
|
866 | 1da92db2 | blueswir1 | or
|
867 | 1da92db2 | blueswir1 | be,pt %xcc label1 */
|
868 | 53c37487 | blueswir1 | label1_ptr = (uint32_t *)s->code_ptr; |
869 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
870 | f5ef6aac | blueswir1 | |
871 | 53c37487 | blueswir1 | /* mov (delay slot) */
|
872 | 53c37487 | blueswir1 | tcg_out_mov(s, arg0, addr_reg); |
873 | 53c37487 | blueswir1 | |
874 | 53c37487 | blueswir1 | /* mov */
|
875 | 56fc64df | blueswir1 | tcg_out_mov(s, arg1, data_reg); |
876 | 53c37487 | blueswir1 | |
877 | bffe1431 | blueswir1 | /* mov */
|
878 | bffe1431 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); |
879 | bffe1431 | blueswir1 | |
880 | 53c37487 | blueswir1 | /* XXX: move that code at the end of the TB */
|
881 | 53c37487 | blueswir1 | /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
|
882 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] |
883 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
884 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
885 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
886 | bffe1431 | blueswir1 | global registers */
|
887 | bffe1431 | blueswir1 | // delay slot
|
888 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
889 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
890 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
891 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
892 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
893 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
894 | f5ef6aac | blueswir1 | |
895 | f5ef6aac | blueswir1 | /* will become:
|
896 | f5ef6aac | blueswir1 | ba label2 */
|
897 | 53c37487 | blueswir1 | label2_ptr = (uint32_t *)s->code_ptr; |
898 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
899 | f5ef6aac | blueswir1 | |
900 | 53c37487 | blueswir1 | /* nop (delay slot) */
|
901 | 53c37487 | blueswir1 | tcg_out_nop(s); |
902 | 53c37487 | blueswir1 | |
903 | 1da92db2 | blueswir1 | #if TARGET_LONG_BITS == 32 |
904 | 1da92db2 | blueswir1 | /* be label1 */
|
905 | 53c37487 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) | |
906 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
907 | 53c37487 | blueswir1 | (unsigned long)label1_ptr)); |
908 | 1da92db2 | blueswir1 | #else
|
909 | 1da92db2 | blueswir1 | /* be,pt %xcc label1 */
|
910 | 1da92db2 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) | |
911 | 1da92db2 | blueswir1 | (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr - |
912 | 1da92db2 | blueswir1 | (unsigned long)label1_ptr)); |
913 | 1da92db2 | blueswir1 | #endif
|
914 | f5ef6aac | blueswir1 | |
915 | 56fc64df | blueswir1 | /* ld [arg1 + x], arg1 */
|
916 | 56fc64df | blueswir1 | tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) - |
917 | 9d0efc88 | blueswir1 | offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP); |
918 | 53c37487 | blueswir1 | |
919 | 90cbed46 | blueswir1 | #if TARGET_LONG_BITS == 32 |
920 | 90cbed46 | blueswir1 | /* and addr_reg, x, arg0 */
|
921 | 90cbed46 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
|
922 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND); |
923 | 90cbed46 | blueswir1 | /* add arg0, arg1, arg0 */
|
924 | 90cbed46 | blueswir1 | tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD); |
925 | 90cbed46 | blueswir1 | #else
|
926 | 56fc64df | blueswir1 | /* add addr_reg, arg1, arg0 */
|
927 | 56fc64df | blueswir1 | tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD); |
928 | 90cbed46 | blueswir1 | #endif
|
929 | 90cbed46 | blueswir1 | |
930 | f5ef6aac | blueswir1 | #else
|
931 | 56fc64df | blueswir1 | arg0 = addr_reg; |
932 | f5ef6aac | blueswir1 | #endif
|
933 | f5ef6aac | blueswir1 | |
934 | f5ef6aac | blueswir1 | switch(opc) {
|
935 | f5ef6aac | blueswir1 | case 0: |
936 | 56fc64df | blueswir1 | /* stb data_reg, [arg0] */
|
937 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STB);
|
938 | f5ef6aac | blueswir1 | break;
|
939 | f5ef6aac | blueswir1 | case 1: |
940 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
941 | 56fc64df | blueswir1 | /* sth data_reg, [arg0] */
|
942 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STH);
|
943 | 8384dd67 | blueswir1 | #else
|
944 | 56fc64df | blueswir1 | /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
945 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
|
946 | 8384dd67 | blueswir1 | #endif
|
947 | f5ef6aac | blueswir1 | break;
|
948 | f5ef6aac | blueswir1 | case 2: |
949 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
950 | 56fc64df | blueswir1 | /* stw data_reg, [arg0] */
|
951 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STW);
|
952 | 8384dd67 | blueswir1 | #else
|
953 | 56fc64df | blueswir1 | /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
954 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
|
955 | 8384dd67 | blueswir1 | #endif
|
956 | f5ef6aac | blueswir1 | break;
|
957 | f5ef6aac | blueswir1 | case 3: |
958 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
959 | 56fc64df | blueswir1 | /* stx data_reg, [arg0] */
|
960 | 56fc64df | blueswir1 | tcg_out_ldst(s, data_reg, arg0, 0, STX);
|
961 | 8384dd67 | blueswir1 | #else
|
962 | 56fc64df | blueswir1 | /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
|
963 | 56fc64df | blueswir1 | tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
|
964 | 8384dd67 | blueswir1 | #endif
|
965 | f5ef6aac | blueswir1 | break;
|
966 | f5ef6aac | blueswir1 | default:
|
967 | f5ef6aac | blueswir1 | tcg_abort(); |
968 | f5ef6aac | blueswir1 | } |
969 | f5ef6aac | blueswir1 | |
970 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
971 | f5ef6aac | blueswir1 | /* label2: */
|
972 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
973 | 53c37487 | blueswir1 | INSN_OFF22((unsigned long)s->code_ptr - |
974 | 53c37487 | blueswir1 | (unsigned long)label2_ptr)); |
975 | f5ef6aac | blueswir1 | #endif
|
976 | f5ef6aac | blueswir1 | } |
977 | f5ef6aac | blueswir1 | |
978 | 8289b279 | blueswir1 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
979 | 8289b279 | blueswir1 | const int *const_args) |
980 | 8289b279 | blueswir1 | { |
981 | 8289b279 | blueswir1 | int c;
|
982 | 8289b279 | blueswir1 | |
983 | 8289b279 | blueswir1 | switch (opc) {
|
984 | 8289b279 | blueswir1 | case INDEX_op_exit_tb:
|
985 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
986 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
987 | 8289b279 | blueswir1 | INSN_IMM13(8));
|
988 | b3db8758 | blueswir1 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
989 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
990 | 8289b279 | blueswir1 | break;
|
991 | 8289b279 | blueswir1 | case INDEX_op_goto_tb:
|
992 | 8289b279 | blueswir1 | if (s->tb_jmp_offset) {
|
993 | 8289b279 | blueswir1 | /* direct jump method */
|
994 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000); |
995 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
996 | cf7c2ca5 | blueswir1 | INSN_IMM13((args[0] & 0x1fff))); |
997 | 8289b279 | blueswir1 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
998 | 8289b279 | blueswir1 | } else {
|
999 | 8289b279 | blueswir1 | /* indirect jump method */
|
1000 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
1001 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
1002 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
1003 | 8289b279 | blueswir1 | } |
1004 | 53cd9273 | blueswir1 | tcg_out_nop(s); |
1005 | 8289b279 | blueswir1 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
1006 | 8289b279 | blueswir1 | break;
|
1007 | 8289b279 | blueswir1 | case INDEX_op_call:
|
1008 | bffe1431 | blueswir1 | if (const_args[0]) |
1009 | bffe1431 | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
1010 | bffe1431 | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
1011 | bffe1431 | blueswir1 | & 0x3fffffff));
|
1012 | bffe1431 | blueswir1 | else {
|
1013 | bffe1431 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, |
1014 | bffe1431 | blueswir1 | (tcg_target_long)(s->tb_next + args[0]));
|
1015 | bffe1431 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | |
1016 | bffe1431 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
1017 | 8289b279 | blueswir1 | } |
1018 | bffe1431 | blueswir1 | /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
|
1019 | bffe1431 | blueswir1 | global registers */
|
1020 | bffe1431 | blueswir1 | // delay slot
|
1021 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
1022 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
1023 | f843e528 | blueswir1 | sizeof(long), HOST_ST_OP); |
1024 | bffe1431 | blueswir1 | tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK, |
1025 | f843e528 | blueswir1 | TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE - |
1026 | f843e528 | blueswir1 | sizeof(long), HOST_LD_OP); |
1027 | 8289b279 | blueswir1 | break;
|
1028 | 8289b279 | blueswir1 | case INDEX_op_jmp:
|
1029 | 8289b279 | blueswir1 | case INDEX_op_br:
|
1030 | 1da92db2 | blueswir1 | tcg_out_branch_i32(s, COND_A, args[0]);
|
1031 | f5ef6aac | blueswir1 | tcg_out_nop(s); |
1032 | 8289b279 | blueswir1 | break;
|
1033 | 8289b279 | blueswir1 | case INDEX_op_movi_i32:
|
1034 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
1035 | 8289b279 | blueswir1 | break;
|
1036 | 8289b279 | blueswir1 | |
1037 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1038 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
1039 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:) \
|
1040 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i64:)
|
1041 | 8289b279 | blueswir1 | #else
|
1042 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
1043 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:)
|
1044 | 8289b279 | blueswir1 | #endif
|
1045 | 8289b279 | blueswir1 | OP_32_64(ld8u); |
1046 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
1047 | 8289b279 | blueswir1 | break;
|
1048 | 8289b279 | blueswir1 | OP_32_64(ld8s); |
1049 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
1050 | 8289b279 | blueswir1 | break;
|
1051 | 8289b279 | blueswir1 | OP_32_64(ld16u); |
1052 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
1053 | 8289b279 | blueswir1 | break;
|
1054 | 8289b279 | blueswir1 | OP_32_64(ld16s); |
1055 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
1056 | 8289b279 | blueswir1 | break;
|
1057 | 8289b279 | blueswir1 | case INDEX_op_ld_i32:
|
1058 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1059 | 53cd9273 | blueswir1 | case INDEX_op_ld32u_i64:
|
1060 | 8289b279 | blueswir1 | #endif
|
1061 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
1062 | 8289b279 | blueswir1 | break;
|
1063 | 8289b279 | blueswir1 | OP_32_64(st8); |
1064 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
1065 | 8289b279 | blueswir1 | break;
|
1066 | 8289b279 | blueswir1 | OP_32_64(st16); |
1067 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
1068 | 8289b279 | blueswir1 | break;
|
1069 | 8289b279 | blueswir1 | case INDEX_op_st_i32:
|
1070 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1071 | 53cd9273 | blueswir1 | case INDEX_op_st32_i64:
|
1072 | 8289b279 | blueswir1 | #endif
|
1073 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
1074 | 8289b279 | blueswir1 | break;
|
1075 | 53cd9273 | blueswir1 | OP_32_64(add); |
1076 | 53cd9273 | blueswir1 | c = ARITH_ADD; |
1077 | 53cd9273 | blueswir1 | goto gen_arith32;
|
1078 | 8289b279 | blueswir1 | OP_32_64(sub); |
1079 | 8289b279 | blueswir1 | c = ARITH_SUB; |
1080 | 8289b279 | blueswir1 | goto gen_arith32;
|
1081 | 8289b279 | blueswir1 | OP_32_64(and); |
1082 | 8289b279 | blueswir1 | c = ARITH_AND; |
1083 | 8289b279 | blueswir1 | goto gen_arith32;
|
1084 | 8289b279 | blueswir1 | OP_32_64(or); |
1085 | 8289b279 | blueswir1 | c = ARITH_OR; |
1086 | 8289b279 | blueswir1 | goto gen_arith32;
|
1087 | 8289b279 | blueswir1 | OP_32_64(xor); |
1088 | 8289b279 | blueswir1 | c = ARITH_XOR; |
1089 | 8289b279 | blueswir1 | goto gen_arith32;
|
1090 | 8289b279 | blueswir1 | case INDEX_op_shl_i32:
|
1091 | 8289b279 | blueswir1 | c = SHIFT_SLL; |
1092 | 8289b279 | blueswir1 | goto gen_arith32;
|
1093 | 8289b279 | blueswir1 | case INDEX_op_shr_i32:
|
1094 | 8289b279 | blueswir1 | c = SHIFT_SRL; |
1095 | 8289b279 | blueswir1 | goto gen_arith32;
|
1096 | 8289b279 | blueswir1 | case INDEX_op_sar_i32:
|
1097 | 8289b279 | blueswir1 | c = SHIFT_SRA; |
1098 | 8289b279 | blueswir1 | goto gen_arith32;
|
1099 | 8289b279 | blueswir1 | case INDEX_op_mul_i32:
|
1100 | 8289b279 | blueswir1 | c = ARITH_UMUL; |
1101 | 8289b279 | blueswir1 | goto gen_arith32;
|
1102 | 8289b279 | blueswir1 | case INDEX_op_div2_i32:
|
1103 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
1104 | 8289b279 | blueswir1 | c = ARITH_SDIVX; |
1105 | 8289b279 | blueswir1 | goto gen_arith32;
|
1106 | 8289b279 | blueswir1 | #else
|
1107 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
1108 | 8289b279 | blueswir1 | c = ARITH_SDIV; |
1109 | 8289b279 | blueswir1 | goto gen_arith32;
|
1110 | 8289b279 | blueswir1 | #endif
|
1111 | 8289b279 | blueswir1 | case INDEX_op_divu2_i32:
|
1112 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
1113 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1114 | 8289b279 | blueswir1 | goto gen_arith32;
|
1115 | 8289b279 | blueswir1 | #else
|
1116 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
1117 | 8289b279 | blueswir1 | c = ARITH_UDIV; |
1118 | 8289b279 | blueswir1 | goto gen_arith32;
|
1119 | 8289b279 | blueswir1 | #endif
|
1120 | 8289b279 | blueswir1 | |
1121 | 8289b279 | blueswir1 | case INDEX_op_brcond_i32:
|
1122 | 1da92db2 | blueswir1 | tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1], |
1123 | 1da92db2 | blueswir1 | args[3]);
|
1124 | 8289b279 | blueswir1 | break;
|
1125 | 56f4927e | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
1126 | 56f4927e | Richard Henderson | case INDEX_op_brcond2_i32:
|
1127 | 56f4927e | Richard Henderson | tcg_out_brcond2_i32(s, args[4], args[0], args[1], |
1128 | 56f4927e | Richard Henderson | args[2], const_args[2], |
1129 | 56f4927e | Richard Henderson | args[3], const_args[3], args[5]); |
1130 | 56f4927e | Richard Henderson | break;
|
1131 | 56f4927e | Richard Henderson | #endif
|
1132 | 8289b279 | blueswir1 | |
1133 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8u:
|
1134 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0);
|
1135 | 8289b279 | blueswir1 | break;
|
1136 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8s:
|
1137 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0 | 4); |
1138 | 8289b279 | blueswir1 | break;
|
1139 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16u:
|
1140 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1);
|
1141 | 8289b279 | blueswir1 | break;
|
1142 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16s:
|
1143 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1 | 4); |
1144 | 8289b279 | blueswir1 | break;
|
1145 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32u:
|
1146 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2);
|
1147 | 8289b279 | blueswir1 | break;
|
1148 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32s:
|
1149 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2 | 4); |
1150 | 8289b279 | blueswir1 | break;
|
1151 | 8289b279 | blueswir1 | case INDEX_op_qemu_st8:
|
1152 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 0);
|
1153 | 8289b279 | blueswir1 | break;
|
1154 | 8289b279 | blueswir1 | case INDEX_op_qemu_st16:
|
1155 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 1);
|
1156 | 8289b279 | blueswir1 | break;
|
1157 | 8289b279 | blueswir1 | case INDEX_op_qemu_st32:
|
1158 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 2);
|
1159 | 8289b279 | blueswir1 | break;
|
1160 | 8289b279 | blueswir1 | |
1161 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1162 | 8289b279 | blueswir1 | case INDEX_op_movi_i64:
|
1163 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
1164 | 8289b279 | blueswir1 | break;
|
1165 | 53cd9273 | blueswir1 | case INDEX_op_ld32s_i64:
|
1166 | 53cd9273 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
1167 | 53cd9273 | blueswir1 | break;
|
1168 | 8289b279 | blueswir1 | case INDEX_op_ld_i64:
|
1169 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
1170 | 8289b279 | blueswir1 | break;
|
1171 | 8289b279 | blueswir1 | case INDEX_op_st_i64:
|
1172 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
1173 | 8289b279 | blueswir1 | break;
|
1174 | 8289b279 | blueswir1 | case INDEX_op_shl_i64:
|
1175 | 8289b279 | blueswir1 | c = SHIFT_SLLX; |
1176 | 8289b279 | blueswir1 | goto gen_arith32;
|
1177 | 8289b279 | blueswir1 | case INDEX_op_shr_i64:
|
1178 | 8289b279 | blueswir1 | c = SHIFT_SRLX; |
1179 | 8289b279 | blueswir1 | goto gen_arith32;
|
1180 | 8289b279 | blueswir1 | case INDEX_op_sar_i64:
|
1181 | 8289b279 | blueswir1 | c = SHIFT_SRAX; |
1182 | 8289b279 | blueswir1 | goto gen_arith32;
|
1183 | 8289b279 | blueswir1 | case INDEX_op_mul_i64:
|
1184 | 8289b279 | blueswir1 | c = ARITH_MULX; |
1185 | 8289b279 | blueswir1 | goto gen_arith32;
|
1186 | 8289b279 | blueswir1 | case INDEX_op_div2_i64:
|
1187 | 53cd9273 | blueswir1 | c = ARITH_SDIVX; |
1188 | 8289b279 | blueswir1 | goto gen_arith32;
|
1189 | 8289b279 | blueswir1 | case INDEX_op_divu2_i64:
|
1190 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1191 | 8289b279 | blueswir1 | goto gen_arith32;
|
1192 | 8289b279 | blueswir1 | |
1193 | 8289b279 | blueswir1 | case INDEX_op_brcond_i64:
|
1194 | 1da92db2 | blueswir1 | tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1], |
1195 | 1da92db2 | blueswir1 | args[3]);
|
1196 | 8289b279 | blueswir1 | break;
|
1197 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld64:
|
1198 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 3);
|
1199 | 8289b279 | blueswir1 | break;
|
1200 | 8289b279 | blueswir1 | case INDEX_op_qemu_st64:
|
1201 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 3);
|
1202 | 8289b279 | blueswir1 | break;
|
1203 | 8289b279 | blueswir1 | |
1204 | 8289b279 | blueswir1 | #endif
|
1205 | 53cd9273 | blueswir1 | gen_arith32:
|
1206 | 53cd9273 | blueswir1 | if (const_args[2]) { |
1207 | 53cd9273 | blueswir1 | tcg_out_arithi(s, args[0], args[1], args[2], c); |
1208 | 53cd9273 | blueswir1 | } else {
|
1209 | 53cd9273 | blueswir1 | tcg_out_arith(s, args[0], args[1], args[2], c); |
1210 | 53cd9273 | blueswir1 | } |
1211 | 53cd9273 | blueswir1 | break;
|
1212 | 53cd9273 | blueswir1 | |
1213 | 8289b279 | blueswir1 | default:
|
1214 | 8289b279 | blueswir1 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
1215 | 8289b279 | blueswir1 | tcg_abort(); |
1216 | 8289b279 | blueswir1 | } |
1217 | 8289b279 | blueswir1 | } |
1218 | 8289b279 | blueswir1 | |
1219 | 8289b279 | blueswir1 | static const TCGTargetOpDef sparc_op_defs[] = { |
1220 | 8289b279 | blueswir1 | { INDEX_op_exit_tb, { } }, |
1221 | b3db8758 | blueswir1 | { INDEX_op_goto_tb, { } }, |
1222 | 8289b279 | blueswir1 | { INDEX_op_call, { "ri" } },
|
1223 | 8289b279 | blueswir1 | { INDEX_op_jmp, { "ri" } },
|
1224 | 8289b279 | blueswir1 | { INDEX_op_br, { } }, |
1225 | 8289b279 | blueswir1 | |
1226 | 8289b279 | blueswir1 | { INDEX_op_mov_i32, { "r", "r" } }, |
1227 | 8289b279 | blueswir1 | { INDEX_op_movi_i32, { "r" } },
|
1228 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1229 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1230 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1231 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1232 | 8289b279 | blueswir1 | { INDEX_op_ld_i32, { "r", "r" } }, |
1233 | 8289b279 | blueswir1 | { INDEX_op_st8_i32, { "r", "r" } }, |
1234 | 8289b279 | blueswir1 | { INDEX_op_st16_i32, { "r", "r" } }, |
1235 | 8289b279 | blueswir1 | { INDEX_op_st_i32, { "r", "r" } }, |
1236 | 8289b279 | blueswir1 | |
1237 | 53cd9273 | blueswir1 | { INDEX_op_add_i32, { "r", "r", "rJ" } }, |
1238 | 53cd9273 | blueswir1 | { INDEX_op_mul_i32, { "r", "r", "rJ" } }, |
1239 | 8289b279 | blueswir1 | { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } }, |
1240 | 8289b279 | blueswir1 | { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } }, |
1241 | 53cd9273 | blueswir1 | { INDEX_op_sub_i32, { "r", "r", "rJ" } }, |
1242 | 53cd9273 | blueswir1 | { INDEX_op_and_i32, { "r", "r", "rJ" } }, |
1243 | 53cd9273 | blueswir1 | { INDEX_op_or_i32, { "r", "r", "rJ" } }, |
1244 | 53cd9273 | blueswir1 | { INDEX_op_xor_i32, { "r", "r", "rJ" } }, |
1245 | 8289b279 | blueswir1 | |
1246 | 53cd9273 | blueswir1 | { INDEX_op_shl_i32, { "r", "r", "rJ" } }, |
1247 | 53cd9273 | blueswir1 | { INDEX_op_shr_i32, { "r", "r", "rJ" } }, |
1248 | 53cd9273 | blueswir1 | { INDEX_op_sar_i32, { "r", "r", "rJ" } }, |
1249 | 8289b279 | blueswir1 | |
1250 | 56f4927e | Richard Henderson | { INDEX_op_brcond_i32, { "r", "rJ" } }, |
1251 | 56f4927e | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 |
1252 | 56f4927e | Richard Henderson | { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } }, |
1253 | 56f4927e | Richard Henderson | #endif
|
1254 | 8289b279 | blueswir1 | |
1255 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1256 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1257 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1258 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1259 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1260 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1261 | 8289b279 | blueswir1 | |
1262 | 8289b279 | blueswir1 | { INDEX_op_qemu_st8, { "L", "L" } }, |
1263 | 8289b279 | blueswir1 | { INDEX_op_qemu_st16, { "L", "L" } }, |
1264 | 8289b279 | blueswir1 | { INDEX_op_qemu_st32, { "L", "L" } }, |
1265 | 8289b279 | blueswir1 | |
1266 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1267 | 8289b279 | blueswir1 | { INDEX_op_mov_i64, { "r", "r" } }, |
1268 | 8289b279 | blueswir1 | { INDEX_op_movi_i64, { "r" } },
|
1269 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1270 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1271 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1272 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1273 | 8289b279 | blueswir1 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1274 | 8289b279 | blueswir1 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1275 | 8289b279 | blueswir1 | { INDEX_op_ld_i64, { "r", "r" } }, |
1276 | 8289b279 | blueswir1 | { INDEX_op_st8_i64, { "r", "r" } }, |
1277 | 8289b279 | blueswir1 | { INDEX_op_st16_i64, { "r", "r" } }, |
1278 | 8289b279 | blueswir1 | { INDEX_op_st32_i64, { "r", "r" } }, |
1279 | 8289b279 | blueswir1 | { INDEX_op_st_i64, { "r", "r" } }, |
1280 | 56fc64df | blueswir1 | { INDEX_op_qemu_ld64, { "L", "L" } }, |
1281 | 56fc64df | blueswir1 | { INDEX_op_qemu_st64, { "L", "L" } }, |
1282 | 8289b279 | blueswir1 | |
1283 | 53cd9273 | blueswir1 | { INDEX_op_add_i64, { "r", "r", "rJ" } }, |
1284 | 53cd9273 | blueswir1 | { INDEX_op_mul_i64, { "r", "r", "rJ" } }, |
1285 | 8289b279 | blueswir1 | { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } }, |
1286 | 8289b279 | blueswir1 | { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } }, |
1287 | 53cd9273 | blueswir1 | { INDEX_op_sub_i64, { "r", "r", "rJ" } }, |
1288 | 53cd9273 | blueswir1 | { INDEX_op_and_i64, { "r", "r", "rJ" } }, |
1289 | 53cd9273 | blueswir1 | { INDEX_op_or_i64, { "r", "r", "rJ" } }, |
1290 | 53cd9273 | blueswir1 | { INDEX_op_xor_i64, { "r", "r", "rJ" } }, |
1291 | 8289b279 | blueswir1 | |
1292 | 53cd9273 | blueswir1 | { INDEX_op_shl_i64, { "r", "r", "rJ" } }, |
1293 | 53cd9273 | blueswir1 | { INDEX_op_shr_i64, { "r", "r", "rJ" } }, |
1294 | 53cd9273 | blueswir1 | { INDEX_op_sar_i64, { "r", "r", "rJ" } }, |
1295 | 8289b279 | blueswir1 | |
1296 | 56f4927e | Richard Henderson | { INDEX_op_brcond_i64, { "r", "rJ" } }, |
1297 | 8289b279 | blueswir1 | #endif
|
1298 | 8289b279 | blueswir1 | { -1 },
|
1299 | 8289b279 | blueswir1 | }; |
1300 | 8289b279 | blueswir1 | |
1301 | 8289b279 | blueswir1 | void tcg_target_init(TCGContext *s)
|
1302 | 8289b279 | blueswir1 | { |
1303 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
1304 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1305 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
1306 | 8289b279 | blueswir1 | #endif
|
1307 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1308 | b3db8758 | blueswir1 | (1 << TCG_REG_G1) |
|
1309 | b3db8758 | blueswir1 | (1 << TCG_REG_G2) |
|
1310 | b3db8758 | blueswir1 | (1 << TCG_REG_G3) |
|
1311 | b3db8758 | blueswir1 | (1 << TCG_REG_G4) |
|
1312 | b3db8758 | blueswir1 | (1 << TCG_REG_G5) |
|
1313 | b3db8758 | blueswir1 | (1 << TCG_REG_G6) |
|
1314 | b3db8758 | blueswir1 | (1 << TCG_REG_G7) |
|
1315 | 8289b279 | blueswir1 | (1 << TCG_REG_O0) |
|
1316 | 8289b279 | blueswir1 | (1 << TCG_REG_O1) |
|
1317 | 8289b279 | blueswir1 | (1 << TCG_REG_O2) |
|
1318 | 8289b279 | blueswir1 | (1 << TCG_REG_O3) |
|
1319 | 8289b279 | blueswir1 | (1 << TCG_REG_O4) |
|
1320 | 8289b279 | blueswir1 | (1 << TCG_REG_O5) |
|
1321 | 8289b279 | blueswir1 | (1 << TCG_REG_O7));
|
1322 | 8289b279 | blueswir1 | |
1323 | 8289b279 | blueswir1 | tcg_regset_clear(s->reserved_regs); |
1324 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
1325 | a212ea75 | Richard Henderson | #if TCG_TARGET_REG_BITS == 64 |
1326 | d795eb86 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
|
1327 | d795eb86 | blueswir1 | #endif
|
1328 | 53cd9273 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
1329 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
1330 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
1331 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
1332 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
1333 | 8289b279 | blueswir1 | tcg_add_target_add_op_defs(sparc_op_defs); |
1334 | 8289b279 | blueswir1 | } |