tcg-sparc: Implement brcond2.
Split out tcg_out_cmp and properly handle immediate arguments.Fix constraints on brcond to match what SUBCC accepts.Add tcg_out_brcond2_i32 for 32-bit host.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.
The test TCG_TARGET_REG_BITS==64 is exactly the feature that weare checking for, whereas something involving sparc_v9 orsparc_v8plus should be reserved for something ISA related,as with SMULX....
tcg-sparc: Improve tcg_out_movi for sparc64.
Generate sign-extended 32-bit constants with SETHI+XOR.Otherwise tidy the routine to avoid the need forconditional compilation and code duplication with movi_imm32.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg-sparc: Fix imm13 check in movi.
We were unnecessarily restricting imm13 constants to 12 bits.
tcg/ppc64: Fix loading of 32bit constants
Signed-off-by: malc <av1474@comtv.ru>
TCG: Mac OS X support for ppc64 target
Darwin/ppc64 does not use function descriptors,adapt prologue and tcg_out_call accordingly.GPR2 is available for general use, so let's use it.
http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...
S/390 fake TCG implementation
Qemu won't let us run a KVM target without having host TCG support. Well, fornow we don't have any so let's implement a fake target that only stubs outeverything.
I tried to keep the patch as close to Uli's source as possible, so whenever...
tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/ppc64,x86_64: fix constraints of op_qemu_st64
This op only takes two arguments, not two.
tcg/i386: remove duplicate sar opcode
Signed-off-by: Magnus Damm <damm@opensource.se>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: improve output log
tcg: allocate s->op_dead_iargs dynamically
Similarly to what is already done in tcg_liveness_analysis() whenUSE_LIVENESS_ANALYSIS is not set.
tcg: remove dead code
tcg: add ext{8,16,32}u_i{32,64} TCG ops
Currently zero extensions ops are implemented by a and op with aconstant. This is then catched in some backend, and replaced bya zero extension instruction. While this works well on RISCmachines, this adds a useless register move on non-RISC machines....
tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG ops
tcg/i386: add support for ext{8,16}u_i32 TCG ops
Revert part of 6692b043198d58a12317009edb98654c6839f043
Committed by accident.
TCG: fix DEF2 macro
tcg/i386: generates dec/inc instead of sub/add when possible
We must take care that dec/inc do not compute CF, which is needed byadd2/sub2.
tcg/i386: optimize and $0xff(ff), reg
tcg/x86_64: generated dec/inc instead of sub/add when possible
tcg/ppc: always use tcg_out_call
ARM back-end: Use sxt[bh] instructions for ext{8, 6}s
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Suppress some variants of English in comments
Replace surpress, supress by suppress.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Compile TCG runtime library only once
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: fix size of local variables in tcg_gen_bswap64_i64
t0, t1 must be 64 bit values, not 32 bit.
X86_64: Use proper jumps/calls when displacement exceeds +-2G
When targeting PPU use rlwinm instead of andi. if possible
andi. is microcoded and slow there.
ARM back-end: Fix encode_imm
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
ARM back-end: Handle all possible immediates for ALU ops
this patch handles all possible constants for immediate operand of ALU ops.I'm not very satisfied by the implementation.
ARM back-end: Add TCG not
this patch:
- implements TCG not.
rename DEBUG_TCG to CONFIG_DEBUG_TCG
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Fix CONFIG_PROFILER
Fix rbase initialization
this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A- implement add/sub/and/or/xor with immediate (only 8-bit)
tcg: Fix tcg_gen_rotr_i64
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
PPC 32/64 GUEST_BASE support
Fix LHZX opcode value
Userspace guest address offsetting
Fix type in i386 tcg.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Re-implement GUEST_BASE support.Offset guest ddress space by default if the guest binary containsregions below the host mmap_min_addr.Implement support for i386, x86-64 and arm hosts.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>...
ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
tcg: make sure NDEBUG is defined before including <assert.h>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
Add a --enable-debug-tcg option to configure
This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUGfrom being defined) when passing an option to the configure script.This should help to prevent any accidental changes that enableDEBUG_TCGV in tcg/tcg.h from being committed in future, and may...
Remove reserved registers from tcg_target_reg_alloc_order
Noticed by Andreas Faerber
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
Whack [LS]MW
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/tcg.h: fix a few typos
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add a CONST flag to TCG helpers
A const function only reads its arguments and does not use TCGglobals variables. Hence a call to such a function does notsave TCG globals variabes back to their canonical location.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg: improve comment about pure functions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7007 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/x86_64: optimize register allocation order
The beginning of the register allocation order list on the TCG x86_64target matches the list of clobbered registers. This means that when anhelper is called, there is almost always clobbered registers that have...
Fix branches and TLB matches for 64 bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
Allocate space for static call args, increase stack frame size on Sparc64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: fix _tl aliases for divu/remu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add _tl aliases for div/divu/rem/remu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/README: fix description of bswap32_i32/i64
Thanks to Stuart Brady for the notice.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6920 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6838 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/x86: add bswap16_i32 ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6837 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: update README wrt recent bswap changes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6834 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add _tl aliases to bswap16/32/64 TCG ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6833 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add bswap16_i64 and bswap32_i64 TCG ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: optimize tcg_gen_bswap16_i32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6831 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: allow bswap16_i32 to be implemented by TCG backends
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6830 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: move {not,neg}_i{32,64} definitions at the right place
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6811 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: fix commit r6805
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6810 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-arm: fix qemu_ld64
Emulating fldl on arm doesn't seem to work too well. It's the wayqemu_ld64 is translated to arm instructions.
tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);...
tcg: update TODO
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6807 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/x86: add not/neg/extu/bswap/rot i32 ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6806 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: optimize logical operations
Simplify nand/nor/eqv and move their optimizations to and/or/xor
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6805 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tcg after commit 6800
The introduction of TCGV_EQUAL and not op is slightly broken.The definition of DEBUG_TCGV shows that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6802 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: use TCGV_EQUAL_I{32,64}
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6800 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: define TCGV_EQUAL_I{32,64}
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6799 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6798 c046a42c-6fe2-441c-8c8c-71466251a162
Implement TCG not ops for x86-64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: don't define TCG rotation ops if they are not supported
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6796 c046a42c-6fe2-441c-8c8c-71466251a162
Implement TCG rotation ops for x86-64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
Prune unused TCG_AREGs
Remove definitions for TCG_AREGs corresponding to AREG definitionsremoved in r6778.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
Sparse fixes: truncation by cast
Fix Sparse warnings about constant truncation caused by cast
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6737 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: remove obsolete old_op_count profiler field
Since we don't generate any "old op" anymore, the old_op_countis unneeded.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6614 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing r24..r26 to callee save registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing r24..r26 to calle save registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
Add "static"
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6588 c046a42c-6fe2-441c-8c8c-71466251a162
Fix DEBUG_TCGV compile error.
Don't call TCGV_LOW on arg2. This section of code falls under
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
R13 is reserved for small data area pointer by SVR4 PPC ABI
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Remove all traces of powerpc
According to $GCC/gcc/config/rs6000/rs6000-c.c _ARCH_PPC is theubiquitous define which should be used to test whether gcc targetsPowerPC, on 64bit platforms _ARCH_PPC64 will be also defined.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6301 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: remove tcg_global_reg2_new_hack()
This patch removes the unused tcg_global_reg2_new_hack() function, whichwas added in r4438 to work around a register shortage problem regardingdyngen. The only ever user of this function was removed in r4577.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>...
TCG: Fix documentation of qemu_ld/st ops
The functions defined in tcg/tcg-op.h have no _i32 or _i64 suffix,qemu_ld64 and qemu_st64 were missing from the list, and there areno 'plain' qemu_ld/qemu_st ops.
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: kill two warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6029 c046a42c-6fe2-441c-8c8c-71466251a162
TCG x86/x86-64: use move with zero-extend for loads/stores
Starting with version 4.3, gcc returns the result of a function inrax/eax/ax/al instead of rax/eax, depending of the return type. Asa consequence we should use a zero extend moe in TCG loads/stores....
Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
Fix TARGET_LONG_BITS warning in TCG
Looking at tcg/tcg.c:828, the bug that the warning indicated would show up asincorrect PC shown in log, only on 32 bit big endian host emulating a 64 bittarget, -d op flag enabled. Now that dyngen is gone, the patch can be applied....
Introduce and use cache-utils.[ch]
Thanks to Segher Boessenkool and Holis Blanchard.
AIX and Darwin cache inquiry:http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html
Auxiliary vectors:http://manugarg.googlepages.com/aboutelfauxiliaryvectors
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162