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/*
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 * ARM Versatile/PB PCI host controller
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 *
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 * Copyright (c) 2006-2009 CodeSourcery.
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 * Written by Paul Brook
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 *
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 * This code is licenced under the LGPL.
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 */
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#include "sysbus.h"
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#include "pci.h"
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#include "pci_host.h"
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typedef struct {
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    SysBusDevice busdev;
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    qemu_irq irq[4];
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    int realview;
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    int mem_config;
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} PCIVPBState;
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static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
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{
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    return addr & 0xffffff;
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}
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static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
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                                   uint32_t val)
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{
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    pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
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}
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static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
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                                   uint32_t val)
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{
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    pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
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}
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static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
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                                   uint32_t val)
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{
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    pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
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}
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static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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    val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
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    return val;
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}
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static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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    val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
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    return val;
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}
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static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
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{
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    uint32_t val;
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    val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
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    return val;
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}
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static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
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    &pci_vpb_config_writeb,
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    &pci_vpb_config_writew,
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    &pci_vpb_config_writel,
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};
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static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
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    &pci_vpb_config_readb,
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    &pci_vpb_config_readw,
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    &pci_vpb_config_readl,
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};
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static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
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{
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    return irq_num;
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}
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static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
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{
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    qemu_irq *pic = opaque;
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    qemu_set_irq(pic[irq_num], level);
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}
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static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
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{
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    PCIVPBState *s = (PCIVPBState *)dev;
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    /* Selfconfig area.  */
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    cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
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    /* Normal config area.  */
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    cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
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    if (s->realview) {
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        /* IO memory area.  */
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        isa_mmio_init(base + 0x03000000, 0x00100000);
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    }
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}
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static int pci_vpb_init(SysBusDevice *dev)
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{
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    PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
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    PCIBus *bus;
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    int i;
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    for (i = 0; i < 4; i++) {
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        sysbus_init_irq(dev, &s->irq[i]);
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    }
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    bus = pci_register_bus(&dev->qdev, "pci",
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                           pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
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                           PCI_DEVFN(11, 0), 4);
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    /* ??? Register memory space.  */
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    s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
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                                           pci_vpb_config_write, bus,
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                                           DEVICE_LITTLE_ENDIAN);
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    sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
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    pci_create_simple(bus, -1, "versatile_pci_host");
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    return 0;
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}
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static int pci_realview_init(SysBusDevice *dev)
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{
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    PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
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    s->realview = 1;
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    return pci_vpb_init(dev);
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}
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static int versatile_pci_host_init(PCIDevice *d)
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{
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    pci_set_word(d->config + PCI_STATUS,
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                 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
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    pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
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    return 0;
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}
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static PCIDeviceInfo versatile_pci_host_info = {
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    .qdev.name = "versatile_pci_host",
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    .qdev.size = sizeof(PCIDevice),
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    .init      = versatile_pci_host_init,
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    .vendor_id = PCI_VENDOR_ID_XILINX,
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    /* Both boards have the same device ID.  Oh well.  */
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    .device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
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    .class_id  = PCI_CLASS_PROCESSOR_CO,
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};
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static void versatile_pci_register_devices(void)
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{
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    sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
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    sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
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                        pci_realview_init);
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    pci_qdev_register(&versatile_pci_host_info);
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}
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device_init(versatile_pci_register_devices)