Revision 57fec1fe target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 36 | 36 |
#include "cpu.h" |
| 37 | 37 |
#include "exec-all.h" |
| 38 | 38 |
#include "disas.h" |
| 39 |
#include "tcg-op.h" |
|
| 39 | 40 |
|
| 40 | 41 |
#define DEBUG_DISAS |
| 41 | 42 |
|
| ... | ... | |
| 65 | 66 |
|
| 66 | 67 |
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
| 67 | 68 |
|
| 68 |
static uint16_t *gen_opc_ptr; |
|
| 69 |
static uint32_t *gen_opparam_ptr; |
|
| 70 | 69 |
extern FILE *logfile; |
| 71 | 70 |
extern int loglevel; |
| 72 | 71 |
|
| 73 |
enum {
|
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| 74 |
#define DEF(s,n,copy_size) INDEX_op_ ## s, |
|
| 75 |
#include "opc.h" |
|
| 76 |
#undef DEF |
|
| 77 |
NB_OPS |
|
| 78 |
}; |
|
| 79 |
|
|
| 80 |
#include "gen-op.h" |
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| 81 |
|
|
| 82 | 72 |
// This function uses non-native bit order |
| 83 | 73 |
#define GET_FIELD(X, FROM, TO) \ |
| 84 | 74 |
((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
| ... | ... | |
| 98 | 88 |
#define QFPREG(r) (r & 0x1c) |
| 99 | 89 |
#endif |
| 100 | 90 |
|
| 101 |
#ifdef USE_DIRECT_JUMP |
|
| 102 |
#define TBPARAM(x) |
|
| 103 |
#else |
|
| 104 |
#define TBPARAM(x) (long)(x) |
|
| 105 |
#endif |
|
| 106 |
|
|
| 107 | 91 |
static int sign_extend(int x, int len) |
| 108 | 92 |
{
|
| 109 | 93 |
len = 32 - len; |
| ... | ... | |
| 699 | 683 |
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && |
| 700 | 684 |
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
|
| 701 | 685 |
/* jump to same page: we can use a direct jump */ |
| 702 |
if (tb_num == 0) |
|
| 703 |
gen_op_goto_tb0(TBPARAM(tb)); |
|
| 704 |
else |
|
| 705 |
gen_op_goto_tb1(TBPARAM(tb)); |
|
| 686 |
tcg_gen_goto_tb(tb_num); |
|
| 706 | 687 |
gen_jmp_im(pc); |
| 707 | 688 |
gen_movl_npc_im(npc); |
| 708 |
gen_op_movl_T0_im((long)tb + tb_num); |
|
| 709 |
gen_op_exit_tb(); |
|
| 689 |
tcg_gen_exit_tb((long)tb + tb_num); |
|
| 710 | 690 |
} else {
|
| 711 | 691 |
/* jump to another page: currently not optimized */ |
| 712 | 692 |
gen_jmp_im(pc); |
| 713 | 693 |
gen_movl_npc_im(npc); |
| 714 |
gen_op_movl_T0_0(); |
|
| 715 |
gen_op_exit_tb(); |
|
| 694 |
tcg_gen_exit_tb(0); |
|
| 716 | 695 |
} |
| 717 | 696 |
} |
| 718 | 697 |
|
| ... | ... | |
| 1281 | 1260 |
gen_op_trapcc_T0(); |
| 1282 | 1261 |
} |
| 1283 | 1262 |
gen_op_next_insn(); |
| 1284 |
gen_op_movl_T0_0(); |
|
| 1285 |
gen_op_exit_tb(); |
|
| 1263 |
tcg_gen_exit_tb(0); |
|
| 1286 | 1264 |
dc->is_br = 1; |
| 1287 | 1265 |
goto jmp_insn; |
| 1288 | 1266 |
} else if (xop == 0x28) {
|
| ... | ... | |
| 2341 | 2319 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); |
| 2342 | 2320 |
save_state(dc); |
| 2343 | 2321 |
gen_op_next_insn(); |
| 2344 |
gen_op_movl_T0_0(); |
|
| 2345 |
gen_op_exit_tb(); |
|
| 2322 |
tcg_gen_exit_tb(0); |
|
| 2346 | 2323 |
dc->is_br = 1; |
| 2347 | 2324 |
break; |
| 2348 | 2325 |
case 0xf: /* V9 sir, nop if user */ |
| ... | ... | |
| 2422 | 2399 |
gen_op_wrpsr(); |
| 2423 | 2400 |
save_state(dc); |
| 2424 | 2401 |
gen_op_next_insn(); |
| 2425 |
gen_op_movl_T0_0(); |
|
| 2426 |
gen_op_exit_tb(); |
|
| 2402 |
tcg_gen_exit_tb(0); |
|
| 2427 | 2403 |
dc->is_br = 1; |
| 2428 | 2404 |
#endif |
| 2429 | 2405 |
} |
| ... | ... | |
| 2457 | 2433 |
gen_op_wrpstate(); |
| 2458 | 2434 |
save_state(dc); |
| 2459 | 2435 |
gen_op_next_insn(); |
| 2460 |
gen_op_movl_T0_0(); |
|
| 2461 |
gen_op_exit_tb(); |
|
| 2436 |
tcg_gen_exit_tb(0); |
|
| 2462 | 2437 |
dc->is_br = 1; |
| 2463 | 2438 |
break; |
| 2464 | 2439 |
case 7: // tl |
| ... | ... | |
| 2517 | 2492 |
// XXX gen_op_wrhpstate(); |
| 2518 | 2493 |
save_state(dc); |
| 2519 | 2494 |
gen_op_next_insn(); |
| 2520 |
gen_op_movl_T0_0(); |
|
| 2521 |
gen_op_exit_tb(); |
|
| 2495 |
tcg_gen_exit_tb(0); |
|
| 2522 | 2496 |
dc->is_br = 1; |
| 2523 | 2497 |
break; |
| 2524 | 2498 |
case 1: // htstate |
| ... | ... | |
| 3635 | 3609 |
dc->npc = (target_ulong) tb->cs_base; |
| 3636 | 3610 |
dc->mem_idx = cpu_mmu_index(env); |
| 3637 | 3611 |
dc->fpu_enabled = cpu_fpu_enabled(env); |
| 3638 |
gen_opc_ptr = gen_opc_buf; |
|
| 3639 | 3612 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
| 3640 |
gen_opparam_ptr = gen_opparam_buf; |
|
| 3641 |
nb_gen_labels = 0; |
|
| 3642 | 3613 |
|
| 3643 | 3614 |
do {
|
| 3644 | 3615 |
if (env->nb_breakpoints > 0) {
|
| ... | ... | |
| 3647 | 3618 |
if (dc->pc != pc_start) |
| 3648 | 3619 |
save_state(dc); |
| 3649 | 3620 |
gen_op_debug(); |
| 3650 |
gen_op_movl_T0_0(); |
|
| 3651 |
gen_op_exit_tb(); |
|
| 3621 |
tcg_gen_exit_tb(0); |
|
| 3652 | 3622 |
dc->is_br = 1; |
| 3653 | 3623 |
goto exit_gen_loop; |
| 3654 | 3624 |
} |
| ... | ... | |
| 3683 | 3653 |
generate an exception */ |
| 3684 | 3654 |
if (env->singlestep_enabled) {
|
| 3685 | 3655 |
gen_jmp_im(dc->pc); |
| 3686 |
gen_op_movl_T0_0(); |
|
| 3687 |
gen_op_exit_tb(); |
|
| 3656 |
tcg_gen_exit_tb(0); |
|
| 3688 | 3657 |
break; |
| 3689 | 3658 |
} |
| 3690 | 3659 |
} while ((gen_opc_ptr < gen_opc_end) && |
| ... | ... | |
| 3700 | 3669 |
if (dc->pc != DYNAMIC_PC) |
| 3701 | 3670 |
gen_jmp_im(dc->pc); |
| 3702 | 3671 |
save_npc(dc); |
| 3703 |
gen_op_movl_T0_0(); |
|
| 3704 |
gen_op_exit_tb(); |
|
| 3672 |
tcg_gen_exit_tb(0); |
|
| 3705 | 3673 |
} |
| 3706 | 3674 |
} |
| 3707 | 3675 |
*gen_opc_ptr = INDEX_op_end; |
| ... | ... | |
| 3726 | 3694 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
| 3727 | 3695 |
target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
| 3728 | 3696 |
fprintf(logfile, "\n"); |
| 3729 |
if (loglevel & CPU_LOG_TB_OP) {
|
|
| 3730 |
fprintf(logfile, "OP:\n"); |
|
| 3731 |
dump_ops(gen_opc_buf, gen_opparam_buf); |
|
| 3732 |
fprintf(logfile, "\n"); |
|
| 3733 |
} |
|
| 3734 | 3697 |
} |
| 3735 | 3698 |
#endif |
| 3736 | 3699 |
return 0; |
| ... | ... | |
| 3746 | 3709 |
return gen_intermediate_code_internal(tb, 1, env); |
| 3747 | 3710 |
} |
| 3748 | 3711 |
|
| 3749 |
extern int ram_size; |
|
| 3750 |
|
|
| 3751 | 3712 |
void cpu_reset(CPUSPARCState *env) |
| 3752 | 3713 |
{
|
| 3753 | 3714 |
tlb_flush(env, 1); |
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