Revision 580b7295 hw/acpi_piix4.c

b/hw/acpi_piix4.c
317 317
    uint8_t *pci_conf;
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    pci_conf = s->dev.config;
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    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
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    pci_conf[0x06] = 0x80;
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    pci_conf[0x07] = 0x02;
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    pci_conf[0x08] = 0x03; // revision number
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    pci_conf[0x09] = 0x00;
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    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
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    pci_conf[0x3d] = 0x01; // interrupt pin 1
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    pci_conf[0x40] = 0x01; /* PM io base read only bit */
......
394 390
    .no_hotplug         = 1,
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    .init               = piix4_pm_initfn,
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    .config_write       = pm_write_config,
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    .vendor_id          = PCI_VENDOR_ID_INTEL,
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    .device_id          = PCI_DEVICE_ID_INTEL_82371AB_3,
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    .revision           = 0x03,
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    .class_id           = PCI_CLASS_BRIDGE_OTHER,
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    .qdev.props         = (Property[]) {
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        DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
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        DEFINE_PROP_END_OF_LIST(),

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