Revision 5844997a

b/hw/xio3130_upstream.c
65 65
    }
66 66

  
67 67
    pcie_port_init_reg(d);
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI);
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    pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130U);
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    d->config[PCI_REVISION_ID] = XIO3130_REVISION;
71 68

  
72 69
    rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
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                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
......
159 156
    .config_write = xio3130_upstream_write_config,
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    .init = xio3130_upstream_initfn,
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    .exit = xio3130_upstream_exitfn,
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    .vendor_id = PCI_VENDOR_ID_TI,
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    .device_id = PCI_DEVICE_ID_TI_XIO3130U,
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    .revision = XIO3130_REVISION,
162 162

  
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    .qdev.props = (Property[]) {
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        DEFINE_PROP_UINT8("port", PCIEPort, port, 0),

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