root / tcg / ppc64 / tcg-target.c @ 591d6f1d
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_CT_CONST_U32 0x100 |
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static uint8_t *tb_ret_addr;
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#define FAST_PATH
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#if TARGET_PHYS_ADDR_BITS == 32 |
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#define LD_ADDEND LWZ
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#else
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#define LD_ADDEND LD
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#endif
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|
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#if TARGET_LONG_BITS == 32 |
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#define LD_ADDR LWZU
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#define CMP_L 0 |
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#else
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#define LD_ADDR LDU
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#define CMP_L (1<<21) |
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#endif
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#ifndef GUEST_BASE
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#define GUEST_BASE 0 |
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#endif
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#ifdef CONFIG_USE_GUEST_BASE
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#define TCG_GUEST_BASE_REG 30 |
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#else
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#define TCG_GUEST_BASE_REG 0 |
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#endif
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"r0",
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"r1",
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"rp",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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}; |
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#endif
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31, |
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#ifdef __APPLE__
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TCG_REG_R2, |
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#endif
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TCG_REG_R3, |
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TCG_REG_R4, |
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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#ifndef __APPLE__
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TCG_REG_R11, |
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#endif
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TCG_REG_R12, |
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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TCG_REG_R27 |
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}; |
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static const int tcg_target_call_iarg_regs[] = { |
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TCG_REG_R3, |
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TCG_REG_R4, |
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10 |
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}; |
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_R3 |
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}; |
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static const int tcg_target_callee_save_regs[] = { |
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#ifdef __APPLE__
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TCG_REG_R11, |
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#endif
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R16, |
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TCG_REG_R17, |
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TCG_REG_R18, |
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TCG_REG_R19, |
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TCG_REG_R20, |
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TCG_REG_R21, |
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TCG_REG_R22, |
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TCG_REG_R23, |
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TCG_REG_R24, |
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TCG_REG_R25, |
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TCG_REG_R26, |
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/* TCG_REG_R27, */ /* currently used for the global env, so no |
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need to save */
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TCG_REG_R28, |
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TCG_REG_R29, |
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TCG_REG_R30, |
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TCG_REG_R31 |
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}; |
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static uint32_t reloc_pc24_val (void *pc, tcg_target_long target) |
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{ |
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tcg_target_long disp; |
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disp = target - (tcg_target_long) pc; |
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if ((disp << 38) >> 38 != disp) |
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tcg_abort (); |
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return disp & 0x3fffffc; |
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} |
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static void reloc_pc24 (void *pc, tcg_target_long target) |
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{ |
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
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| reloc_pc24_val (pc, target); |
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} |
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static uint16_t reloc_pc14_val (void *pc, tcg_target_long target) |
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{ |
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tcg_target_long disp; |
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disp = target - (tcg_target_long) pc; |
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if (disp != (int16_t) disp)
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tcg_abort (); |
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return disp & 0xfffc; |
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} |
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static void reloc_pc14 (void *pc, tcg_target_long target) |
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{ |
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
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| reloc_pc14_val (pc, target); |
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} |
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static void patch_reloc (uint8_t *code_ptr, int type, |
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tcg_target_long value, tcg_target_long addend) |
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{ |
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value += addend; |
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switch (type) {
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case R_PPC_REL14:
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reloc_pc14 (code_ptr, value); |
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break;
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case R_PPC_REL24:
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reloc_pc24 (code_ptr, value); |
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break;
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default:
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tcg_abort (); |
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} |
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} |
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/* maximum number of register used for input function arguments */
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static int tcg_target_get_call_iarg_regs_count (int flags) |
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{ |
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return ARRAY_SIZE (tcg_target_call_iarg_regs);
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} |
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/* parse target specific constraints */
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static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) |
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{ |
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const char *ct_str; |
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ct_str = *pct_str; |
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switch (ct_str[0]) { |
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case 'A': case 'B': case 'C': case 'D': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A'); |
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break;
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case 'r': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); |
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break;
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case 'L': /* qemu_ld constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); |
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#ifdef CONFIG_SOFTMMU
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); |
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#endif
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break;
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case 'S': /* qemu_st constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); |
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); |
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#ifdef CONFIG_SOFTMMU
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); |
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); |
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#endif
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break;
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case 'Z': |
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ct->ct |= TCG_CT_CONST_U32; |
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break;
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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|
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/* test if a constant matches the constraint */
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static int tcg_target_const_match (tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
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{ |
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int ct;
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val)) |
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return 1; |
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return 0; |
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} |
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#define OPCD(opc) ((opc)<<26) |
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#define XO19(opc) (OPCD(19)|((opc)<<1)) |
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#define XO30(opc) (OPCD(30)|((opc)<<2)) |
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#define XO31(opc) (OPCD(31)|((opc)<<1)) |
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#define XO58(opc) (OPCD(58)|(opc)) |
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#define XO62(opc) (OPCD(62)|(opc)) |
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#define B OPCD( 18) |
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#define BC OPCD( 16) |
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#define LBZ OPCD( 34) |
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#define LHZ OPCD( 40) |
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#define LHA OPCD( 42) |
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#define LWZ OPCD( 32) |
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#define STB OPCD( 38) |
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#define STH OPCD( 44) |
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#define STW OPCD( 36) |
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|
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#define STD XO62( 0) |
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#define STDU XO62( 1) |
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#define STDX XO31(149) |
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|
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#define LD XO58( 0) |
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#define LDX XO31( 21) |
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#define LDU XO58( 1) |
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#define LWA XO58( 2) |
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#define LWAX XO31(341) |
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|
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#define ADDI OPCD( 14) |
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#define ADDIS OPCD( 15) |
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#define ORI OPCD( 24) |
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#define ORIS OPCD( 25) |
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#define XORI OPCD( 26) |
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#define XORIS OPCD( 27) |
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#define ANDI OPCD( 28) |
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#define ANDIS OPCD( 29) |
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#define MULLI OPCD( 7) |
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#define CMPLI OPCD( 10) |
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#define CMPI OPCD( 11) |
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|
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#define LWZU OPCD( 33) |
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#define STWU OPCD( 37) |
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|
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#define RLWINM OPCD( 21) |
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|
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#define RLDICL XO30( 0) |
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#define RLDICR XO30( 1) |
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#define RLDIMI XO30( 3) |
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|
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#define BCLR XO19( 16) |
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#define BCCTR XO19(528) |
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#define CRAND XO19(257) |
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#define CRANDC XO19(129) |
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#define CRNAND XO19(225) |
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#define CROR XO19(449) |
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|
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#define EXTSB XO31(954) |
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#define EXTSH XO31(922) |
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#define EXTSW XO31(986) |
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#define ADD XO31(266) |
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#define ADDE XO31(138) |
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#define ADDC XO31( 10) |
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#define AND XO31( 28) |
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#define SUBF XO31( 40) |
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#define SUBFC XO31( 8) |
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#define SUBFE XO31(136) |
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#define OR XO31(444) |
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#define XOR XO31(316) |
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#define MULLW XO31(235) |
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#define MULHWU XO31( 11) |
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#define DIVW XO31(491) |
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#define DIVWU XO31(459) |
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#define CMP XO31( 0) |
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#define CMPL XO31( 32) |
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#define LHBRX XO31(790) |
355 |
#define LWBRX XO31(534) |
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#define STHBRX XO31(918) |
357 |
#define STWBRX XO31(662) |
358 |
#define MFSPR XO31(339) |
359 |
#define MTSPR XO31(467) |
360 |
#define SRAWI XO31(824) |
361 |
#define NEG XO31(104) |
362 |
|
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#define MULLD XO31(233) |
364 |
#define MULHD XO31( 73) |
365 |
#define MULHDU XO31( 9) |
366 |
#define DIVD XO31(489) |
367 |
#define DIVDU XO31(457) |
368 |
|
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#define LBZX XO31( 87) |
370 |
#define LHZX XO31(279) |
371 |
#define LHAX XO31(343) |
372 |
#define LWZX XO31( 23) |
373 |
#define STBX XO31(215) |
374 |
#define STHX XO31(407) |
375 |
#define STWX XO31(151) |
376 |
|
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#define SPR(a,b) ((((a)<<5)|(b))<<11) |
378 |
#define LR SPR(8, 0) |
379 |
#define CTR SPR(9, 0) |
380 |
|
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#define SLW XO31( 24) |
382 |
#define SRW XO31(536) |
383 |
#define SRAW XO31(792) |
384 |
|
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#define SLD XO31( 27) |
386 |
#define SRD XO31(539) |
387 |
#define SRAD XO31(794) |
388 |
#define SRADI XO31(413<<1) |
389 |
|
390 |
#define TW XO31( 4) |
391 |
#define TRAP (TW | TO (31)) |
392 |
|
393 |
#define RT(r) ((r)<<21) |
394 |
#define RS(r) ((r)<<21) |
395 |
#define RA(r) ((r)<<16) |
396 |
#define RB(r) ((r)<<11) |
397 |
#define TO(t) ((t)<<21) |
398 |
#define SH(s) ((s)<<11) |
399 |
#define MB(b) ((b)<<6) |
400 |
#define ME(e) ((e)<<1) |
401 |
#define BO(o) ((o)<<21) |
402 |
#define MB64(b) ((b)<<5) |
403 |
|
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#define LK 1 |
405 |
|
406 |
#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
|
407 |
#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
|
408 |
|
409 |
#define BF(n) ((n)<<23) |
410 |
#define BI(n, c) (((c)+((n)*4))<<16) |
411 |
#define BT(n, c) (((c)+((n)*4))<<21) |
412 |
#define BA(n, c) (((c)+((n)*4))<<16) |
413 |
#define BB(n, c) (((c)+((n)*4))<<11) |
414 |
|
415 |
#define BO_COND_TRUE BO (12) |
416 |
#define BO_COND_FALSE BO ( 4) |
417 |
#define BO_ALWAYS BO (20) |
418 |
|
419 |
enum {
|
420 |
CR_LT, |
421 |
CR_GT, |
422 |
CR_EQ, |
423 |
CR_SO |
424 |
}; |
425 |
|
426 |
static const uint32_t tcg_to_bc[10] = { |
427 |
[TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
|
428 |
[TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
|
429 |
[TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
|
430 |
[TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
|
431 |
[TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
|
432 |
[TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
|
433 |
[TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
|
434 |
[TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
|
435 |
[TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
|
436 |
[TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
|
437 |
}; |
438 |
|
439 |
static void tcg_out_mov (TCGContext *s, int ret, int arg) |
440 |
{ |
441 |
tcg_out32 (s, OR | SAB (arg, ret, arg)); |
442 |
} |
443 |
|
444 |
static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb) |
445 |
{ |
446 |
sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1); |
447 |
mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f)); |
448 |
tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb); |
449 |
} |
450 |
|
451 |
static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg) |
452 |
{ |
453 |
if (arg == (int16_t) arg)
|
454 |
tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); |
455 |
else {
|
456 |
tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff)); |
457 |
if (arg & 0xffff) |
458 |
tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
|
459 |
} |
460 |
} |
461 |
|
462 |
static void tcg_out_movi (TCGContext *s, TCGType type, |
463 |
int ret, tcg_target_long arg)
|
464 |
{ |
465 |
int32_t arg32 = arg; |
466 |
arg = type == TCG_TYPE_I32 ? arg & 0xffffffff : arg;
|
467 |
|
468 |
if (arg == arg32) {
|
469 |
tcg_out_movi32 (s, ret, arg32); |
470 |
} |
471 |
else {
|
472 |
if ((uint64_t) arg >> 32) { |
473 |
uint16_t h16 = arg >> 16;
|
474 |
uint16_t l16 = arg; |
475 |
|
476 |
tcg_out_movi32 (s, ret, arg >> 32);
|
477 |
tcg_out_rld (s, RLDICR, ret, ret, 32, 31); |
478 |
if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
|
479 |
if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
|
480 |
} |
481 |
else {
|
482 |
tcg_out_movi32 (s, ret, arg32); |
483 |
if (arg32 < 0) |
484 |
tcg_out_rld (s, RLDICL, ret, ret, 0, 32); |
485 |
} |
486 |
} |
487 |
} |
488 |
|
489 |
static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target) |
490 |
{ |
491 |
tcg_target_long disp; |
492 |
|
493 |
disp = target - (tcg_target_long) s->code_ptr; |
494 |
if ((disp << 38) >> 38 == disp) |
495 |
tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
|
496 |
else {
|
497 |
tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
|
498 |
tcg_out32 (s, MTSPR | RS (0) | CTR);
|
499 |
tcg_out32 (s, BCCTR | BO_ALWAYS | mask); |
500 |
} |
501 |
} |
502 |
|
503 |
static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg) |
504 |
{ |
505 |
#ifdef __APPLE__
|
506 |
if (const_arg) {
|
507 |
tcg_out_b (s, LK, arg); |
508 |
} |
509 |
else {
|
510 |
tcg_out32 (s, MTSPR | RS (arg) | LR); |
511 |
tcg_out32 (s, BCLR | BO_ALWAYS | LK); |
512 |
} |
513 |
#else
|
514 |
int reg;
|
515 |
|
516 |
if (const_arg) {
|
517 |
reg = 2;
|
518 |
tcg_out_movi (s, TCG_TYPE_I64, reg, arg); |
519 |
} |
520 |
else reg = arg;
|
521 |
|
522 |
tcg_out32 (s, LD | RT (0) | RA (reg));
|
523 |
tcg_out32 (s, MTSPR | RA (0) | CTR);
|
524 |
tcg_out32 (s, LD | RT (11) | RA (reg) | 16); |
525 |
tcg_out32 (s, LD | RT (2) | RA (reg) | 8); |
526 |
tcg_out32 (s, BCCTR | BO_ALWAYS | LK); |
527 |
#endif
|
528 |
} |
529 |
|
530 |
static void tcg_out_ldst (TCGContext *s, int ret, int addr, |
531 |
int offset, int op1, int op2) |
532 |
{ |
533 |
if (offset == (int16_t) offset)
|
534 |
tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
|
535 |
else {
|
536 |
tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
|
537 |
tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
|
538 |
} |
539 |
} |
540 |
|
541 |
static void tcg_out_ldsta (TCGContext *s, int ret, int addr, |
542 |
int offset, int op1, int op2) |
543 |
{ |
544 |
if (offset == (int16_t) (offset & ~3)) |
545 |
tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
|
546 |
else {
|
547 |
tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
|
548 |
tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
|
549 |
} |
550 |
} |
551 |
|
552 |
#if defined (CONFIG_SOFTMMU)
|
553 |
|
554 |
#include "../../softmmu_defs.h" |
555 |
|
556 |
static void *qemu_ld_helpers[4] = { |
557 |
__ldb_mmu, |
558 |
__ldw_mmu, |
559 |
__ldl_mmu, |
560 |
__ldq_mmu, |
561 |
}; |
562 |
|
563 |
static void *qemu_st_helpers[4] = { |
564 |
__stb_mmu, |
565 |
__stw_mmu, |
566 |
__stl_mmu, |
567 |
__stq_mmu, |
568 |
}; |
569 |
|
570 |
static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2, |
571 |
int addr_reg, int s_bits, int offset) |
572 |
{ |
573 |
#if TARGET_LONG_BITS == 32 |
574 |
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); |
575 |
|
576 |
tcg_out32 (s, (RLWINM |
577 |
| RA (r0) |
578 |
| RS (addr_reg) |
579 |
| SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
|
580 |
| MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
|
581 |
| ME (31 - CPU_TLB_ENTRY_BITS)
|
582 |
) |
583 |
); |
584 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0)); |
585 |
tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset)); |
586 |
tcg_out32 (s, (RLWINM |
587 |
| RA (r2) |
588 |
| RS (addr_reg) |
589 |
| SH (0)
|
590 |
| MB ((32 - s_bits) & 31) |
591 |
| ME (31 - TARGET_PAGE_BITS)
|
592 |
) |
593 |
); |
594 |
#else
|
595 |
tcg_out_rld (s, RLDICL, r0, addr_reg, |
596 |
64 - TARGET_PAGE_BITS,
|
597 |
64 - CPU_TLB_BITS);
|
598 |
tcg_out_rld (s, RLDICR, r0, r0, |
599 |
CPU_TLB_ENTRY_BITS, |
600 |
63 - CPU_TLB_ENTRY_BITS);
|
601 |
|
602 |
tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0)); |
603 |
tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset); |
604 |
|
605 |
if (!s_bits) {
|
606 |
tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS); |
607 |
} |
608 |
else {
|
609 |
tcg_out_rld (s, RLDICL, r2, addr_reg, |
610 |
64 - TARGET_PAGE_BITS,
|
611 |
TARGET_PAGE_BITS - s_bits); |
612 |
tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
|
613 |
} |
614 |
#endif
|
615 |
} |
616 |
#endif
|
617 |
|
618 |
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) |
619 |
{ |
620 |
int addr_reg, data_reg, r0, r1, rbase, mem_index, s_bits, bswap;
|
621 |
#ifdef CONFIG_SOFTMMU
|
622 |
int r2;
|
623 |
void *label1_ptr, *label2_ptr;
|
624 |
#endif
|
625 |
|
626 |
data_reg = *args++; |
627 |
addr_reg = *args++; |
628 |
mem_index = *args; |
629 |
s_bits = opc & 3;
|
630 |
|
631 |
#ifdef CONFIG_SOFTMMU
|
632 |
r0 = 3;
|
633 |
r1 = 4;
|
634 |
r2 = 0;
|
635 |
rbase = 0;
|
636 |
|
637 |
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits, |
638 |
offsetof (CPUState, tlb_table[mem_index][0].addr_read));
|
639 |
|
640 |
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
|
641 |
|
642 |
label1_ptr = s->code_ptr; |
643 |
#ifdef FAST_PATH
|
644 |
tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
|
645 |
#endif
|
646 |
|
647 |
/* slow path */
|
648 |
tcg_out_mov (s, 3, addr_reg);
|
649 |
tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
|
650 |
|
651 |
tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
|
652 |
|
653 |
switch (opc) {
|
654 |
case 0|4: |
655 |
tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
|
656 |
break;
|
657 |
case 1|4: |
658 |
tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
|
659 |
break;
|
660 |
case 2|4: |
661 |
tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
|
662 |
break;
|
663 |
case 0: |
664 |
case 1: |
665 |
case 2: |
666 |
case 3: |
667 |
if (data_reg != 3) |
668 |
tcg_out_mov (s, data_reg, 3);
|
669 |
break;
|
670 |
} |
671 |
label2_ptr = s->code_ptr; |
672 |
tcg_out32 (s, B); |
673 |
|
674 |
/* label1: fast path */
|
675 |
#ifdef FAST_PATH
|
676 |
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr); |
677 |
#endif
|
678 |
|
679 |
/* r0 now contains &env->tlb_table[mem_index][index].addr_read */
|
680 |
tcg_out32 (s, (LD_ADDEND |
681 |
| RT (r0) |
682 |
| RA (r0) |
683 |
| (offsetof (CPUTLBEntry, addend) |
684 |
- offsetof (CPUTLBEntry, addr_read)) |
685 |
)); |
686 |
/* r0 = env->tlb_table[mem_index][index].addend */
|
687 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); |
688 |
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
689 |
|
690 |
#else /* !CONFIG_SOFTMMU */ |
691 |
#if TARGET_LONG_BITS == 32 |
692 |
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); |
693 |
#endif
|
694 |
r0 = addr_reg; |
695 |
r1 = 3;
|
696 |
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
|
697 |
#endif
|
698 |
|
699 |
#ifdef TARGET_WORDS_BIGENDIAN
|
700 |
bswap = 0;
|
701 |
#else
|
702 |
bswap = 1;
|
703 |
#endif
|
704 |
switch (opc) {
|
705 |
default:
|
706 |
case 0: |
707 |
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0)); |
708 |
break;
|
709 |
case 0|4: |
710 |
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0)); |
711 |
tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg)); |
712 |
break;
|
713 |
case 1: |
714 |
if (bswap)
|
715 |
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0)); |
716 |
else
|
717 |
tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0)); |
718 |
break;
|
719 |
case 1|4: |
720 |
if (bswap) {
|
721 |
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0)); |
722 |
tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg)); |
723 |
} |
724 |
else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
|
725 |
break;
|
726 |
case 2: |
727 |
if (bswap)
|
728 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
729 |
else
|
730 |
tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0)); |
731 |
break;
|
732 |
case 2|4: |
733 |
if (bswap) {
|
734 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
735 |
tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg)); |
736 |
} |
737 |
else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
|
738 |
break;
|
739 |
case 3: |
740 |
#ifdef CONFIG_USE_GUEST_BASE
|
741 |
if (bswap) {
|
742 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
743 |
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0)); |
744 |
tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1)); |
745 |
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0); |
746 |
} |
747 |
else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
|
748 |
#else
|
749 |
if (bswap) {
|
750 |
tcg_out_movi32 (s, 0, 4); |
751 |
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0)); |
752 |
tcg_out32 (s, LWBRX | RT ( r1) | RA (r0)); |
753 |
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0); |
754 |
} |
755 |
else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
|
756 |
#endif
|
757 |
break;
|
758 |
} |
759 |
|
760 |
#ifdef CONFIG_SOFTMMU
|
761 |
reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr); |
762 |
#endif
|
763 |
} |
764 |
|
765 |
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) |
766 |
{ |
767 |
int addr_reg, r0, r1, rbase, data_reg, mem_index, bswap;
|
768 |
#ifdef CONFIG_SOFTMMU
|
769 |
int r2;
|
770 |
void *label1_ptr, *label2_ptr;
|
771 |
#endif
|
772 |
|
773 |
data_reg = *args++; |
774 |
addr_reg = *args++; |
775 |
mem_index = *args; |
776 |
|
777 |
#ifdef CONFIG_SOFTMMU
|
778 |
r0 = 3;
|
779 |
r1 = 4;
|
780 |
r2 = 0;
|
781 |
rbase = 0;
|
782 |
|
783 |
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc, |
784 |
offsetof (CPUState, tlb_table[mem_index][0].addr_write));
|
785 |
|
786 |
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
|
787 |
|
788 |
label1_ptr = s->code_ptr; |
789 |
#ifdef FAST_PATH
|
790 |
tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
|
791 |
#endif
|
792 |
|
793 |
/* slow path */
|
794 |
tcg_out_mov (s, 3, addr_reg);
|
795 |
tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc))); |
796 |
tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
|
797 |
|
798 |
tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
|
799 |
|
800 |
label2_ptr = s->code_ptr; |
801 |
tcg_out32 (s, B); |
802 |
|
803 |
/* label1: fast path */
|
804 |
#ifdef FAST_PATH
|
805 |
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr); |
806 |
#endif
|
807 |
|
808 |
tcg_out32 (s, (LD_ADDEND |
809 |
| RT (r0) |
810 |
| RA (r0) |
811 |
| (offsetof (CPUTLBEntry, addend) |
812 |
- offsetof (CPUTLBEntry, addr_write)) |
813 |
)); |
814 |
/* r0 = env->tlb_table[mem_index][index].addend */
|
815 |
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); |
816 |
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
817 |
|
818 |
#else /* !CONFIG_SOFTMMU */ |
819 |
#if TARGET_LONG_BITS == 32 |
820 |
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32); |
821 |
#endif
|
822 |
r1 = 3;
|
823 |
r0 = addr_reg; |
824 |
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
|
825 |
#endif
|
826 |
|
827 |
#ifdef TARGET_WORDS_BIGENDIAN
|
828 |
bswap = 0;
|
829 |
#else
|
830 |
bswap = 1;
|
831 |
#endif
|
832 |
switch (opc) {
|
833 |
case 0: |
834 |
tcg_out32 (s, STBX | SAB (data_reg, rbase, r0)); |
835 |
break;
|
836 |
case 1: |
837 |
if (bswap)
|
838 |
tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0)); |
839 |
else
|
840 |
tcg_out32 (s, STHX | SAB (data_reg, rbase, r0)); |
841 |
break;
|
842 |
case 2: |
843 |
if (bswap)
|
844 |
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0)); |
845 |
else
|
846 |
tcg_out32 (s, STWX | SAB (data_reg, rbase, r0)); |
847 |
break;
|
848 |
case 3: |
849 |
if (bswap) {
|
850 |
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0)); |
851 |
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
852 |
tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0); |
853 |
tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
|
854 |
} |
855 |
else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
|
856 |
break;
|
857 |
} |
858 |
|
859 |
#ifdef CONFIG_SOFTMMU
|
860 |
reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr); |
861 |
#endif
|
862 |
} |
863 |
|
864 |
void tcg_target_qemu_prologue (TCGContext *s)
|
865 |
{ |
866 |
int i, frame_size;
|
867 |
#ifndef __APPLE__
|
868 |
uint64_t addr; |
869 |
#endif
|
870 |
|
871 |
frame_size = 0
|
872 |
+ 8 /* back chain */ |
873 |
+ 8 /* CR */ |
874 |
+ 8 /* LR */ |
875 |
+ 8 /* compiler doubleword */ |
876 |
+ 8 /* link editor doubleword */ |
877 |
+ 8 /* TOC save area */ |
878 |
+ TCG_STATIC_CALL_ARGS_SIZE |
879 |
+ ARRAY_SIZE (tcg_target_callee_save_regs) * 8
|
880 |
; |
881 |
frame_size = (frame_size + 15) & ~15; |
882 |
|
883 |
#ifndef __APPLE__
|
884 |
/* First emit adhoc function descriptor */
|
885 |
addr = (uint64_t) s->code_ptr + 24;
|
886 |
tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */ |
887 |
s->code_ptr += 16; /* skip TOC and environment pointer */ |
888 |
#endif
|
889 |
|
890 |
/* Prologue */
|
891 |
tcg_out32 (s, MFSPR | RT (0) | LR);
|
892 |
tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff)); |
893 |
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i) |
894 |
tcg_out32 (s, (STD |
895 |
| RS (tcg_target_callee_save_regs[i]) |
896 |
| RA (1)
|
897 |
| (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE) |
898 |
) |
899 |
); |
900 |
tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16)); |
901 |
|
902 |
#ifdef CONFIG_USE_GUEST_BASE
|
903 |
tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE); |
904 |
#endif
|
905 |
|
906 |
tcg_out32 (s, MTSPR | RS (3) | CTR);
|
907 |
tcg_out32 (s, BCCTR | BO_ALWAYS); |
908 |
|
909 |
/* Epilogue */
|
910 |
tb_ret_addr = s->code_ptr; |
911 |
|
912 |
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i) |
913 |
tcg_out32 (s, (LD |
914 |
| RT (tcg_target_callee_save_regs[i]) |
915 |
| RA (1)
|
916 |
| (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE) |
917 |
) |
918 |
); |
919 |
tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16)); |
920 |
tcg_out32 (s, MTSPR | RS (0) | LR);
|
921 |
tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size); |
922 |
tcg_out32 (s, BCLR | BO_ALWAYS); |
923 |
} |
924 |
|
925 |
static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1, |
926 |
tcg_target_long arg2) |
927 |
{ |
928 |
if (type == TCG_TYPE_I32)
|
929 |
tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX); |
930 |
else
|
931 |
tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX); |
932 |
} |
933 |
|
934 |
static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1, |
935 |
tcg_target_long arg2) |
936 |
{ |
937 |
if (type == TCG_TYPE_I32)
|
938 |
tcg_out_ldst (s, arg, arg1, arg2, STW, STWX); |
939 |
else
|
940 |
tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX); |
941 |
} |
942 |
|
943 |
static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si) |
944 |
{ |
945 |
if (!si && rt == ra)
|
946 |
return;
|
947 |
|
948 |
if (si == (int16_t) si)
|
949 |
tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
|
950 |
else {
|
951 |
uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15); |
952 |
tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h); |
953 |
tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
|
954 |
} |
955 |
} |
956 |
|
957 |
static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si) |
958 |
{ |
959 |
/* XXX: suboptimal */
|
960 |
if (si == (int16_t) si
|
961 |
|| ((((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0)) |
962 |
ppc_addi32 (s, rt, ra, si); |
963 |
else {
|
964 |
tcg_out_movi (s, TCG_TYPE_I64, 0, si);
|
965 |
tcg_out32 (s, ADD | RT (rt) | RA (ra)); |
966 |
} |
967 |
} |
968 |
|
969 |
static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val) |
970 |
{ |
971 |
ppc_addi64 (s, reg, reg, val); |
972 |
} |
973 |
|
974 |
static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, |
975 |
int const_arg2, int cr, int arch64) |
976 |
{ |
977 |
int imm;
|
978 |
uint32_t op; |
979 |
|
980 |
switch (cond) {
|
981 |
case TCG_COND_EQ:
|
982 |
case TCG_COND_NE:
|
983 |
if (const_arg2) {
|
984 |
if ((int16_t) arg2 == arg2) {
|
985 |
op = CMPI; |
986 |
imm = 1;
|
987 |
break;
|
988 |
} |
989 |
else if ((uint16_t) arg2 == arg2) { |
990 |
op = CMPLI; |
991 |
imm = 1;
|
992 |
break;
|
993 |
} |
994 |
} |
995 |
op = CMPL; |
996 |
imm = 0;
|
997 |
break;
|
998 |
|
999 |
case TCG_COND_LT:
|
1000 |
case TCG_COND_GE:
|
1001 |
case TCG_COND_LE:
|
1002 |
case TCG_COND_GT:
|
1003 |
if (const_arg2) {
|
1004 |
if ((int16_t) arg2 == arg2) {
|
1005 |
op = CMPI; |
1006 |
imm = 1;
|
1007 |
break;
|
1008 |
} |
1009 |
} |
1010 |
op = CMP; |
1011 |
imm = 0;
|
1012 |
break;
|
1013 |
|
1014 |
case TCG_COND_LTU:
|
1015 |
case TCG_COND_GEU:
|
1016 |
case TCG_COND_LEU:
|
1017 |
case TCG_COND_GTU:
|
1018 |
if (const_arg2) {
|
1019 |
if ((uint16_t) arg2 == arg2) {
|
1020 |
op = CMPLI; |
1021 |
imm = 1;
|
1022 |
break;
|
1023 |
} |
1024 |
} |
1025 |
op = CMPL; |
1026 |
imm = 0;
|
1027 |
break;
|
1028 |
|
1029 |
default:
|
1030 |
tcg_abort (); |
1031 |
} |
1032 |
op |= BF (cr) | (arch64 << 21);
|
1033 |
|
1034 |
if (imm)
|
1035 |
tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
|
1036 |
else {
|
1037 |
if (const_arg2) {
|
1038 |
tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
|
1039 |
tcg_out32 (s, op | RA (arg1) | RB (0));
|
1040 |
} |
1041 |
else
|
1042 |
tcg_out32 (s, op | RA (arg1) | RB (arg2)); |
1043 |
} |
1044 |
|
1045 |
} |
1046 |
|
1047 |
static void tcg_out_bc (TCGContext *s, int bc, int label_index) |
1048 |
{ |
1049 |
TCGLabel *l = &s->labels[label_index]; |
1050 |
|
1051 |
if (l->has_value)
|
1052 |
tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value)); |
1053 |
else {
|
1054 |
uint16_t val = *(uint16_t *) &s->code_ptr[2];
|
1055 |
|
1056 |
/* Thanks to Andrzej Zaborowski */
|
1057 |
tcg_out32 (s, bc | (val & 0xfffc));
|
1058 |
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0); |
1059 |
} |
1060 |
} |
1061 |
|
1062 |
static void tcg_out_brcond (TCGContext *s, int cond, |
1063 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
1064 |
int label_index, int arch64) |
1065 |
{ |
1066 |
tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
|
1067 |
tcg_out_bc (s, tcg_to_bc[cond], label_index); |
1068 |
} |
1069 |
|
1070 |
void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) |
1071 |
{ |
1072 |
TCGContext s; |
1073 |
unsigned long patch_size; |
1074 |
|
1075 |
s.code_ptr = (uint8_t *) jmp_addr; |
1076 |
tcg_out_b (&s, 0, addr);
|
1077 |
patch_size = s.code_ptr - (uint8_t *) jmp_addr; |
1078 |
flush_icache_range (jmp_addr, jmp_addr + patch_size); |
1079 |
} |
1080 |
|
1081 |
static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args, |
1082 |
const int *const_args) |
1083 |
{ |
1084 |
int c;
|
1085 |
|
1086 |
switch (opc) {
|
1087 |
case INDEX_op_exit_tb:
|
1088 |
tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
|
1089 |
tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
|
1090 |
break;
|
1091 |
case INDEX_op_goto_tb:
|
1092 |
if (s->tb_jmp_offset) {
|
1093 |
/* direct jump method */
|
1094 |
|
1095 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
1096 |
s->code_ptr += 28;
|
1097 |
} |
1098 |
else {
|
1099 |
tcg_abort (); |
1100 |
} |
1101 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
1102 |
break;
|
1103 |
case INDEX_op_br:
|
1104 |
{ |
1105 |
TCGLabel *l = &s->labels[args[0]];
|
1106 |
|
1107 |
if (l->has_value) {
|
1108 |
tcg_out_b (s, 0, l->u.value);
|
1109 |
} |
1110 |
else {
|
1111 |
uint32_t val = *(uint32_t *) s->code_ptr; |
1112 |
|
1113 |
/* Thanks to Andrzej Zaborowski */
|
1114 |
tcg_out32 (s, B | (val & 0x3fffffc));
|
1115 |
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0); |
1116 |
} |
1117 |
} |
1118 |
break;
|
1119 |
case INDEX_op_call:
|
1120 |
tcg_out_call (s, args[0], const_args[0]); |
1121 |
break;
|
1122 |
case INDEX_op_jmp:
|
1123 |
if (const_args[0]) { |
1124 |
tcg_out_b (s, 0, args[0]); |
1125 |
} |
1126 |
else {
|
1127 |
tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
|
1128 |
tcg_out32 (s, BCCTR | BO_ALWAYS); |
1129 |
} |
1130 |
break;
|
1131 |
case INDEX_op_movi_i32:
|
1132 |
tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]); |
1133 |
break;
|
1134 |
case INDEX_op_movi_i64:
|
1135 |
tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]); |
1136 |
break;
|
1137 |
case INDEX_op_ld8u_i32:
|
1138 |
case INDEX_op_ld8u_i64:
|
1139 |
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX); |
1140 |
break;
|
1141 |
case INDEX_op_ld8s_i32:
|
1142 |
case INDEX_op_ld8s_i64:
|
1143 |
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX); |
1144 |
tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0])); |
1145 |
break;
|
1146 |
case INDEX_op_ld16u_i32:
|
1147 |
case INDEX_op_ld16u_i64:
|
1148 |
tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX); |
1149 |
break;
|
1150 |
case INDEX_op_ld16s_i32:
|
1151 |
case INDEX_op_ld16s_i64:
|
1152 |
tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX); |
1153 |
break;
|
1154 |
case INDEX_op_ld_i32:
|
1155 |
case INDEX_op_ld32u_i64:
|
1156 |
tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX); |
1157 |
break;
|
1158 |
case INDEX_op_ld32s_i64:
|
1159 |
tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX); |
1160 |
break;
|
1161 |
case INDEX_op_ld_i64:
|
1162 |
tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX); |
1163 |
break;
|
1164 |
case INDEX_op_st8_i32:
|
1165 |
case INDEX_op_st8_i64:
|
1166 |
tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX); |
1167 |
break;
|
1168 |
case INDEX_op_st16_i32:
|
1169 |
case INDEX_op_st16_i64:
|
1170 |
tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX); |
1171 |
break;
|
1172 |
case INDEX_op_st_i32:
|
1173 |
case INDEX_op_st32_i64:
|
1174 |
tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX); |
1175 |
break;
|
1176 |
case INDEX_op_st_i64:
|
1177 |
tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX); |
1178 |
break;
|
1179 |
|
1180 |
case INDEX_op_add_i32:
|
1181 |
if (const_args[2]) |
1182 |
ppc_addi32 (s, args[0], args[1], args[2]); |
1183 |
else
|
1184 |
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2])); |
1185 |
break;
|
1186 |
case INDEX_op_sub_i32:
|
1187 |
if (const_args[2]) |
1188 |
ppc_addi32 (s, args[0], args[1], -args[2]); |
1189 |
else
|
1190 |
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1])); |
1191 |
break;
|
1192 |
|
1193 |
case INDEX_op_and_i64:
|
1194 |
case INDEX_op_and_i32:
|
1195 |
if (const_args[2]) { |
1196 |
if ((args[2] & 0xffff) == args[2]) |
1197 |
tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]); |
1198 |
else if ((args[2] & 0xffff0000) == args[2]) |
1199 |
tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0]) |
1200 |
| ((args[2] >> 16) & 0xffff)); |
1201 |
else {
|
1202 |
tcg_out_movi (s, (opc == INDEX_op_and_i32 |
1203 |
? TCG_TYPE_I32 |
1204 |
: TCG_TYPE_I64), |
1205 |
0, args[2]); |
1206 |
tcg_out32 (s, AND | SAB (args[1], args[0], 0)); |
1207 |
} |
1208 |
} |
1209 |
else
|
1210 |
tcg_out32 (s, AND | SAB (args[1], args[0], args[2])); |
1211 |
break;
|
1212 |
case INDEX_op_or_i64:
|
1213 |
case INDEX_op_or_i32:
|
1214 |
if (const_args[2]) { |
1215 |
if (args[2] & 0xffff) { |
1216 |
tcg_out32 (s, ORI | RS (args[1]) | RA (args[0]) |
1217 |
| (args[2] & 0xffff)); |
1218 |
if (args[2] >> 16) |
1219 |
tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0]) |
1220 |
| ((args[2] >> 16) & 0xffff)); |
1221 |
} |
1222 |
else {
|
1223 |
tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0]) |
1224 |
| ((args[2] >> 16) & 0xffff)); |
1225 |
} |
1226 |
} |
1227 |
else
|
1228 |
tcg_out32 (s, OR | SAB (args[1], args[0], args[2])); |
1229 |
break;
|
1230 |
case INDEX_op_xor_i64:
|
1231 |
case INDEX_op_xor_i32:
|
1232 |
if (const_args[2]) { |
1233 |
if ((args[2] & 0xffff) == args[2]) |
1234 |
tcg_out32 (s, XORI | RS (args[1]) | RA (args[0]) |
1235 |
| (args[2] & 0xffff)); |
1236 |
else if ((args[2] & 0xffff0000) == args[2]) |
1237 |
tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0]) |
1238 |
| ((args[2] >> 16) & 0xffff)); |
1239 |
else {
|
1240 |
tcg_out_movi (s, (opc == INDEX_op_and_i32 |
1241 |
? TCG_TYPE_I32 |
1242 |
: TCG_TYPE_I64), |
1243 |
0, args[2]); |
1244 |
tcg_out32 (s, XOR | SAB (args[1], args[0], 0)); |
1245 |
} |
1246 |
} |
1247 |
else
|
1248 |
tcg_out32 (s, XOR | SAB (args[1], args[0], args[2])); |
1249 |
break;
|
1250 |
|
1251 |
case INDEX_op_mul_i32:
|
1252 |
if (const_args[2]) { |
1253 |
if (args[2] == (int16_t) args[2]) |
1254 |
tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1]) |
1255 |
| (args[2] & 0xffff)); |
1256 |
else {
|
1257 |
tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]); |
1258 |
tcg_out32 (s, MULLW | TAB (args[0], args[1], 0)); |
1259 |
} |
1260 |
} |
1261 |
else
|
1262 |
tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2])); |
1263 |
break;
|
1264 |
|
1265 |
case INDEX_op_div_i32:
|
1266 |
tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2])); |
1267 |
break;
|
1268 |
|
1269 |
case INDEX_op_divu_i32:
|
1270 |
tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2])); |
1271 |
break;
|
1272 |
|
1273 |
case INDEX_op_rem_i32:
|
1274 |
tcg_out32 (s, DIVW | TAB (0, args[1], args[2])); |
1275 |
tcg_out32 (s, MULLW | TAB (0, 0, args[2])); |
1276 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
1277 |
break;
|
1278 |
|
1279 |
case INDEX_op_remu_i32:
|
1280 |
tcg_out32 (s, DIVWU | TAB (0, args[1], args[2])); |
1281 |
tcg_out32 (s, MULLW | TAB (0, 0, args[2])); |
1282 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
1283 |
break;
|
1284 |
|
1285 |
case INDEX_op_shl_i32:
|
1286 |
if (const_args[2]) { |
1287 |
tcg_out32 (s, (RLWINM |
1288 |
| RA (args[0])
|
1289 |
| RS (args[1])
|
1290 |
| SH (args[2])
|
1291 |
| MB (0)
|
1292 |
| ME (31 - args[2]) |
1293 |
) |
1294 |
); |
1295 |
} |
1296 |
else
|
1297 |
tcg_out32 (s, SLW | SAB (args[1], args[0], args[2])); |
1298 |
break;
|
1299 |
case INDEX_op_shr_i32:
|
1300 |
if (const_args[2]) { |
1301 |
tcg_out32 (s, (RLWINM |
1302 |
| RA (args[0])
|
1303 |
| RS (args[1])
|
1304 |
| SH (32 - args[2]) |
1305 |
| MB (args[2])
|
1306 |
| ME (31)
|
1307 |
) |
1308 |
); |
1309 |
} |
1310 |
else
|
1311 |
tcg_out32 (s, SRW | SAB (args[1], args[0], args[2])); |
1312 |
break;
|
1313 |
case INDEX_op_sar_i32:
|
1314 |
if (const_args[2]) |
1315 |
tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2])); |
1316 |
else
|
1317 |
tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2])); |
1318 |
break;
|
1319 |
|
1320 |
case INDEX_op_brcond_i32:
|
1321 |
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0); |
1322 |
break;
|
1323 |
|
1324 |
case INDEX_op_brcond_i64:
|
1325 |
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1); |
1326 |
break;
|
1327 |
|
1328 |
case INDEX_op_neg_i32:
|
1329 |
case INDEX_op_neg_i64:
|
1330 |
tcg_out32 (s, NEG | RT (args[0]) | RA (args[1])); |
1331 |
break;
|
1332 |
|
1333 |
case INDEX_op_add_i64:
|
1334 |
if (const_args[2]) |
1335 |
ppc_addi64 (s, args[0], args[1], args[2]); |
1336 |
else
|
1337 |
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2])); |
1338 |
break;
|
1339 |
case INDEX_op_sub_i64:
|
1340 |
if (const_args[2]) |
1341 |
ppc_addi64 (s, args[0], args[1], -args[2]); |
1342 |
else
|
1343 |
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1])); |
1344 |
break;
|
1345 |
|
1346 |
case INDEX_op_shl_i64:
|
1347 |
if (const_args[2]) |
1348 |
tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]); |
1349 |
else
|
1350 |
tcg_out32 (s, SLD | SAB (args[1], args[0], args[2])); |
1351 |
break;
|
1352 |
case INDEX_op_shr_i64:
|
1353 |
if (const_args[2]) |
1354 |
tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]); |
1355 |
else
|
1356 |
tcg_out32 (s, SRD | SAB (args[1], args[0], args[2])); |
1357 |
break;
|
1358 |
case INDEX_op_sar_i64:
|
1359 |
if (const_args[2]) { |
1360 |
int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); |
1361 |
tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh); |
1362 |
} |
1363 |
else
|
1364 |
tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2])); |
1365 |
break;
|
1366 |
|
1367 |
case INDEX_op_mul_i64:
|
1368 |
tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2])); |
1369 |
break;
|
1370 |
case INDEX_op_div_i64:
|
1371 |
tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2])); |
1372 |
break;
|
1373 |
case INDEX_op_divu_i64:
|
1374 |
tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2])); |
1375 |
break;
|
1376 |
case INDEX_op_rem_i64:
|
1377 |
tcg_out32 (s, DIVD | TAB (0, args[1], args[2])); |
1378 |
tcg_out32 (s, MULLD | TAB (0, 0, args[2])); |
1379 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
1380 |
break;
|
1381 |
case INDEX_op_remu_i64:
|
1382 |
tcg_out32 (s, DIVDU | TAB (0, args[1], args[2])); |
1383 |
tcg_out32 (s, MULLD | TAB (0, 0, args[2])); |
1384 |
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1])); |
1385 |
break;
|
1386 |
|
1387 |
case INDEX_op_qemu_ld8u:
|
1388 |
tcg_out_qemu_ld (s, args, 0);
|
1389 |
break;
|
1390 |
case INDEX_op_qemu_ld8s:
|
1391 |
tcg_out_qemu_ld (s, args, 0 | 4); |
1392 |
break;
|
1393 |
case INDEX_op_qemu_ld16u:
|
1394 |
tcg_out_qemu_ld (s, args, 1);
|
1395 |
break;
|
1396 |
case INDEX_op_qemu_ld16s:
|
1397 |
tcg_out_qemu_ld (s, args, 1 | 4); |
1398 |
break;
|
1399 |
case INDEX_op_qemu_ld32u:
|
1400 |
tcg_out_qemu_ld (s, args, 2);
|
1401 |
break;
|
1402 |
case INDEX_op_qemu_ld32s:
|
1403 |
tcg_out_qemu_ld (s, args, 2 | 4); |
1404 |
break;
|
1405 |
case INDEX_op_qemu_ld64:
|
1406 |
tcg_out_qemu_ld (s, args, 3);
|
1407 |
break;
|
1408 |
case INDEX_op_qemu_st8:
|
1409 |
tcg_out_qemu_st (s, args, 0);
|
1410 |
break;
|
1411 |
case INDEX_op_qemu_st16:
|
1412 |
tcg_out_qemu_st (s, args, 1);
|
1413 |
break;
|
1414 |
case INDEX_op_qemu_st32:
|
1415 |
tcg_out_qemu_st (s, args, 2);
|
1416 |
break;
|
1417 |
case INDEX_op_qemu_st64:
|
1418 |
tcg_out_qemu_st (s, args, 3);
|
1419 |
break;
|
1420 |
|
1421 |
case INDEX_op_ext8s_i32:
|
1422 |
case INDEX_op_ext8s_i64:
|
1423 |
c = EXTSB; |
1424 |
goto gen_ext;
|
1425 |
case INDEX_op_ext16s_i32:
|
1426 |
case INDEX_op_ext16s_i64:
|
1427 |
c = EXTSH; |
1428 |
goto gen_ext;
|
1429 |
case INDEX_op_ext32s_i64:
|
1430 |
c = EXTSW; |
1431 |
goto gen_ext;
|
1432 |
gen_ext:
|
1433 |
tcg_out32 (s, c | RS (args[1]) | RA (args[0])); |
1434 |
break;
|
1435 |
|
1436 |
default:
|
1437 |
tcg_dump_ops (s, stderr); |
1438 |
tcg_abort (); |
1439 |
} |
1440 |
} |
1441 |
|
1442 |
static const TCGTargetOpDef ppc_op_defs[] = { |
1443 |
{ INDEX_op_exit_tb, { } }, |
1444 |
{ INDEX_op_goto_tb, { } }, |
1445 |
{ INDEX_op_call, { "ri" } },
|
1446 |
{ INDEX_op_jmp, { "ri" } },
|
1447 |
{ INDEX_op_br, { } }, |
1448 |
|
1449 |
{ INDEX_op_mov_i32, { "r", "r" } }, |
1450 |
{ INDEX_op_mov_i64, { "r", "r" } }, |
1451 |
{ INDEX_op_movi_i32, { "r" } },
|
1452 |
{ INDEX_op_movi_i64, { "r" } },
|
1453 |
|
1454 |
{ INDEX_op_ld8u_i32, { "r", "r" } }, |
1455 |
{ INDEX_op_ld8s_i32, { "r", "r" } }, |
1456 |
{ INDEX_op_ld16u_i32, { "r", "r" } }, |
1457 |
{ INDEX_op_ld16s_i32, { "r", "r" } }, |
1458 |
{ INDEX_op_ld_i32, { "r", "r" } }, |
1459 |
{ INDEX_op_ld_i64, { "r", "r" } }, |
1460 |
{ INDEX_op_st8_i32, { "r", "r" } }, |
1461 |
{ INDEX_op_st8_i64, { "r", "r" } }, |
1462 |
{ INDEX_op_st16_i32, { "r", "r" } }, |
1463 |
{ INDEX_op_st16_i64, { "r", "r" } }, |
1464 |
{ INDEX_op_st_i32, { "r", "r" } }, |
1465 |
{ INDEX_op_st_i64, { "r", "r" } }, |
1466 |
{ INDEX_op_st32_i64, { "r", "r" } }, |
1467 |
|
1468 |
{ INDEX_op_ld8u_i64, { "r", "r" } }, |
1469 |
{ INDEX_op_ld8s_i64, { "r", "r" } }, |
1470 |
{ INDEX_op_ld16u_i64, { "r", "r" } }, |
1471 |
{ INDEX_op_ld16s_i64, { "r", "r" } }, |
1472 |
{ INDEX_op_ld32u_i64, { "r", "r" } }, |
1473 |
{ INDEX_op_ld32s_i64, { "r", "r" } }, |
1474 |
{ INDEX_op_ld_i64, { "r", "r" } }, |
1475 |
|
1476 |
{ INDEX_op_add_i32, { "r", "r", "ri" } }, |
1477 |
{ INDEX_op_mul_i32, { "r", "r", "ri" } }, |
1478 |
{ INDEX_op_div_i32, { "r", "r", "r" } }, |
1479 |
{ INDEX_op_divu_i32, { "r", "r", "r" } }, |
1480 |
{ INDEX_op_rem_i32, { "r", "r", "r" } }, |
1481 |
{ INDEX_op_remu_i32, { "r", "r", "r" } }, |
1482 |
{ INDEX_op_sub_i32, { "r", "r", "ri" } }, |
1483 |
{ INDEX_op_and_i32, { "r", "r", "ri" } }, |
1484 |
{ INDEX_op_or_i32, { "r", "r", "ri" } }, |
1485 |
{ INDEX_op_xor_i32, { "r", "r", "ri" } }, |
1486 |
|
1487 |
{ INDEX_op_shl_i32, { "r", "r", "ri" } }, |
1488 |
{ INDEX_op_shr_i32, { "r", "r", "ri" } }, |
1489 |
{ INDEX_op_sar_i32, { "r", "r", "ri" } }, |
1490 |
|
1491 |
{ INDEX_op_brcond_i32, { "r", "ri" } }, |
1492 |
{ INDEX_op_brcond_i64, { "r", "ri" } }, |
1493 |
|
1494 |
{ INDEX_op_neg_i32, { "r", "r" } }, |
1495 |
|
1496 |
{ INDEX_op_add_i64, { "r", "r", "ri" } }, |
1497 |
{ INDEX_op_sub_i64, { "r", "r", "ri" } }, |
1498 |
{ INDEX_op_and_i64, { "r", "r", "rZ" } }, |
1499 |
{ INDEX_op_or_i64, { "r", "r", "rZ" } }, |
1500 |
{ INDEX_op_xor_i64, { "r", "r", "rZ" } }, |
1501 |
|
1502 |
{ INDEX_op_shl_i64, { "r", "r", "ri" } }, |
1503 |
{ INDEX_op_shr_i64, { "r", "r", "ri" } }, |
1504 |
{ INDEX_op_sar_i64, { "r", "r", "ri" } }, |
1505 |
|
1506 |
{ INDEX_op_mul_i64, { "r", "r", "r" } }, |
1507 |
{ INDEX_op_div_i64, { "r", "r", "r" } }, |
1508 |
{ INDEX_op_divu_i64, { "r", "r", "r" } }, |
1509 |
{ INDEX_op_rem_i64, { "r", "r", "r" } }, |
1510 |
{ INDEX_op_remu_i64, { "r", "r", "r" } }, |
1511 |
|
1512 |
{ INDEX_op_neg_i64, { "r", "r" } }, |
1513 |
|
1514 |
{ INDEX_op_qemu_ld8u, { "r", "L" } }, |
1515 |
{ INDEX_op_qemu_ld8s, { "r", "L" } }, |
1516 |
{ INDEX_op_qemu_ld16u, { "r", "L" } }, |
1517 |
{ INDEX_op_qemu_ld16s, { "r", "L" } }, |
1518 |
{ INDEX_op_qemu_ld32u, { "r", "L" } }, |
1519 |
{ INDEX_op_qemu_ld32s, { "r", "L" } }, |
1520 |
{ INDEX_op_qemu_ld64, { "r", "L" } }, |
1521 |
|
1522 |
{ INDEX_op_qemu_st8, { "S", "S" } }, |
1523 |
{ INDEX_op_qemu_st16, { "S", "S" } }, |
1524 |
{ INDEX_op_qemu_st32, { "S", "S" } }, |
1525 |
{ INDEX_op_qemu_st64, { "S", "S" } }, |
1526 |
|
1527 |
{ INDEX_op_ext8s_i32, { "r", "r" } }, |
1528 |
{ INDEX_op_ext16s_i32, { "r", "r" } }, |
1529 |
{ INDEX_op_ext8s_i64, { "r", "r" } }, |
1530 |
{ INDEX_op_ext16s_i64, { "r", "r" } }, |
1531 |
{ INDEX_op_ext32s_i64, { "r", "r" } }, |
1532 |
|
1533 |
{ -1 },
|
1534 |
}; |
1535 |
|
1536 |
void tcg_target_init (TCGContext *s)
|
1537 |
{ |
1538 |
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
1539 |
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
1540 |
tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
|
1541 |
(1 << TCG_REG_R0) |
|
1542 |
#ifdef __APPLE__
|
1543 |
(1 << TCG_REG_R2) |
|
1544 |
#endif
|
1545 |
(1 << TCG_REG_R3) |
|
1546 |
(1 << TCG_REG_R4) |
|
1547 |
(1 << TCG_REG_R5) |
|
1548 |
(1 << TCG_REG_R6) |
|
1549 |
(1 << TCG_REG_R7) |
|
1550 |
(1 << TCG_REG_R8) |
|
1551 |
(1 << TCG_REG_R9) |
|
1552 |
(1 << TCG_REG_R10) |
|
1553 |
(1 << TCG_REG_R11) |
|
1554 |
(1 << TCG_REG_R12)
|
1555 |
); |
1556 |
|
1557 |
tcg_regset_clear (s->reserved_regs); |
1558 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0); |
1559 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1); |
1560 |
#ifndef __APPLE__
|
1561 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2); |
1562 |
#endif
|
1563 |
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13); |
1564 |
|
1565 |
#ifdef CONFIG_USE_GUEST_BASE
|
1566 |
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
1567 |
#endif
|
1568 |
|
1569 |
tcg_add_target_add_op_defs (ppc_op_defs); |
1570 |
} |