Revision 593f17e5 target-alpha/translate.c
b/target-alpha/translate.c | ||
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598 | 598 |
gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact); |
599 | 599 |
} |
600 | 600 |
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601 |
static void gen_fcvtlq(int rb, int rc) |
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602 |
{ |
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603 |
if (unlikely(rc == 31)) { |
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604 |
return; |
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605 |
} |
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606 |
if (unlikely(rb == 31)) { |
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607 |
tcg_gen_movi_i64(cpu_fir[rc], 0); |
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608 |
} else { |
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609 |
TCGv tmp = tcg_temp_new(); |
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610 |
|
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611 |
/* The arithmetic right shift here, plus the sign-extended mask below |
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612 |
yields a sign-extended result without an explicit ext32s_i64. */ |
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613 |
tcg_gen_sari_i64(tmp, cpu_fir[rb], 32); |
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614 |
tcg_gen_shri_i64(cpu_fir[rc], cpu_fir[rb], 29); |
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615 |
tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000); |
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616 |
tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rc], 0x3fffffff); |
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617 |
tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp); |
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618 |
|
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619 |
tcg_temp_free(tmp); |
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620 |
} |
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621 |
} |
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622 |
|
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601 | 623 |
static void gen_fcvtql(int rb, int rc) |
602 | 624 |
{ |
603 | 625 |
if (unlikely(rc == 31)) { |
... | ... | |
647 | 669 |
tcg_temp_free(tmp); \ |
648 | 670 |
} \ |
649 | 671 |
} |
650 |
FARITH2(cvtlq) |
|
651 | 672 |
|
652 | 673 |
/* ??? VAX instruction qualifiers ignored. */ |
653 | 674 |
FARITH2(sqrtf) |
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