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1
/*
2
 * gdb server stub
3
 *
4
 * Copyright (c) 2003-2005 Fabrice Bellard
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18
 */
19
#include "config.h"
20
#include "qemu-common.h"
21
#ifdef CONFIG_USER_ONLY
22
#include <stdlib.h>
23
#include <stdio.h>
24
#include <stdarg.h>
25
#include <string.h>
26
#include <errno.h>
27
#include <unistd.h>
28
#include <fcntl.h>
29

    
30
#include "qemu.h"
31
#else
32
#include "monitor.h"
33
#include "qemu-char.h"
34
#include "sysemu.h"
35
#include "gdbstub.h"
36
#endif
37

    
38
#define MAX_PACKET_LENGTH 4096
39

    
40
#include "exec-all.h"
41
#include "qemu_socket.h"
42
#include "kvm.h"
43

    
44

    
45
enum {
46
    GDB_SIGNAL_0 = 0,
47
    GDB_SIGNAL_INT = 2,
48
    GDB_SIGNAL_QUIT = 3,
49
    GDB_SIGNAL_TRAP = 5,
50
    GDB_SIGNAL_ABRT = 6,
51
    GDB_SIGNAL_ALRM = 14,
52
    GDB_SIGNAL_IO = 23,
53
    GDB_SIGNAL_XCPU = 24,
54
    GDB_SIGNAL_UNKNOWN = 143
55
};
56

    
57
#ifdef CONFIG_USER_ONLY
58

    
59
/* Map target signal numbers to GDB protocol signal numbers and vice
60
 * versa.  For user emulation's currently supported systems, we can
61
 * assume most signals are defined.
62
 */
63

    
64
static int gdb_signal_table[] = {
65
    0,
66
    TARGET_SIGHUP,
67
    TARGET_SIGINT,
68
    TARGET_SIGQUIT,
69
    TARGET_SIGILL,
70
    TARGET_SIGTRAP,
71
    TARGET_SIGABRT,
72
    -1, /* SIGEMT */
73
    TARGET_SIGFPE,
74
    TARGET_SIGKILL,
75
    TARGET_SIGBUS,
76
    TARGET_SIGSEGV,
77
    TARGET_SIGSYS,
78
    TARGET_SIGPIPE,
79
    TARGET_SIGALRM,
80
    TARGET_SIGTERM,
81
    TARGET_SIGURG,
82
    TARGET_SIGSTOP,
83
    TARGET_SIGTSTP,
84
    TARGET_SIGCONT,
85
    TARGET_SIGCHLD,
86
    TARGET_SIGTTIN,
87
    TARGET_SIGTTOU,
88
    TARGET_SIGIO,
89
    TARGET_SIGXCPU,
90
    TARGET_SIGXFSZ,
91
    TARGET_SIGVTALRM,
92
    TARGET_SIGPROF,
93
    TARGET_SIGWINCH,
94
    -1, /* SIGLOST */
95
    TARGET_SIGUSR1,
96
    TARGET_SIGUSR2,
97
#ifdef TARGET_SIGPWR
98
    TARGET_SIGPWR,
99
#else
100
    -1,
101
#endif
102
    -1, /* SIGPOLL */
103
    -1,
104
    -1,
105
    -1,
106
    -1,
107
    -1,
108
    -1,
109
    -1,
110
    -1,
111
    -1,
112
    -1,
113
    -1,
114
#ifdef __SIGRTMIN
115
    __SIGRTMIN + 1,
116
    __SIGRTMIN + 2,
117
    __SIGRTMIN + 3,
118
    __SIGRTMIN + 4,
119
    __SIGRTMIN + 5,
120
    __SIGRTMIN + 6,
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    __SIGRTMIN + 7,
122
    __SIGRTMIN + 8,
123
    __SIGRTMIN + 9,
124
    __SIGRTMIN + 10,
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    __SIGRTMIN + 11,
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    __SIGRTMIN + 12,
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    __SIGRTMIN + 13,
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    __SIGRTMIN + 14,
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    __SIGRTMIN + 15,
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    __SIGRTMIN + 16,
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    __SIGRTMIN + 17,
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    __SIGRTMIN + 18,
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    __SIGRTMIN + 19,
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    __SIGRTMIN + 20,
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    __SIGRTMIN + 21,
136
    __SIGRTMIN + 22,
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    __SIGRTMIN + 23,
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    __SIGRTMIN + 24,
139
    __SIGRTMIN + 25,
140
    __SIGRTMIN + 26,
141
    __SIGRTMIN + 27,
142
    __SIGRTMIN + 28,
143
    __SIGRTMIN + 29,
144
    __SIGRTMIN + 30,
145
    __SIGRTMIN + 31,
146
    -1, /* SIGCANCEL */
147
    __SIGRTMIN,
148
    __SIGRTMIN + 32,
149
    __SIGRTMIN + 33,
150
    __SIGRTMIN + 34,
151
    __SIGRTMIN + 35,
152
    __SIGRTMIN + 36,
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    __SIGRTMIN + 37,
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    __SIGRTMIN + 38,
155
    __SIGRTMIN + 39,
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    __SIGRTMIN + 40,
157
    __SIGRTMIN + 41,
158
    __SIGRTMIN + 42,
159
    __SIGRTMIN + 43,
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    __SIGRTMIN + 44,
161
    __SIGRTMIN + 45,
162
    __SIGRTMIN + 46,
163
    __SIGRTMIN + 47,
164
    __SIGRTMIN + 48,
165
    __SIGRTMIN + 49,
166
    __SIGRTMIN + 50,
167
    __SIGRTMIN + 51,
168
    __SIGRTMIN + 52,
169
    __SIGRTMIN + 53,
170
    __SIGRTMIN + 54,
171
    __SIGRTMIN + 55,
172
    __SIGRTMIN + 56,
173
    __SIGRTMIN + 57,
174
    __SIGRTMIN + 58,
175
    __SIGRTMIN + 59,
176
    __SIGRTMIN + 60,
177
    __SIGRTMIN + 61,
178
    __SIGRTMIN + 62,
179
    __SIGRTMIN + 63,
180
    __SIGRTMIN + 64,
181
    __SIGRTMIN + 65,
182
    __SIGRTMIN + 66,
183
    __SIGRTMIN + 67,
184
    __SIGRTMIN + 68,
185
    __SIGRTMIN + 69,
186
    __SIGRTMIN + 70,
187
    __SIGRTMIN + 71,
188
    __SIGRTMIN + 72,
189
    __SIGRTMIN + 73,
190
    __SIGRTMIN + 74,
191
    __SIGRTMIN + 75,
192
    __SIGRTMIN + 76,
193
    __SIGRTMIN + 77,
194
    __SIGRTMIN + 78,
195
    __SIGRTMIN + 79,
196
    __SIGRTMIN + 80,
197
    __SIGRTMIN + 81,
198
    __SIGRTMIN + 82,
199
    __SIGRTMIN + 83,
200
    __SIGRTMIN + 84,
201
    __SIGRTMIN + 85,
202
    __SIGRTMIN + 86,
203
    __SIGRTMIN + 87,
204
    __SIGRTMIN + 88,
205
    __SIGRTMIN + 89,
206
    __SIGRTMIN + 90,
207
    __SIGRTMIN + 91,
208
    __SIGRTMIN + 92,
209
    __SIGRTMIN + 93,
210
    __SIGRTMIN + 94,
211
    __SIGRTMIN + 95,
212
    -1, /* SIGINFO */
213
    -1, /* UNKNOWN */
214
    -1, /* DEFAULT */
215
    -1,
216
    -1,
217
    -1,
218
    -1,
219
    -1,
220
    -1
221
#endif
222
};
223
#else
224
/* In system mode we only need SIGINT and SIGTRAP; other signals
225
   are not yet supported.  */
226

    
227
enum {
228
    TARGET_SIGINT = 2,
229
    TARGET_SIGTRAP = 5
230
};
231

    
232
static int gdb_signal_table[] = {
233
    -1,
234
    -1,
235
    TARGET_SIGINT,
236
    -1,
237
    -1,
238
    TARGET_SIGTRAP
239
};
240
#endif
241

    
242
#ifdef CONFIG_USER_ONLY
243
static int target_signal_to_gdb (int sig)
244
{
245
    int i;
246
    for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
247
        if (gdb_signal_table[i] == sig)
248
            return i;
249
    return GDB_SIGNAL_UNKNOWN;
250
}
251
#endif
252

    
253
static int gdb_signal_to_target (int sig)
254
{
255
    if (sig < ARRAY_SIZE (gdb_signal_table))
256
        return gdb_signal_table[sig];
257
    else
258
        return -1;
259
}
260

    
261
//#define DEBUG_GDB
262

    
263
typedef struct GDBRegisterState {
264
    int base_reg;
265
    int num_regs;
266
    gdb_reg_cb get_reg;
267
    gdb_reg_cb set_reg;
268
    const char *xml;
269
    struct GDBRegisterState *next;
270
} GDBRegisterState;
271

    
272
enum RSState {
273
    RS_INACTIVE,
274
    RS_IDLE,
275
    RS_GETLINE,
276
    RS_CHKSUM1,
277
    RS_CHKSUM2,
278
    RS_SYSCALL,
279
};
280
typedef struct GDBState {
281
    CPUState *c_cpu; /* current CPU for step/continue ops */
282
    CPUState *g_cpu; /* current CPU for other ops */
283
    CPUState *query_cpu; /* for q{f|s}ThreadInfo */
284
    enum RSState state; /* parsing state */
285
    char line_buf[MAX_PACKET_LENGTH];
286
    int line_buf_index;
287
    int line_csum;
288
    uint8_t last_packet[MAX_PACKET_LENGTH + 4];
289
    int last_packet_len;
290
    int signal;
291
#ifdef CONFIG_USER_ONLY
292
    int fd;
293
    int running_state;
294
#else
295
    CharDriverState *chr;
296
    CharDriverState *mon_chr;
297
#endif
298
} GDBState;
299

    
300
/* By default use no IRQs and no timers while single stepping so as to
301
 * make single stepping like an ICE HW step.
302
 */
303
static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
304

    
305
static GDBState *gdbserver_state;
306

    
307
/* This is an ugly hack to cope with both new and old gdb.
308
   If gdb sends qXfer:features:read then assume we're talking to a newish
309
   gdb that understands target descriptions.  */
310
static int gdb_has_xml;
311

    
312
#ifdef CONFIG_USER_ONLY
313
/* XXX: This is not thread safe.  Do we care?  */
314
static int gdbserver_fd = -1;
315

    
316
static int get_char(GDBState *s)
317
{
318
    uint8_t ch;
319
    int ret;
320

    
321
    for(;;) {
322
        ret = recv(s->fd, &ch, 1, 0);
323
        if (ret < 0) {
324
            if (errno == ECONNRESET)
325
                s->fd = -1;
326
            if (errno != EINTR && errno != EAGAIN)
327
                return -1;
328
        } else if (ret == 0) {
329
            close(s->fd);
330
            s->fd = -1;
331
            return -1;
332
        } else {
333
            break;
334
        }
335
    }
336
    return ch;
337
}
338
#endif
339

    
340
static gdb_syscall_complete_cb gdb_current_syscall_cb;
341

    
342
static enum {
343
    GDB_SYS_UNKNOWN,
344
    GDB_SYS_ENABLED,
345
    GDB_SYS_DISABLED,
346
} gdb_syscall_mode;
347

    
348
/* If gdb is connected when the first semihosting syscall occurs then use
349
   remote gdb syscalls.  Otherwise use native file IO.  */
350
int use_gdb_syscalls(void)
351
{
352
    if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
353
        gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
354
                                            : GDB_SYS_DISABLED);
355
    }
356
    return gdb_syscall_mode == GDB_SYS_ENABLED;
357
}
358

    
359
/* Resume execution.  */
360
static inline void gdb_continue(GDBState *s)
361
{
362
#ifdef CONFIG_USER_ONLY
363
    s->running_state = 1;
364
#else
365
    vm_start();
366
#endif
367
}
368

    
369
static void put_buffer(GDBState *s, const uint8_t *buf, int len)
370
{
371
#ifdef CONFIG_USER_ONLY
372
    int ret;
373

    
374
    while (len > 0) {
375
        ret = send(s->fd, buf, len, 0);
376
        if (ret < 0) {
377
            if (errno != EINTR && errno != EAGAIN)
378
                return;
379
        } else {
380
            buf += ret;
381
            len -= ret;
382
        }
383
    }
384
#else
385
    qemu_chr_write(s->chr, buf, len);
386
#endif
387
}
388

    
389
static inline int fromhex(int v)
390
{
391
    if (v >= '0' && v <= '9')
392
        return v - '0';
393
    else if (v >= 'A' && v <= 'F')
394
        return v - 'A' + 10;
395
    else if (v >= 'a' && v <= 'f')
396
        return v - 'a' + 10;
397
    else
398
        return 0;
399
}
400

    
401
static inline int tohex(int v)
402
{
403
    if (v < 10)
404
        return v + '0';
405
    else
406
        return v - 10 + 'a';
407
}
408

    
409
static void memtohex(char *buf, const uint8_t *mem, int len)
410
{
411
    int i, c;
412
    char *q;
413
    q = buf;
414
    for(i = 0; i < len; i++) {
415
        c = mem[i];
416
        *q++ = tohex(c >> 4);
417
        *q++ = tohex(c & 0xf);
418
    }
419
    *q = '\0';
420
}
421

    
422
static void hextomem(uint8_t *mem, const char *buf, int len)
423
{
424
    int i;
425

    
426
    for(i = 0; i < len; i++) {
427
        mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
428
        buf += 2;
429
    }
430
}
431

    
432
/* return -1 if error, 0 if OK */
433
static int put_packet_binary(GDBState *s, const char *buf, int len)
434
{
435
    int csum, i;
436
    uint8_t *p;
437

    
438
    for(;;) {
439
        p = s->last_packet;
440
        *(p++) = '$';
441
        memcpy(p, buf, len);
442
        p += len;
443
        csum = 0;
444
        for(i = 0; i < len; i++) {
445
            csum += buf[i];
446
        }
447
        *(p++) = '#';
448
        *(p++) = tohex((csum >> 4) & 0xf);
449
        *(p++) = tohex((csum) & 0xf);
450

    
451
        s->last_packet_len = p - s->last_packet;
452
        put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
453

    
454
#ifdef CONFIG_USER_ONLY
455
        i = get_char(s);
456
        if (i < 0)
457
            return -1;
458
        if (i == '+')
459
            break;
460
#else
461
        break;
462
#endif
463
    }
464
    return 0;
465
}
466

    
467
/* return -1 if error, 0 if OK */
468
static int put_packet(GDBState *s, const char *buf)
469
{
470
#ifdef DEBUG_GDB
471
    printf("reply='%s'\n", buf);
472
#endif
473

    
474
    return put_packet_binary(s, buf, strlen(buf));
475
}
476

    
477
/* The GDB remote protocol transfers values in target byte order.  This means
478
   we can use the raw memory access routines to access the value buffer.
479
   Conveniently, these also handle the case where the buffer is mis-aligned.
480
 */
481
#define GET_REG8(val) do { \
482
    stb_p(mem_buf, val); \
483
    return 1; \
484
    } while(0)
485
#define GET_REG16(val) do { \
486
    stw_p(mem_buf, val); \
487
    return 2; \
488
    } while(0)
489
#define GET_REG32(val) do { \
490
    stl_p(mem_buf, val); \
491
    return 4; \
492
    } while(0)
493
#define GET_REG64(val) do { \
494
    stq_p(mem_buf, val); \
495
    return 8; \
496
    } while(0)
497

    
498
#if TARGET_LONG_BITS == 64
499
#define GET_REGL(val) GET_REG64(val)
500
#define ldtul_p(addr) ldq_p(addr)
501
#else
502
#define GET_REGL(val) GET_REG32(val)
503
#define ldtul_p(addr) ldl_p(addr)
504
#endif
505

    
506
#if defined(TARGET_I386)
507

    
508
#ifdef TARGET_X86_64
509
static const int gpr_map[16] = {
510
    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
511
    8, 9, 10, 11, 12, 13, 14, 15
512
};
513
#else
514
#define gpr_map gpr_map32
515
#endif
516
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
517

    
518
#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
519

    
520
#define IDX_IP_REG      CPU_NB_REGS
521
#define IDX_FLAGS_REG   (IDX_IP_REG + 1)
522
#define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
523
#define IDX_FP_REGS     (IDX_SEG_REGS + 6)
524
#define IDX_XMM_REGS    (IDX_FP_REGS + 16)
525
#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
526

    
527
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
528
{
529
    if (n < CPU_NB_REGS) {
530
        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
531
            GET_REG64(env->regs[gpr_map[n]]);
532
        } else if (n < CPU_NB_REGS32) {
533
            GET_REG32(env->regs[gpr_map32[n]]);
534
        }
535
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
536
#ifdef USE_X86LDOUBLE
537
        /* FIXME: byteswap float values - after fixing fpregs layout. */
538
        memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
539
#else
540
        memset(mem_buf, 0, 10);
541
#endif
542
        return 10;
543
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
544
        n -= IDX_XMM_REGS;
545
        if (n < CPU_NB_REGS32 ||
546
            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
547
            stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
548
            stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
549
            return 16;
550
        }
551
    } else {
552
        switch (n) {
553
        case IDX_IP_REG:
554
            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
555
                GET_REG64(env->eip);
556
            } else {
557
                GET_REG32(env->eip);
558
            }
559
        case IDX_FLAGS_REG: GET_REG32(env->eflags);
560

    
561
        case IDX_SEG_REGS:     GET_REG32(env->segs[R_CS].selector);
562
        case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
563
        case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
564
        case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
565
        case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
566
        case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
567

    
568
        case IDX_FP_REGS + 8:  GET_REG32(env->fpuc);
569
        case IDX_FP_REGS + 9:  GET_REG32((env->fpus & ~0x3800) |
570
                                         (env->fpstt & 0x7) << 11);
571
        case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
572
        case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
573
        case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
574
        case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
575
        case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
576
        case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
577

    
578
        case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
579
        }
580
    }
581
    return 0;
582
}
583

    
584
static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
585
{
586
    uint16_t selector = ldl_p(mem_buf);
587

    
588
    if (selector != env->segs[sreg].selector) {
589
#if defined(CONFIG_USER_ONLY)
590
        cpu_x86_load_seg(env, sreg, selector);
591
#else
592
        unsigned int limit, flags;
593
        target_ulong base;
594

    
595
        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
596
            base = selector << 4;
597
            limit = 0xffff;
598
            flags = 0;
599
        } else {
600
            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
601
                return 4;
602
        }
603
        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
604
#endif
605
    }
606
    return 4;
607
}
608

    
609
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
610
{
611
    uint32_t tmp;
612

    
613
    if (n < CPU_NB_REGS) {
614
        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
615
            env->regs[gpr_map[n]] = ldtul_p(mem_buf);
616
            return sizeof(target_ulong);
617
        } else if (n < CPU_NB_REGS32) {
618
            n = gpr_map32[n];
619
            env->regs[n] &= ~0xffffffffUL;
620
            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
621
            return 4;
622
        }
623
    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
624
#ifdef USE_X86LDOUBLE
625
        /* FIXME: byteswap float values - after fixing fpregs layout. */
626
        memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
627
#endif
628
        return 10;
629
    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
630
        n -= IDX_XMM_REGS;
631
        if (n < CPU_NB_REGS32 ||
632
            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
633
            env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
634
            env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
635
            return 16;
636
        }
637
    } else {
638
        switch (n) {
639
        case IDX_IP_REG:
640
            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
641
                env->eip = ldq_p(mem_buf);
642
                return 8;
643
            } else {
644
                env->eip &= ~0xffffffffUL;
645
                env->eip |= (uint32_t)ldl_p(mem_buf);
646
                return 4;
647
            }
648
        case IDX_FLAGS_REG:
649
            env->eflags = ldl_p(mem_buf);
650
            return 4;
651

    
652
        case IDX_SEG_REGS:     return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
653
        case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
654
        case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
655
        case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
656
        case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
657
        case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
658

    
659
        case IDX_FP_REGS + 8:
660
            env->fpuc = ldl_p(mem_buf);
661
            return 4;
662
        case IDX_FP_REGS + 9:
663
            tmp = ldl_p(mem_buf);
664
            env->fpstt = (tmp >> 11) & 7;
665
            env->fpus = tmp & ~0x3800;
666
            return 4;
667
        case IDX_FP_REGS + 10: /* ftag */  return 4;
668
        case IDX_FP_REGS + 11: /* fiseg */ return 4;
669
        case IDX_FP_REGS + 12: /* fioff */ return 4;
670
        case IDX_FP_REGS + 13: /* foseg */ return 4;
671
        case IDX_FP_REGS + 14: /* fooff */ return 4;
672
        case IDX_FP_REGS + 15: /* fop */   return 4;
673

    
674
        case IDX_MXCSR_REG:
675
            env->mxcsr = ldl_p(mem_buf);
676
            return 4;
677
        }
678
    }
679
    /* Unrecognised register.  */
680
    return 0;
681
}
682

    
683
#elif defined (TARGET_PPC)
684

    
685
/* Old gdb always expects FP registers.  Newer (xml-aware) gdb only
686
   expects whatever the target description contains.  Due to a
687
   historical mishap the FP registers appear in between core integer
688
   regs and PC, MSR, CR, and so forth.  We hack round this by giving the
689
   FP regs zero size when talking to a newer gdb.  */
690
#define NUM_CORE_REGS 71
691
#if defined (TARGET_PPC64)
692
#define GDB_CORE_XML "power64-core.xml"
693
#else
694
#define GDB_CORE_XML "power-core.xml"
695
#endif
696

    
697
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
698
{
699
    if (n < 32) {
700
        /* gprs */
701
        GET_REGL(env->gpr[n]);
702
    } else if (n < 64) {
703
        /* fprs */
704
        if (gdb_has_xml)
705
            return 0;
706
        stfq_p(mem_buf, env->fpr[n-32]);
707
        return 8;
708
    } else {
709
        switch (n) {
710
        case 64: GET_REGL(env->nip);
711
        case 65: GET_REGL(env->msr);
712
        case 66:
713
            {
714
                uint32_t cr = 0;
715
                int i;
716
                for (i = 0; i < 8; i++)
717
                    cr |= env->crf[i] << (32 - ((i + 1) * 4));
718
                GET_REG32(cr);
719
            }
720
        case 67: GET_REGL(env->lr);
721
        case 68: GET_REGL(env->ctr);
722
        case 69: GET_REGL(env->xer);
723
        case 70:
724
            {
725
                if (gdb_has_xml)
726
                    return 0;
727
                GET_REG32(0); /* fpscr */
728
            }
729
        }
730
    }
731
    return 0;
732
}
733

    
734
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
735
{
736
    if (n < 32) {
737
        /* gprs */
738
        env->gpr[n] = ldtul_p(mem_buf);
739
        return sizeof(target_ulong);
740
    } else if (n < 64) {
741
        /* fprs */
742
        if (gdb_has_xml)
743
            return 0;
744
        env->fpr[n-32] = ldfq_p(mem_buf);
745
        return 8;
746
    } else {
747
        switch (n) {
748
        case 64:
749
            env->nip = ldtul_p(mem_buf);
750
            return sizeof(target_ulong);
751
        case 65:
752
            ppc_store_msr(env, ldtul_p(mem_buf));
753
            return sizeof(target_ulong);
754
        case 66:
755
            {
756
                uint32_t cr = ldl_p(mem_buf);
757
                int i;
758
                for (i = 0; i < 8; i++)
759
                    env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
760
                return 4;
761
            }
762
        case 67:
763
            env->lr = ldtul_p(mem_buf);
764
            return sizeof(target_ulong);
765
        case 68:
766
            env->ctr = ldtul_p(mem_buf);
767
            return sizeof(target_ulong);
768
        case 69:
769
            env->xer = ldtul_p(mem_buf);
770
            return sizeof(target_ulong);
771
        case 70:
772
            /* fpscr */
773
            if (gdb_has_xml)
774
                return 0;
775
            return 4;
776
        }
777
    }
778
    return 0;
779
}
780

    
781
#elif defined (TARGET_SPARC)
782

    
783
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
784
#define NUM_CORE_REGS 86
785
#else
786
#define NUM_CORE_REGS 72
787
#endif
788

    
789
#ifdef TARGET_ABI32
790
#define GET_REGA(val) GET_REG32(val)
791
#else
792
#define GET_REGA(val) GET_REGL(val)
793
#endif
794

    
795
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
796
{
797
    if (n < 8) {
798
        /* g0..g7 */
799
        GET_REGA(env->gregs[n]);
800
    }
801
    if (n < 32) {
802
        /* register window */
803
        GET_REGA(env->regwptr[n - 8]);
804
    }
805
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
806
    if (n < 64) {
807
        /* fprs */
808
        GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
809
    }
810
    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
811
    switch (n) {
812
    case 64: GET_REGA(env->y);
813
    case 65: GET_REGA(cpu_get_psr(env));
814
    case 66: GET_REGA(env->wim);
815
    case 67: GET_REGA(env->tbr);
816
    case 68: GET_REGA(env->pc);
817
    case 69: GET_REGA(env->npc);
818
    case 70: GET_REGA(env->fsr);
819
    case 71: GET_REGA(0); /* csr */
820
    default: GET_REGA(0);
821
    }
822
#else
823
    if (n < 64) {
824
        /* f0-f31 */
825
        GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
826
    }
827
    if (n < 80) {
828
        /* f32-f62 (double width, even numbers only) */
829
        uint64_t val;
830

    
831
        val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
832
        val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
833
        GET_REG64(val);
834
    }
835
    switch (n) {
836
    case 80: GET_REGL(env->pc);
837
    case 81: GET_REGL(env->npc);
838
    case 82: GET_REGL((cpu_get_ccr(env) << 32) |
839
                      ((env->asi & 0xff) << 24) |
840
                      ((env->pstate & 0xfff) << 8) |
841
                      cpu_get_cwp64(env));
842
    case 83: GET_REGL(env->fsr);
843
    case 84: GET_REGL(env->fprs);
844
    case 85: GET_REGL(env->y);
845
    }
846
#endif
847
    return 0;
848
}
849

    
850
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
851
{
852
#if defined(TARGET_ABI32)
853
    abi_ulong tmp;
854

    
855
    tmp = ldl_p(mem_buf);
856
#else
857
    target_ulong tmp;
858

    
859
    tmp = ldtul_p(mem_buf);
860
#endif
861

    
862
    if (n < 8) {
863
        /* g0..g7 */
864
        env->gregs[n] = tmp;
865
    } else if (n < 32) {
866
        /* register window */
867
        env->regwptr[n - 8] = tmp;
868
    }
869
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
870
    else if (n < 64) {
871
        /* fprs */
872
        *((uint32_t *)&env->fpr[n - 32]) = tmp;
873
    } else {
874
        /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
875
        switch (n) {
876
        case 64: env->y = tmp; break;
877
        case 65: cpu_put_psr(env, tmp); break;
878
        case 66: env->wim = tmp; break;
879
        case 67: env->tbr = tmp; break;
880
        case 68: env->pc = tmp; break;
881
        case 69: env->npc = tmp; break;
882
        case 70: env->fsr = tmp; break;
883
        default: return 0;
884
        }
885
    }
886
    return 4;
887
#else
888
    else if (n < 64) {
889
        /* f0-f31 */
890
        env->fpr[n] = ldfl_p(mem_buf);
891
        return 4;
892
    } else if (n < 80) {
893
        /* f32-f62 (double width, even numbers only) */
894
        *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
895
        *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
896
    } else {
897
        switch (n) {
898
        case 80: env->pc = tmp; break;
899
        case 81: env->npc = tmp; break;
900
        case 82:
901
            cpu_put_ccr(env, tmp >> 32);
902
            env->asi = (tmp >> 24) & 0xff;
903
            env->pstate = (tmp >> 8) & 0xfff;
904
            cpu_put_cwp64(env, tmp & 0xff);
905
            break;
906
        case 83: env->fsr = tmp; break;
907
        case 84: env->fprs = tmp; break;
908
        case 85: env->y = tmp; break;
909
        default: return 0;
910
        }
911
    }
912
    return 8;
913
#endif
914
}
915
#elif defined (TARGET_ARM)
916

    
917
/* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
918
   whatever the target description contains.  Due to a historical mishap
919
   the FPA registers appear in between core integer regs and the CPSR.
920
   We hack round this by giving the FPA regs zero size when talking to a
921
   newer gdb.  */
922
#define NUM_CORE_REGS 26
923
#define GDB_CORE_XML "arm-core.xml"
924

    
925
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
926
{
927
    if (n < 16) {
928
        /* Core integer register.  */
929
        GET_REG32(env->regs[n]);
930
    }
931
    if (n < 24) {
932
        /* FPA registers.  */
933
        if (gdb_has_xml)
934
            return 0;
935
        memset(mem_buf, 0, 12);
936
        return 12;
937
    }
938
    switch (n) {
939
    case 24:
940
        /* FPA status register.  */
941
        if (gdb_has_xml)
942
            return 0;
943
        GET_REG32(0);
944
    case 25:
945
        /* CPSR */
946
        GET_REG32(cpsr_read(env));
947
    }
948
    /* Unknown register.  */
949
    return 0;
950
}
951

    
952
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
953
{
954
    uint32_t tmp;
955

    
956
    tmp = ldl_p(mem_buf);
957

    
958
    /* Mask out low bit of PC to workaround gdb bugs.  This will probably
959
       cause problems if we ever implement the Jazelle DBX extensions.  */
960
    if (n == 15)
961
        tmp &= ~1;
962

    
963
    if (n < 16) {
964
        /* Core integer register.  */
965
        env->regs[n] = tmp;
966
        return 4;
967
    }
968
    if (n < 24) { /* 16-23 */
969
        /* FPA registers (ignored).  */
970
        if (gdb_has_xml)
971
            return 0;
972
        return 12;
973
    }
974
    switch (n) {
975
    case 24:
976
        /* FPA status register (ignored).  */
977
        if (gdb_has_xml)
978
            return 0;
979
        return 4;
980
    case 25:
981
        /* CPSR */
982
        cpsr_write (env, tmp, 0xffffffff);
983
        return 4;
984
    }
985
    /* Unknown register.  */
986
    return 0;
987
}
988

    
989
#elif defined (TARGET_M68K)
990

    
991
#define NUM_CORE_REGS 18
992

    
993
#define GDB_CORE_XML "cf-core.xml"
994

    
995
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
996
{
997
    if (n < 8) {
998
        /* D0-D7 */
999
        GET_REG32(env->dregs[n]);
1000
    } else if (n < 16) {
1001
        /* A0-A7 */
1002
        GET_REG32(env->aregs[n - 8]);
1003
    } else {
1004
        switch (n) {
1005
        case 16: GET_REG32(env->sr);
1006
        case 17: GET_REG32(env->pc);
1007
        }
1008
    }
1009
    /* FP registers not included here because they vary between
1010
       ColdFire and m68k.  Use XML bits for these.  */
1011
    return 0;
1012
}
1013

    
1014
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1015
{
1016
    uint32_t tmp;
1017

    
1018
    tmp = ldl_p(mem_buf);
1019

    
1020
    if (n < 8) {
1021
        /* D0-D7 */
1022
        env->dregs[n] = tmp;
1023
    } else if (n < 16) {
1024
        /* A0-A7 */
1025
        env->aregs[n - 8] = tmp;
1026
    } else {
1027
        switch (n) {
1028
        case 16: env->sr = tmp; break;
1029
        case 17: env->pc = tmp; break;
1030
        default: return 0;
1031
        }
1032
    }
1033
    return 4;
1034
}
1035
#elif defined (TARGET_MIPS)
1036

    
1037
#define NUM_CORE_REGS 73
1038

    
1039
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1040
{
1041
    if (n < 32) {
1042
        GET_REGL(env->active_tc.gpr[n]);
1043
    }
1044
    if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1045
        if (n >= 38 && n < 70) {
1046
            if (env->CP0_Status & (1 << CP0St_FR))
1047
                GET_REGL(env->active_fpu.fpr[n - 38].d);
1048
            else
1049
                GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1050
        }
1051
        switch (n) {
1052
        case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1053
        case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1054
        }
1055
    }
1056
    switch (n) {
1057
    case 32: GET_REGL((int32_t)env->CP0_Status);
1058
    case 33: GET_REGL(env->active_tc.LO[0]);
1059
    case 34: GET_REGL(env->active_tc.HI[0]);
1060
    case 35: GET_REGL(env->CP0_BadVAddr);
1061
    case 36: GET_REGL((int32_t)env->CP0_Cause);
1062
    case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1063
    case 72: GET_REGL(0); /* fp */
1064
    case 89: GET_REGL((int32_t)env->CP0_PRid);
1065
    }
1066
    if (n >= 73 && n <= 88) {
1067
        /* 16 embedded regs.  */
1068
        GET_REGL(0);
1069
    }
1070

    
1071
    return 0;
1072
}
1073

    
1074
/* convert MIPS rounding mode in FCR31 to IEEE library */
1075
static unsigned int ieee_rm[] =
1076
  {
1077
    float_round_nearest_even,
1078
    float_round_to_zero,
1079
    float_round_up,
1080
    float_round_down
1081
  };
1082
#define RESTORE_ROUNDING_MODE \
1083
    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1084

    
1085
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1086
{
1087
    target_ulong tmp;
1088

    
1089
    tmp = ldtul_p(mem_buf);
1090

    
1091
    if (n < 32) {
1092
        env->active_tc.gpr[n] = tmp;
1093
        return sizeof(target_ulong);
1094
    }
1095
    if (env->CP0_Config1 & (1 << CP0C1_FP)
1096
            && n >= 38 && n < 73) {
1097
        if (n < 70) {
1098
            if (env->CP0_Status & (1 << CP0St_FR))
1099
              env->active_fpu.fpr[n - 38].d = tmp;
1100
            else
1101
              env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1102
        }
1103
        switch (n) {
1104
        case 70:
1105
            env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1106
            /* set rounding mode */
1107
            RESTORE_ROUNDING_MODE;
1108
#ifndef CONFIG_SOFTFLOAT
1109
            /* no floating point exception for native float */
1110
            SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1111
#endif
1112
            break;
1113
        case 71: env->active_fpu.fcr0 = tmp; break;
1114
        }
1115
        return sizeof(target_ulong);
1116
    }
1117
    switch (n) {
1118
    case 32: env->CP0_Status = tmp; break;
1119
    case 33: env->active_tc.LO[0] = tmp; break;
1120
    case 34: env->active_tc.HI[0] = tmp; break;
1121
    case 35: env->CP0_BadVAddr = tmp; break;
1122
    case 36: env->CP0_Cause = tmp; break;
1123
    case 37:
1124
        env->active_tc.PC = tmp & ~(target_ulong)1;
1125
        if (tmp & 1) {
1126
            env->hflags |= MIPS_HFLAG_M16;
1127
        } else {
1128
            env->hflags &= ~(MIPS_HFLAG_M16);
1129
        }
1130
        break;
1131
    case 72: /* fp, ignored */ break;
1132
    default: 
1133
        if (n > 89)
1134
            return 0;
1135
        /* Other registers are readonly.  Ignore writes.  */
1136
        break;
1137
    }
1138

    
1139
    return sizeof(target_ulong);
1140
}
1141
#elif defined (TARGET_SH4)
1142

    
1143
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1144
/* FIXME: We should use XML for this.  */
1145

    
1146
#define NUM_CORE_REGS 59
1147

    
1148
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1149
{
1150
    if (n < 8) {
1151
        if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1152
            GET_REGL(env->gregs[n + 16]);
1153
        } else {
1154
            GET_REGL(env->gregs[n]);
1155
        }
1156
    } else if (n < 16) {
1157
        GET_REGL(env->gregs[n]);
1158
    } else if (n >= 25 && n < 41) {
1159
        GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1160
    } else if (n >= 43 && n < 51) {
1161
        GET_REGL(env->gregs[n - 43]);
1162
    } else if (n >= 51 && n < 59) {
1163
        GET_REGL(env->gregs[n - (51 - 16)]);
1164
    }
1165
    switch (n) {
1166
    case 16: GET_REGL(env->pc);
1167
    case 17: GET_REGL(env->pr);
1168
    case 18: GET_REGL(env->gbr);
1169
    case 19: GET_REGL(env->vbr);
1170
    case 20: GET_REGL(env->mach);
1171
    case 21: GET_REGL(env->macl);
1172
    case 22: GET_REGL(env->sr);
1173
    case 23: GET_REGL(env->fpul);
1174
    case 24: GET_REGL(env->fpscr);
1175
    case 41: GET_REGL(env->ssr);
1176
    case 42: GET_REGL(env->spc);
1177
    }
1178

    
1179
    return 0;
1180
}
1181

    
1182
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1183
{
1184
    uint32_t tmp;
1185

    
1186
    tmp = ldl_p(mem_buf);
1187

    
1188
    if (n < 8) {
1189
        if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1190
            env->gregs[n + 16] = tmp;
1191
        } else {
1192
            env->gregs[n] = tmp;
1193
        }
1194
        return 4;
1195
    } else if (n < 16) {
1196
        env->gregs[n] = tmp;
1197
        return 4;
1198
    } else if (n >= 25 && n < 41) {
1199
        env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1200
        return 4;
1201
    } else if (n >= 43 && n < 51) {
1202
        env->gregs[n - 43] = tmp;
1203
        return 4;
1204
    } else if (n >= 51 && n < 59) {
1205
        env->gregs[n - (51 - 16)] = tmp;
1206
        return 4;
1207
    }
1208
    switch (n) {
1209
    case 16: env->pc = tmp; break;
1210
    case 17: env->pr = tmp; break;
1211
    case 18: env->gbr = tmp; break;
1212
    case 19: env->vbr = tmp; break;
1213
    case 20: env->mach = tmp; break;
1214
    case 21: env->macl = tmp; break;
1215
    case 22: env->sr = tmp; break;
1216
    case 23: env->fpul = tmp; break;
1217
    case 24: env->fpscr = tmp; break;
1218
    case 41: env->ssr = tmp; break;
1219
    case 42: env->spc = tmp; break;
1220
    default: return 0;
1221
    }
1222

    
1223
    return 4;
1224
}
1225
#elif defined (TARGET_MICROBLAZE)
1226

    
1227
#define NUM_CORE_REGS (32 + 5)
1228

    
1229
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1230
{
1231
    if (n < 32) {
1232
        GET_REG32(env->regs[n]);
1233
    } else {
1234
        GET_REG32(env->sregs[n - 32]);
1235
    }
1236
    return 0;
1237
}
1238

    
1239
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1240
{
1241
    uint32_t tmp;
1242

    
1243
    if (n > NUM_CORE_REGS)
1244
        return 0;
1245

    
1246
    tmp = ldl_p(mem_buf);
1247

    
1248
    if (n < 32) {
1249
        env->regs[n] = tmp;
1250
    } else {
1251
        env->sregs[n - 32] = tmp;
1252
    }
1253
    return 4;
1254
}
1255
#elif defined (TARGET_CRIS)
1256

    
1257
#define NUM_CORE_REGS 49
1258

    
1259
static int
1260
read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
1261
{
1262
    if (n < 15) {
1263
        GET_REG32(env->regs[n]);
1264
    }
1265

    
1266
    if (n == 15) {
1267
        GET_REG32(env->pc);
1268
    }
1269

    
1270
    if (n < 32) {
1271
        switch (n) {
1272
        case 16:
1273
            GET_REG8(env->pregs[n - 16]);
1274
            break;
1275
        case 17:
1276
            GET_REG8(env->pregs[n - 16]);
1277
            break;
1278
        case 20:
1279
        case 21:
1280
            GET_REG16(env->pregs[n - 16]);
1281
            break;
1282
        default:
1283
            if (n >= 23) {
1284
                GET_REG32(env->pregs[n - 16]);
1285
            }
1286
            break;
1287
        }
1288
    }
1289
    return 0;
1290
}
1291

    
1292
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1293
{
1294
    uint8_t srs;
1295

    
1296
    if (env->pregs[PR_VR] < 32)
1297
        return read_register_crisv10(env, mem_buf, n);
1298

    
1299
    srs = env->pregs[PR_SRS];
1300
    if (n < 16) {
1301
        GET_REG32(env->regs[n]);
1302
    }
1303

    
1304
    if (n >= 21 && n < 32) {
1305
        GET_REG32(env->pregs[n - 16]);
1306
    }
1307
    if (n >= 33 && n < 49) {
1308
        GET_REG32(env->sregs[srs][n - 33]);
1309
    }
1310
    switch (n) {
1311
    case 16: GET_REG8(env->pregs[0]);
1312
    case 17: GET_REG8(env->pregs[1]);
1313
    case 18: GET_REG32(env->pregs[2]);
1314
    case 19: GET_REG8(srs);
1315
    case 20: GET_REG16(env->pregs[4]);
1316
    case 32: GET_REG32(env->pc);
1317
    }
1318

    
1319
    return 0;
1320
}
1321

    
1322
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1323
{
1324
    uint32_t tmp;
1325

    
1326
    if (n > 49)
1327
        return 0;
1328

    
1329
    tmp = ldl_p(mem_buf);
1330

    
1331
    if (n < 16) {
1332
        env->regs[n] = tmp;
1333
    }
1334

    
1335
    if (n >= 21 && n < 32) {
1336
        env->pregs[n - 16] = tmp;
1337
    }
1338

    
1339
    /* FIXME: Should support function regs be writable?  */
1340
    switch (n) {
1341
    case 16: return 1;
1342
    case 17: return 1;
1343
    case 18: env->pregs[PR_PID] = tmp; break;
1344
    case 19: return 1;
1345
    case 20: return 2;
1346
    case 32: env->pc = tmp; break;
1347
    }
1348

    
1349
    return 4;
1350
}
1351
#elif defined (TARGET_ALPHA)
1352

    
1353
#define NUM_CORE_REGS 67
1354

    
1355
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1356
{
1357
    uint64_t val;
1358
    CPU_DoubleU d;
1359

    
1360
    switch (n) {
1361
    case 0 ... 30:
1362
        val = env->ir[n];
1363
        break;
1364
    case 32 ... 62:
1365
        d.d = env->fir[n - 32];
1366
        val = d.ll;
1367
        break;
1368
    case 63:
1369
        val = cpu_alpha_load_fpcr(env);
1370
        break;
1371
    case 64:
1372
        val = env->pc;
1373
        break;
1374
    case 66:
1375
        val = env->unique;
1376
        break;
1377
    case 31:
1378
    case 65:
1379
        /* 31 really is the zero register; 65 is unassigned in the
1380
           gdb protocol, but is still required to occupy 8 bytes. */
1381
        val = 0;
1382
        break;
1383
    default:
1384
        return 0;
1385
    }
1386
    GET_REGL(val);
1387
}
1388

    
1389
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1390
{
1391
    target_ulong tmp = ldtul_p(mem_buf);
1392
    CPU_DoubleU d;
1393

    
1394
    switch (n) {
1395
    case 0 ... 30:
1396
        env->ir[n] = tmp;
1397
        break;
1398
    case 32 ... 62:
1399
        d.ll = tmp;
1400
        env->fir[n - 32] = d.d;
1401
        break;
1402
    case 63:
1403
        cpu_alpha_store_fpcr(env, tmp);
1404
        break;
1405
    case 64:
1406
        env->pc = tmp;
1407
        break;
1408
    case 66:
1409
        env->unique = tmp;
1410
        break;
1411
    case 31:
1412
    case 65:
1413
        /* 31 really is the zero register; 65 is unassigned in the
1414
           gdb protocol, but is still required to occupy 8 bytes. */
1415
        break;
1416
    default:
1417
        return 0;
1418
    }
1419
    return 8;
1420
}
1421
#elif defined (TARGET_S390X)
1422

    
1423
#define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1424

    
1425
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1426
{
1427
    switch (n) {
1428
        case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1429
        case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1430
        case S390_R0_REGNUM ... S390_R15_REGNUM:
1431
            GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1432
        case S390_A0_REGNUM ... S390_A15_REGNUM:
1433
            GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1434
        case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1435
        case S390_F0_REGNUM ... S390_F15_REGNUM:
1436
            /* XXX */
1437
            break;
1438
        case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1439
        case S390_CC_REGNUM:
1440
            env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
1441
                                 env->cc_vr);
1442
            GET_REG32(env->cc_op);
1443
            break;
1444
    }
1445

    
1446
    return 0;
1447
}
1448

    
1449
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1450
{
1451
    target_ulong tmpl;
1452
    uint32_t tmp32;
1453
    int r = 8;
1454
    tmpl = ldtul_p(mem_buf);
1455
    tmp32 = ldl_p(mem_buf);
1456

    
1457
    switch (n) {
1458
        case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1459
        case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1460
        case S390_R0_REGNUM ... S390_R15_REGNUM:
1461
            env->regs[n-S390_R0_REGNUM] = tmpl; break;
1462
        case S390_A0_REGNUM ... S390_A15_REGNUM:
1463
            env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1464
        case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1465
        case S390_F0_REGNUM ... S390_F15_REGNUM:
1466
            /* XXX */
1467
            break;
1468
        case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1469
        case S390_CC_REGNUM: env->cc_op = tmp32; r=4; break;
1470
    }
1471

    
1472
    return r;
1473
}
1474
#elif defined (TARGET_LM32)
1475

    
1476
#include "hw/lm32_pic.h"
1477
#define NUM_CORE_REGS (32 + 7)
1478

    
1479
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1480
{
1481
    if (n < 32) {
1482
        GET_REG32(env->regs[n]);
1483
    } else {
1484
        switch (n) {
1485
        case 32:
1486
            GET_REG32(env->pc);
1487
            break;
1488
        /* FIXME: put in right exception ID */
1489
        case 33:
1490
            GET_REG32(0);
1491
            break;
1492
        case 34:
1493
            GET_REG32(env->eba);
1494
            break;
1495
        case 35:
1496
            GET_REG32(env->deba);
1497
            break;
1498
        case 36:
1499
            GET_REG32(env->ie);
1500
            break;
1501
        case 37:
1502
            GET_REG32(lm32_pic_get_im(env->pic_state));
1503
            break;
1504
        case 38:
1505
            GET_REG32(lm32_pic_get_ip(env->pic_state));
1506
            break;
1507
        }
1508
    }
1509
    return 0;
1510
}
1511

    
1512
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1513
{
1514
    uint32_t tmp;
1515

    
1516
    if (n > NUM_CORE_REGS) {
1517
        return 0;
1518
    }
1519

    
1520
    tmp = ldl_p(mem_buf);
1521

    
1522
    if (n < 32) {
1523
        env->regs[n] = tmp;
1524
    } else {
1525
        switch (n) {
1526
        case 32:
1527
            env->pc = tmp;
1528
            break;
1529
        case 34:
1530
            env->eba = tmp;
1531
            break;
1532
        case 35:
1533
            env->deba = tmp;
1534
            break;
1535
        case 36:
1536
            env->ie = tmp;
1537
            break;
1538
        case 37:
1539
            lm32_pic_set_im(env->pic_state, tmp);
1540
            break;
1541
        case 38:
1542
            lm32_pic_set_ip(env->pic_state, tmp);
1543
            break;
1544
        }
1545
    }
1546
    return 4;
1547
}
1548
#else
1549

    
1550
#define NUM_CORE_REGS 0
1551

    
1552
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1553
{
1554
    return 0;
1555
}
1556

    
1557
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1558
{
1559
    return 0;
1560
}
1561

    
1562
#endif
1563

    
1564
static int num_g_regs = NUM_CORE_REGS;
1565

    
1566
#ifdef GDB_CORE_XML
1567
/* Encode data using the encoding for 'x' packets.  */
1568
static int memtox(char *buf, const char *mem, int len)
1569
{
1570
    char *p = buf;
1571
    char c;
1572

    
1573
    while (len--) {
1574
        c = *(mem++);
1575
        switch (c) {
1576
        case '#': case '$': case '*': case '}':
1577
            *(p++) = '}';
1578
            *(p++) = c ^ 0x20;
1579
            break;
1580
        default:
1581
            *(p++) = c;
1582
            break;
1583
        }
1584
    }
1585
    return p - buf;
1586
}
1587

    
1588
static const char *get_feature_xml(const char *p, const char **newp)
1589
{
1590
    size_t len;
1591
    int i;
1592
    const char *name;
1593
    static char target_xml[1024];
1594

    
1595
    len = 0;
1596
    while (p[len] && p[len] != ':')
1597
        len++;
1598
    *newp = p + len;
1599

    
1600
    name = NULL;
1601
    if (strncmp(p, "target.xml", len) == 0) {
1602
        /* Generate the XML description for this CPU.  */
1603
        if (!target_xml[0]) {
1604
            GDBRegisterState *r;
1605

    
1606
            snprintf(target_xml, sizeof(target_xml),
1607
                     "<?xml version=\"1.0\"?>"
1608
                     "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1609
                     "<target>"
1610
                     "<xi:include href=\"%s\"/>",
1611
                     GDB_CORE_XML);
1612

    
1613
            for (r = first_cpu->gdb_regs; r; r = r->next) {
1614
                pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1615
                pstrcat(target_xml, sizeof(target_xml), r->xml);
1616
                pstrcat(target_xml, sizeof(target_xml), "\"/>");
1617
            }
1618
            pstrcat(target_xml, sizeof(target_xml), "</target>");
1619
        }
1620
        return target_xml;
1621
    }
1622
    for (i = 0; ; i++) {
1623
        name = xml_builtin[i][0];
1624
        if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1625
            break;
1626
    }
1627
    return name ? xml_builtin[i][1] : NULL;
1628
}
1629
#endif
1630

    
1631
static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1632
{
1633
    GDBRegisterState *r;
1634

    
1635
    if (reg < NUM_CORE_REGS)
1636
        return cpu_gdb_read_register(env, mem_buf, reg);
1637

    
1638
    for (r = env->gdb_regs; r; r = r->next) {
1639
        if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1640
            return r->get_reg(env, mem_buf, reg - r->base_reg);
1641
        }
1642
    }
1643
    return 0;
1644
}
1645

    
1646
static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1647
{
1648
    GDBRegisterState *r;
1649

    
1650
    if (reg < NUM_CORE_REGS)
1651
        return cpu_gdb_write_register(env, mem_buf, reg);
1652

    
1653
    for (r = env->gdb_regs; r; r = r->next) {
1654
        if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1655
            return r->set_reg(env, mem_buf, reg - r->base_reg);
1656
        }
1657
    }
1658
    return 0;
1659
}
1660

    
1661
/* Register a supplemental set of CPU registers.  If g_pos is nonzero it
1662
   specifies the first register number and these registers are included in
1663
   a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
1664
   gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1665
 */
1666

    
1667
void gdb_register_coprocessor(CPUState * env,
1668
                             gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1669
                             int num_regs, const char *xml, int g_pos)
1670
{
1671
    GDBRegisterState *s;
1672
    GDBRegisterState **p;
1673
    static int last_reg = NUM_CORE_REGS;
1674

    
1675
    s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1676
    s->base_reg = last_reg;
1677
    s->num_regs = num_regs;
1678
    s->get_reg = get_reg;
1679
    s->set_reg = set_reg;
1680
    s->xml = xml;
1681
    p = &env->gdb_regs;
1682
    while (*p) {
1683
        /* Check for duplicates.  */
1684
        if (strcmp((*p)->xml, xml) == 0)
1685
            return;
1686
        p = &(*p)->next;
1687
    }
1688
    /* Add to end of list.  */
1689
    last_reg += num_regs;
1690
    *p = s;
1691
    if (g_pos) {
1692
        if (g_pos != s->base_reg) {
1693
            fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1694
                    "Expected %d got %d\n", xml, g_pos, s->base_reg);
1695
        } else {
1696
            num_g_regs = last_reg;
1697
        }
1698
    }
1699
}
1700

    
1701
#ifndef CONFIG_USER_ONLY
1702
static const int xlat_gdb_type[] = {
1703
    [GDB_WATCHPOINT_WRITE]  = BP_GDB | BP_MEM_WRITE,
1704
    [GDB_WATCHPOINT_READ]   = BP_GDB | BP_MEM_READ,
1705
    [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1706
};
1707
#endif
1708

    
1709
static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1710
{
1711
    CPUState *env;
1712
    int err = 0;
1713

    
1714
    if (kvm_enabled())
1715
        return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1716

    
1717
    switch (type) {
1718
    case GDB_BREAKPOINT_SW:
1719
    case GDB_BREAKPOINT_HW:
1720
        for (env = first_cpu; env != NULL; env = env->next_cpu) {
1721
            err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1722
            if (err)
1723
                break;
1724
        }
1725
        return err;
1726
#ifndef CONFIG_USER_ONLY
1727
    case GDB_WATCHPOINT_WRITE:
1728
    case GDB_WATCHPOINT_READ:
1729
    case GDB_WATCHPOINT_ACCESS:
1730
        for (env = first_cpu; env != NULL; env = env->next_cpu) {
1731
            err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1732
                                        NULL);
1733
            if (err)
1734
                break;
1735
        }
1736
        return err;
1737
#endif
1738
    default:
1739
        return -ENOSYS;
1740
    }
1741
}
1742

    
1743
static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1744
{
1745
    CPUState *env;
1746
    int err = 0;
1747

    
1748
    if (kvm_enabled())
1749
        return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1750

    
1751
    switch (type) {
1752
    case GDB_BREAKPOINT_SW:
1753
    case GDB_BREAKPOINT_HW:
1754
        for (env = first_cpu; env != NULL; env = env->next_cpu) {
1755
            err = cpu_breakpoint_remove(env, addr, BP_GDB);
1756
            if (err)
1757
                break;
1758
        }
1759
        return err;
1760
#ifndef CONFIG_USER_ONLY
1761
    case GDB_WATCHPOINT_WRITE:
1762
    case GDB_WATCHPOINT_READ:
1763
    case GDB_WATCHPOINT_ACCESS:
1764
        for (env = first_cpu; env != NULL; env = env->next_cpu) {
1765
            err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1766
            if (err)
1767
                break;
1768
        }
1769
        return err;
1770
#endif
1771
    default:
1772
        return -ENOSYS;
1773
    }
1774
}
1775

    
1776
static void gdb_breakpoint_remove_all(void)
1777
{
1778
    CPUState *env;
1779

    
1780
    if (kvm_enabled()) {
1781
        kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1782
        return;
1783
    }
1784

    
1785
    for (env = first_cpu; env != NULL; env = env->next_cpu) {
1786
        cpu_breakpoint_remove_all(env, BP_GDB);
1787
#ifndef CONFIG_USER_ONLY
1788
        cpu_watchpoint_remove_all(env, BP_GDB);
1789
#endif
1790
    }
1791
}
1792

    
1793
static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1794
{
1795
#if defined(TARGET_I386)
1796
    cpu_synchronize_state(s->c_cpu);
1797
    s->c_cpu->eip = pc;
1798
#elif defined (TARGET_PPC)
1799
    s->c_cpu->nip = pc;
1800
#elif defined (TARGET_SPARC)
1801
    s->c_cpu->pc = pc;
1802
    s->c_cpu->npc = pc + 4;
1803
#elif defined (TARGET_ARM)
1804
    s->c_cpu->regs[15] = pc;
1805
#elif defined (TARGET_SH4)
1806
    s->c_cpu->pc = pc;
1807
#elif defined (TARGET_MIPS)
1808
    s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
1809
    if (pc & 1) {
1810
        s->c_cpu->hflags |= MIPS_HFLAG_M16;
1811
    } else {
1812
        s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
1813
    }
1814
#elif defined (TARGET_MICROBLAZE)
1815
    s->c_cpu->sregs[SR_PC] = pc;
1816
#elif defined (TARGET_CRIS)
1817
    s->c_cpu->pc = pc;
1818
#elif defined (TARGET_ALPHA)
1819
    s->c_cpu->pc = pc;
1820
#elif defined (TARGET_S390X)
1821
    cpu_synchronize_state(s->c_cpu);
1822
    s->c_cpu->psw.addr = pc;
1823
#elif defined (TARGET_LM32)
1824
    s->c_cpu->pc = pc;
1825
#endif
1826
}
1827

    
1828
static inline int gdb_id(CPUState *env)
1829
{
1830
#if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1831
    return env->host_tid;
1832
#else
1833
    return env->cpu_index + 1;
1834
#endif
1835
}
1836

    
1837
static CPUState *find_cpu(uint32_t thread_id)
1838
{
1839
    CPUState *env;
1840

    
1841
    for (env = first_cpu; env != NULL; env = env->next_cpu) {
1842
        if (gdb_id(env) == thread_id) {
1843
            return env;
1844
        }
1845
    }
1846

    
1847
    return NULL;
1848
}
1849

    
1850
static int gdb_handle_packet(GDBState *s, const char *line_buf)
1851
{
1852
    CPUState *env;
1853
    const char *p;
1854
    uint32_t thread;
1855
    int ch, reg_size, type, res;
1856
    char buf[MAX_PACKET_LENGTH];
1857
    uint8_t mem_buf[MAX_PACKET_LENGTH];
1858
    uint8_t *registers;
1859
    target_ulong addr, len;
1860

    
1861
#ifdef DEBUG_GDB
1862
    printf("command='%s'\n", line_buf);
1863
#endif
1864
    p = line_buf;
1865
    ch = *p++;
1866
    switch(ch) {
1867
    case '?':
1868
        /* TODO: Make this return the correct value for user-mode.  */
1869
        snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1870
                 gdb_id(s->c_cpu));
1871
        put_packet(s, buf);
1872
        /* Remove all the breakpoints when this query is issued,
1873
         * because gdb is doing and initial connect and the state
1874
         * should be cleaned up.
1875
         */
1876
        gdb_breakpoint_remove_all();
1877
        break;
1878
    case 'c':
1879
        if (*p != '\0') {
1880
            addr = strtoull(p, (char **)&p, 16);
1881
            gdb_set_cpu_pc(s, addr);
1882
        }
1883
        s->signal = 0;
1884
        gdb_continue(s);
1885
        return RS_IDLE;
1886
    case 'C':
1887
        s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1888
        if (s->signal == -1)
1889
            s->signal = 0;
1890
        gdb_continue(s);
1891
        return RS_IDLE;
1892
    case 'v':
1893
        if (strncmp(p, "Cont", 4) == 0) {
1894
            int res_signal, res_thread;
1895

    
1896
            p += 4;
1897
            if (*p == '?') {
1898
                put_packet(s, "vCont;c;C;s;S");
1899
                break;
1900
            }
1901
            res = 0;
1902
            res_signal = 0;
1903
            res_thread = 0;
1904
            while (*p) {
1905
                int action, signal;
1906

    
1907
                if (*p++ != ';') {
1908
                    res = 0;
1909
                    break;
1910
                }
1911
                action = *p++;
1912
                signal = 0;
1913
                if (action == 'C' || action == 'S') {
1914
                    signal = strtoul(p, (char **)&p, 16);
1915
                } else if (action != 'c' && action != 's') {
1916
                    res = 0;
1917
                    break;
1918
                }
1919
                thread = 0;
1920
                if (*p == ':') {
1921
                    thread = strtoull(p+1, (char **)&p, 16);
1922
                }
1923
                action = tolower(action);
1924
                if (res == 0 || (res == 'c' && action == 's')) {
1925
                    res = action;
1926
                    res_signal = signal;
1927
                    res_thread = thread;
1928
                }
1929
            }
1930
            if (res) {
1931
                if (res_thread != -1 && res_thread != 0) {
1932
                    env = find_cpu(res_thread);
1933
                    if (env == NULL) {
1934
                        put_packet(s, "E22");
1935
                        break;
1936
                    }
1937
                    s->c_cpu = env;
1938
                }
1939
                if (res == 's') {
1940
                    cpu_single_step(s->c_cpu, sstep_flags);
1941
                }
1942
                s->signal = res_signal;
1943
                gdb_continue(s);
1944
                return RS_IDLE;
1945
            }
1946
            break;
1947
        } else {
1948
            goto unknown_command;
1949
        }
1950
    case 'k':
1951
        /* Kill the target */
1952
        fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1953
        exit(0);
1954
    case 'D':
1955
        /* Detach packet */
1956
        gdb_breakpoint_remove_all();
1957
        gdb_syscall_mode = GDB_SYS_DISABLED;
1958
        gdb_continue(s);
1959
        put_packet(s, "OK");
1960
        break;
1961
    case 's':
1962
        if (*p != '\0') {
1963
            addr = strtoull(p, (char **)&p, 16);
1964
            gdb_set_cpu_pc(s, addr);
1965
        }
1966
        cpu_single_step(s->c_cpu, sstep_flags);
1967
        gdb_continue(s);
1968
        return RS_IDLE;
1969
    case 'F':
1970
        {
1971
            target_ulong ret;
1972
            target_ulong err;
1973

    
1974
            ret = strtoull(p, (char **)&p, 16);
1975
            if (*p == ',') {
1976
                p++;
1977
                err = strtoull(p, (char **)&p, 16);
1978
            } else {
1979
                err = 0;
1980
            }
1981
            if (*p == ',')
1982
                p++;
1983
            type = *p;
1984
            if (gdb_current_syscall_cb)
1985
                gdb_current_syscall_cb(s->c_cpu, ret, err);
1986
            if (type == 'C') {
1987
                put_packet(s, "T02");
1988
            } else {
1989
                gdb_continue(s);
1990
            }
1991
        }
1992
        break;
1993
    case 'g':
1994
        cpu_synchronize_state(s->g_cpu);
1995
        len = 0;
1996
        for (addr = 0; addr < num_g_regs; addr++) {
1997
            reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1998
            len += reg_size;
1999
        }
2000
        memtohex(buf, mem_buf, len);
2001
        put_packet(s, buf);
2002
        break;
2003
    case 'G':
2004
        cpu_synchronize_state(s->g_cpu);
2005
        registers = mem_buf;
2006
        len = strlen(p) / 2;
2007
        hextomem((uint8_t *)registers, p, len);
2008
        for (addr = 0; addr < num_g_regs && len > 0; addr++) {
2009
            reg_size = gdb_write_register(s->g_cpu, registers, addr);
2010
            len -= reg_size;
2011
            registers += reg_size;
2012
        }
2013
        put_packet(s, "OK");
2014
        break;
2015
    case 'm':
2016
        addr = strtoull(p, (char **)&p, 16);
2017
        if (*p == ',')
2018
            p++;
2019
        len = strtoull(p, NULL, 16);
2020
        if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
2021
            put_packet (s, "E14");
2022
        } else {
2023
            memtohex(buf, mem_buf, len);
2024
            put_packet(s, buf);
2025
        }
2026
        break;
2027
    case 'M':
2028
        addr = strtoull(p, (char **)&p, 16);
2029
        if (*p == ',')
2030
            p++;
2031
        len = strtoull(p, (char **)&p, 16);
2032
        if (*p == ':')
2033
            p++;
2034
        hextomem(mem_buf, p, len);
2035
        if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
2036
            put_packet(s, "E14");
2037
        else
2038
            put_packet(s, "OK");
2039
        break;
2040
    case 'p':
2041
        /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
2042
           This works, but can be very slow.  Anything new enough to
2043
           understand XML also knows how to use this properly.  */
2044
        if (!gdb_has_xml)
2045
            goto unknown_command;
2046
        addr = strtoull(p, (char **)&p, 16);
2047
        reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
2048
        if (reg_size) {
2049
            memtohex(buf, mem_buf, reg_size);
2050
            put_packet(s, buf);
2051
        } else {
2052
            put_packet(s, "E14");
2053
        }
2054
        break;
2055
    case 'P':
2056
        if (!gdb_has_xml)
2057
            goto unknown_command;
2058
        addr = strtoull(p, (char **)&p, 16);
2059
        if (*p == '=')
2060
            p++;
2061
        reg_size = strlen(p) / 2;
2062
        hextomem(mem_buf, p, reg_size);
2063
        gdb_write_register(s->g_cpu, mem_buf, addr);
2064
        put_packet(s, "OK");
2065
        break;
2066
    case 'Z':
2067
    case 'z':
2068
        type = strtoul(p, (char **)&p, 16);
2069
        if (*p == ',')
2070
            p++;
2071
        addr = strtoull(p, (char **)&p, 16);
2072
        if (*p == ',')
2073
            p++;
2074
        len = strtoull(p, (char **)&p, 16);
2075
        if (ch == 'Z')
2076
            res = gdb_breakpoint_insert(addr, len, type);
2077
        else
2078
            res = gdb_breakpoint_remove(addr, len, type);
2079
        if (res >= 0)
2080
             put_packet(s, "OK");
2081
        else if (res == -ENOSYS)
2082
            put_packet(s, "");
2083
        else
2084
            put_packet(s, "E22");
2085
        break;
2086
    case 'H':
2087
        type = *p++;
2088
        thread = strtoull(p, (char **)&p, 16);
2089
        if (thread == -1 || thread == 0) {
2090
            put_packet(s, "OK");
2091
            break;
2092
        }
2093
        env = find_cpu(thread);
2094
        if (env == NULL) {
2095
            put_packet(s, "E22");
2096
            break;
2097
        }
2098
        switch (type) {
2099
        case 'c':
2100
            s->c_cpu = env;
2101
            put_packet(s, "OK");
2102
            break;
2103
        case 'g':
2104
            s->g_cpu = env;
2105
            put_packet(s, "OK");
2106
            break;
2107
        default:
2108
             put_packet(s, "E22");
2109
             break;
2110
        }
2111
        break;
2112
    case 'T':
2113
        thread = strtoull(p, (char **)&p, 16);
2114
        env = find_cpu(thread);
2115

    
2116
        if (env != NULL) {
2117
            put_packet(s, "OK");
2118
        } else {
2119
            put_packet(s, "E22");
2120
        }
2121
        break;
2122
    case 'q':
2123
    case 'Q':
2124
        /* parse any 'q' packets here */
2125
        if (!strcmp(p,"qemu.sstepbits")) {
2126
            /* Query Breakpoint bit definitions */
2127
            snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2128
                     SSTEP_ENABLE,
2129
                     SSTEP_NOIRQ,
2130
                     SSTEP_NOTIMER);
2131
            put_packet(s, buf);
2132
            break;
2133
        } else if (strncmp(p,"qemu.sstep",10) == 0) {
2134
            /* Display or change the sstep_flags */
2135
            p += 10;
2136
            if (*p != '=') {
2137
                /* Display current setting */
2138
                snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
2139
                put_packet(s, buf);
2140
                break;
2141
            }
2142
            p++;
2143
            type = strtoul(p, (char **)&p, 16);
2144
            sstep_flags = type;
2145
            put_packet(s, "OK");
2146
            break;
2147
        } else if (strcmp(p,"C") == 0) {
2148
            /* "Current thread" remains vague in the spec, so always return
2149
             *  the first CPU (gdb returns the first thread). */
2150
            put_packet(s, "QC1");
2151
            break;
2152
        } else if (strcmp(p,"fThreadInfo") == 0) {
2153
            s->query_cpu = first_cpu;
2154
            goto report_cpuinfo;
2155
        } else if (strcmp(p,"sThreadInfo") == 0) {
2156
        report_cpuinfo:
2157
            if (s->query_cpu) {
2158
                snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2159
                put_packet(s, buf);
2160
                s->query_cpu = s->query_cpu->next_cpu;
2161
            } else
2162
                put_packet(s, "l");
2163
            break;
2164
        } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2165
            thread = strtoull(p+16, (char **)&p, 16);
2166
            env = find_cpu(thread);
2167
            if (env != NULL) {
2168
                cpu_synchronize_state(env);
2169
                len = snprintf((char *)mem_buf, sizeof(mem_buf),
2170
                               "CPU#%d [%s]", env->cpu_index,
2171
                               env->halted ? "halted " : "running");
2172
                memtohex(buf, mem_buf, len);
2173
                put_packet(s, buf);
2174
            }
2175
            break;
2176
        }
2177
#ifdef CONFIG_USER_ONLY
2178
        else if (strncmp(p, "Offsets", 7) == 0) {
2179
            TaskState *ts = s->c_cpu->opaque;
2180

    
2181
            snprintf(buf, sizeof(buf),
2182
                     "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2183
                     ";Bss=" TARGET_ABI_FMT_lx,
2184
                     ts->info->code_offset,
2185
                     ts->info->data_offset,
2186
                     ts->info->data_offset);
2187
            put_packet(s, buf);
2188
            break;
2189
        }
2190
#else /* !CONFIG_USER_ONLY */
2191
        else if (strncmp(p, "Rcmd,", 5) == 0) {
2192
            int len = strlen(p + 5);
2193

    
2194
            if ((len % 2) != 0) {
2195
                put_packet(s, "E01");
2196
                break;
2197
            }
2198
            hextomem(mem_buf, p + 5, len);
2199
            len = len / 2;
2200
            mem_buf[len++] = 0;
2201
            qemu_chr_read(s->mon_chr, mem_buf, len);
2202
            put_packet(s, "OK");
2203
            break;
2204
        }
2205
#endif /* !CONFIG_USER_ONLY */
2206
        if (strncmp(p, "Supported", 9) == 0) {
2207
            snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2208
#ifdef GDB_CORE_XML
2209
            pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2210
#endif
2211
            put_packet(s, buf);
2212
            break;
2213
        }
2214
#ifdef GDB_CORE_XML
2215
        if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2216
            const char *xml;
2217
            target_ulong total_len;
2218

    
2219
            gdb_has_xml = 1;
2220
            p += 19;
2221
            xml = get_feature_xml(p, &p);
2222
            if (!xml) {
2223
                snprintf(buf, sizeof(buf), "E00");
2224
                put_packet(s, buf);
2225
                break;
2226
            }
2227

    
2228
            if (*p == ':')
2229
                p++;
2230
            addr = strtoul(p, (char **)&p, 16);
2231
            if (*p == ',')
2232
                p++;
2233
            len = strtoul(p, (char **)&p, 16);
2234

    
2235
            total_len = strlen(xml);
2236
            if (addr > total_len) {
2237
                snprintf(buf, sizeof(buf), "E00");
2238
                put_packet(s, buf);
2239
                break;
2240
            }
2241
            if (len > (MAX_PACKET_LENGTH - 5) / 2)
2242
                len = (MAX_PACKET_LENGTH - 5) / 2;
2243
            if (len < total_len - addr) {
2244
                buf[0] = 'm';
2245
                len = memtox(buf + 1, xml + addr, len);
2246
            } else {
2247
                buf[0] = 'l';
2248
                len = memtox(buf + 1, xml + addr, total_len - addr);
2249
            }
2250
            put_packet_binary(s, buf, len + 1);
2251
            break;
2252
        }
2253
#endif
2254
        /* Unrecognised 'q' command.  */
2255
        goto unknown_command;
2256

    
2257
    default:
2258
    unknown_command:
2259
        /* put empty packet */
2260
        buf[0] = '\0';
2261
        put_packet(s, buf);
2262
        break;
2263
    }
2264
    return RS_IDLE;
2265
}
2266

    
2267
void gdb_set_stop_cpu(CPUState *env)
2268
{
2269
    gdbserver_state->c_cpu = env;
2270
    gdbserver_state->g_cpu = env;
2271
}
2272

    
2273
#ifndef CONFIG_USER_ONLY
2274
static void gdb_vm_state_change(void *opaque, int running, int reason)
2275
{
2276
    GDBState *s = gdbserver_state;
2277
    CPUState *env = s->c_cpu;
2278
    char buf[256];
2279
    const char *type;
2280
    int ret;
2281

    
2282
    if (running || s->state == RS_INACTIVE || s->state == RS_SYSCALL) {
2283
        return;
2284
    }
2285
    switch (reason) {
2286
    case VMSTOP_DEBUG:
2287
        if (env->watchpoint_hit) {
2288
            switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2289
            case BP_MEM_READ:
2290
                type = "r";
2291
                break;
2292
            case BP_MEM_ACCESS:
2293
                type = "a";
2294
                break;
2295
            default:
2296
                type = "";
2297
                break;
2298
            }
2299
            snprintf(buf, sizeof(buf),
2300
                     "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2301
                     GDB_SIGNAL_TRAP, gdb_id(env), type,
2302
                     env->watchpoint_hit->vaddr);
2303
            env->watchpoint_hit = NULL;
2304
            goto send_packet;
2305
        }
2306
        tb_flush(env);
2307
        ret = GDB_SIGNAL_TRAP;
2308
        break;
2309
    case VMSTOP_USER:
2310
        ret = GDB_SIGNAL_INT;
2311
        break;
2312
    case VMSTOP_SHUTDOWN:
2313
        ret = GDB_SIGNAL_QUIT;
2314
        break;
2315
    case VMSTOP_DISKFULL:
2316
        ret = GDB_SIGNAL_IO;
2317
        break;
2318
    case VMSTOP_WATCHDOG:
2319
        ret = GDB_SIGNAL_ALRM;
2320
        break;
2321
    case VMSTOP_PANIC:
2322
        ret = GDB_SIGNAL_ABRT;
2323
        break;
2324
    case VMSTOP_SAVEVM:
2325
    case VMSTOP_LOADVM:
2326
        return;
2327
    case VMSTOP_MIGRATE:
2328
        ret = GDB_SIGNAL_XCPU;
2329
        break;
2330
    default:
2331
        ret = GDB_SIGNAL_UNKNOWN;
2332
        break;
2333
    }
2334
    snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2335

    
2336
send_packet:
2337
    put_packet(s, buf);
2338

    
2339
    /* disable single step if it was enabled */
2340
    cpu_single_step(env, 0);
2341
}
2342
#endif
2343

    
2344
/* Send a gdb syscall request.
2345
   This accepts limited printf-style format specifiers, specifically:
2346
    %x  - target_ulong argument printed in hex.
2347
    %lx - 64-bit argument printed in hex.
2348
    %s  - string pointer (target_ulong) and length (int) pair.  */
2349
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2350
{
2351
    va_list va;
2352
    char buf[256];
2353
    char *p;
2354
    target_ulong addr;
2355
    uint64_t i64;
2356
    GDBState *s;
2357

    
2358
    s = gdbserver_state;
2359
    if (!s)
2360
        return;
2361
    gdb_current_syscall_cb = cb;
2362
    s->state = RS_SYSCALL;
2363
#ifndef CONFIG_USER_ONLY
2364
    vm_stop(VMSTOP_DEBUG);
2365
#endif
2366
    s->state = RS_IDLE;
2367
    va_start(va, fmt);
2368
    p = buf;
2369
    *(p++) = 'F';
2370
    while (*fmt) {
2371
        if (*fmt == '%') {
2372
            fmt++;
2373
            switch (*fmt++) {
2374
            case 'x':
2375
                addr = va_arg(va, target_ulong);
2376
                p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2377
                break;
2378
            case 'l':
2379
                if (*(fmt++) != 'x')
2380
                    goto bad_format;
2381
                i64 = va_arg(va, uint64_t);
2382
                p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2383
                break;
2384
            case 's':
2385
                addr = va_arg(va, target_ulong);
2386
                p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2387
                              addr, va_arg(va, int));
2388
                break;
2389
            default:
2390
            bad_format:
2391
                fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2392
                        fmt - 1);
2393
                break;
2394
            }
2395
        } else {
2396
            *(p++) = *(fmt++);
2397
        }
2398
    }
2399
    *p = 0;
2400
    va_end(va);
2401
    put_packet(s, buf);
2402
#ifdef CONFIG_USER_ONLY
2403
    gdb_handlesig(s->c_cpu, 0);
2404
#else
2405
    cpu_exit(s->c_cpu);
2406
#endif
2407
}
2408

    
2409
static void gdb_read_byte(GDBState *s, int ch)
2410
{
2411
    int i, csum;
2412
    uint8_t reply;
2413

    
2414
#ifndef CONFIG_USER_ONLY
2415
    if (s->last_packet_len) {
2416
        /* Waiting for a response to the last packet.  If we see the start
2417
           of a new command then abandon the previous response.  */
2418
        if (ch == '-') {
2419
#ifdef DEBUG_GDB
2420
            printf("Got NACK, retransmitting\n");
2421
#endif
2422
            put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2423
        }
2424
#ifdef DEBUG_GDB
2425
        else if (ch == '+')
2426
            printf("Got ACK\n");
2427
        else
2428
            printf("Got '%c' when expecting ACK/NACK\n", ch);
2429
#endif
2430
        if (ch == '+' || ch == '$')
2431
            s->last_packet_len = 0;
2432
        if (ch != '$')
2433
            return;
2434
    }
2435
    if (vm_running) {
2436
        /* when the CPU is running, we cannot do anything except stop
2437
           it when receiving a char */
2438
        vm_stop(VMSTOP_USER);
2439
    } else
2440
#endif
2441
    {
2442
        switch(s->state) {
2443
        case RS_IDLE:
2444
            if (ch == '$') {
2445
                s->line_buf_index = 0;
2446
                s->state = RS_GETLINE;
2447
            }
2448
            break;
2449
        case RS_GETLINE:
2450
            if (ch == '#') {
2451
            s->state = RS_CHKSUM1;
2452
            } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2453
                s->state = RS_IDLE;
2454
            } else {
2455
            s->line_buf[s->line_buf_index++] = ch;
2456
            }
2457
            break;
2458
        case RS_CHKSUM1:
2459
            s->line_buf[s->line_buf_index] = '\0';
2460
            s->line_csum = fromhex(ch) << 4;
2461
            s->state = RS_CHKSUM2;
2462
            break;
2463
        case RS_CHKSUM2:
2464
            s->line_csum |= fromhex(ch);
2465
            csum = 0;
2466
            for(i = 0; i < s->line_buf_index; i++) {
2467
                csum += s->line_buf[i];
2468
            }
2469
            if (s->line_csum != (csum & 0xff)) {
2470
                reply = '-';
2471
                put_buffer(s, &reply, 1);
2472
                s->state = RS_IDLE;
2473
            } else {
2474
                reply = '+';
2475
                put_buffer(s, &reply, 1);
2476
                s->state = gdb_handle_packet(s, s->line_buf);
2477
            }
2478
            break;
2479
        default:
2480
            abort();
2481
        }
2482
    }
2483
}
2484

    
2485
/* Tell the remote gdb that the process has exited.  */
2486
void gdb_exit(CPUState *env, int code)
2487
{
2488
  GDBState *s;
2489
  char buf[4];
2490

    
2491
  s = gdbserver_state;
2492
  if (!s) {
2493
      return;
2494
  }
2495
#ifdef CONFIG_USER_ONLY
2496
  if (gdbserver_fd < 0 || s->fd < 0) {
2497
      return;
2498
  }
2499
#endif
2500

    
2501
  snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2502
  put_packet(s, buf);
2503

    
2504
#ifndef CONFIG_USER_ONLY
2505
  if (s->chr) {
2506
      qemu_chr_close(s->chr);
2507
  }
2508
#endif
2509
}
2510

    
2511
#ifdef CONFIG_USER_ONLY
2512
int
2513
gdb_queuesig (void)
2514
{
2515
    GDBState *s;
2516

    
2517
    s = gdbserver_state;
2518

    
2519
    if (gdbserver_fd < 0 || s->fd < 0)
2520
        return 0;
2521
    else
2522
        return 1;
2523
}
2524

    
2525
int
2526
gdb_handlesig (CPUState *env, int sig)
2527
{
2528
  GDBState *s;
2529
  char buf[256];
2530
  int n;
2531

    
2532
  s = gdbserver_state;
2533
  if (gdbserver_fd < 0 || s->fd < 0)
2534
    return sig;
2535

    
2536
  /* disable single step if it was enabled */
2537
  cpu_single_step(env, 0);
2538
  tb_flush(env);
2539

    
2540
  if (sig != 0)
2541
    {
2542
      snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2543
      put_packet(s, buf);
2544
    }
2545
  /* put_packet() might have detected that the peer terminated the 
2546
     connection.  */
2547
  if (s->fd < 0)
2548
      return sig;
2549

    
2550
  sig = 0;
2551
  s->state = RS_IDLE;
2552
  s->running_state = 0;
2553
  while (s->running_state == 0) {
2554
      n = read (s->fd, buf, 256);
2555
      if (n > 0)
2556
        {
2557
          int i;
2558

    
2559
          for (i = 0; i < n; i++)
2560
            gdb_read_byte (s, buf[i]);
2561
        }
2562
      else if (n == 0 || errno != EAGAIN)
2563
        {
2564
          /* XXX: Connection closed.  Should probably wait for annother
2565
             connection before continuing.  */
2566
          return sig;
2567
        }
2568
  }
2569
  sig = s->signal;
2570
  s->signal = 0;
2571
  return sig;
2572
}
2573

    
2574
/* Tell the remote gdb that the process has exited due to SIG.  */
2575
void gdb_signalled(CPUState *env, int sig)
2576
{
2577
  GDBState *s;
2578
  char buf[4];
2579

    
2580
  s = gdbserver_state;
2581
  if (gdbserver_fd < 0 || s->fd < 0)
2582
    return;
2583

    
2584
  snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2585
  put_packet(s, buf);
2586
}
2587

    
2588
static void gdb_accept(void)
2589
{
2590
    GDBState *s;
2591
    struct sockaddr_in sockaddr;
2592
    socklen_t len;
2593
    int val, fd;
2594

    
2595
    for(;;) {
2596
        len = sizeof(sockaddr);
2597
        fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2598
        if (fd < 0 && errno != EINTR) {
2599
            perror("accept");
2600
            return;
2601
        } else if (fd >= 0) {
2602
#ifndef _WIN32
2603
            fcntl(fd, F_SETFD, FD_CLOEXEC);
2604
#endif
2605
            break;
2606
        }
2607
    }
2608

    
2609
    /* set short latency */
2610
    val = 1;
2611
    setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2612

    
2613
    s = qemu_mallocz(sizeof(GDBState));
2614
    s->c_cpu = first_cpu;
2615
    s->g_cpu = first_cpu;
2616
    s->fd = fd;
2617
    gdb_has_xml = 0;
2618

    
2619
    gdbserver_state = s;
2620

    
2621
    fcntl(fd, F_SETFL, O_NONBLOCK);
2622
}
2623

    
2624
static int gdbserver_open(int port)
2625
{
2626
    struct sockaddr_in sockaddr;
2627
    int fd, val, ret;
2628

    
2629
    fd = socket(PF_INET, SOCK_STREAM, 0);
2630
    if (fd < 0) {
2631
        perror("socket");
2632
        return -1;
2633
    }
2634
#ifndef _WIN32
2635
    fcntl(fd, F_SETFD, FD_CLOEXEC);
2636
#endif
2637

    
2638
    /* allow fast reuse */
2639
    val = 1;
2640
    setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2641

    
2642
    sockaddr.sin_family = AF_INET;
2643
    sockaddr.sin_port = htons(port);
2644
    sockaddr.sin_addr.s_addr = 0;
2645
    ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2646
    if (ret < 0) {
2647
        perror("bind");
2648
        return -1;
2649
    }
2650
    ret = listen(fd, 0);
2651
    if (ret < 0) {
2652
        perror("listen");
2653
        return -1;
2654
    }
2655
    return fd;
2656
}
2657

    
2658
int gdbserver_start(int port)
2659
{
2660
    gdbserver_fd = gdbserver_open(port);
2661
    if (gdbserver_fd < 0)
2662
        return -1;
2663
    /* accept connections */
2664
    gdb_accept();
2665
    return 0;
2666
}
2667

    
2668
/* Disable gdb stub for child processes.  */
2669
void gdbserver_fork(CPUState *env)
2670
{
2671
    GDBState *s = gdbserver_state;
2672
    if (gdbserver_fd < 0 || s->fd < 0)
2673
      return;
2674
    close(s->fd);
2675
    s->fd = -1;
2676
    cpu_breakpoint_remove_all(env, BP_GDB);
2677
    cpu_watchpoint_remove_all(env, BP_GDB);
2678
}
2679
#else
2680
static int gdb_chr_can_receive(void *opaque)
2681
{
2682
  /* We can handle an arbitrarily large amount of data.
2683
   Pick the maximum packet size, which is as good as anything.  */
2684
  return MAX_PACKET_LENGTH;
2685
}
2686

    
2687
static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2688
{
2689
    int i;
2690

    
2691
    for (i = 0; i < size; i++) {
2692
        gdb_read_byte(gdbserver_state, buf[i]);
2693
    }
2694
}
2695

    
2696
static void gdb_chr_event(void *opaque, int event)
2697
{
2698
    switch (event) {
2699
    case CHR_EVENT_OPENED:
2700
        vm_stop(VMSTOP_USER);
2701
        gdb_has_xml = 0;
2702
        break;
2703
    default:
2704
        break;
2705
    }
2706
}
2707

    
2708
static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2709
{
2710
    char buf[MAX_PACKET_LENGTH];
2711

    
2712
    buf[0] = 'O';
2713
    if (len > (MAX_PACKET_LENGTH/2) - 1)
2714
        len = (MAX_PACKET_LENGTH/2) - 1;
2715
    memtohex(buf + 1, (uint8_t *)msg, len);
2716
    put_packet(s, buf);
2717
}
2718

    
2719
static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2720
{
2721
    const char *p = (const char *)buf;
2722
    int max_sz;
2723

    
2724
    max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2725
    for (;;) {
2726
        if (len <= max_sz) {
2727
            gdb_monitor_output(gdbserver_state, p, len);
2728
            break;
2729
        }
2730
        gdb_monitor_output(gdbserver_state, p, max_sz);
2731
        p += max_sz;
2732
        len -= max_sz;
2733
    }
2734
    return len;
2735
}
2736

    
2737
#ifndef _WIN32
2738
static void gdb_sigterm_handler(int signal)
2739
{
2740
    if (vm_running) {
2741
        vm_stop(VMSTOP_USER);
2742
    }
2743
}
2744
#endif
2745

    
2746
int gdbserver_start(const char *device)
2747
{
2748
    GDBState *s;
2749
    char gdbstub_device_name[128];
2750
    CharDriverState *chr = NULL;
2751
    CharDriverState *mon_chr;
2752

    
2753
    if (!device)
2754
        return -1;
2755
    if (strcmp(device, "none") != 0) {
2756
        if (strstart(device, "tcp:", NULL)) {
2757
            /* enforce required TCP attributes */
2758
            snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2759
                     "%s,nowait,nodelay,server", device);
2760
            device = gdbstub_device_name;
2761
        }
2762
#ifndef _WIN32
2763
        else if (strcmp(device, "stdio") == 0) {
2764
            struct sigaction act;
2765

    
2766
            memset(&act, 0, sizeof(act));
2767
            act.sa_handler = gdb_sigterm_handler;
2768
            sigaction(SIGINT, &act, NULL);
2769
        }
2770
#endif
2771
        chr = qemu_chr_open("gdb", device, NULL);
2772
        if (!chr)
2773
            return -1;
2774

    
2775
        qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2776
                              gdb_chr_event, NULL);
2777
    }
2778

    
2779
    s = gdbserver_state;
2780
    if (!s) {
2781
        s = qemu_mallocz(sizeof(GDBState));
2782
        gdbserver_state = s;
2783

    
2784
        qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2785

    
2786
        /* Initialize a monitor terminal for gdb */
2787
        mon_chr = qemu_mallocz(sizeof(*mon_chr));
2788
        mon_chr->chr_write = gdb_monitor_write;
2789
        monitor_init(mon_chr, 0);
2790
    } else {
2791
        if (s->chr)
2792
            qemu_chr_close(s->chr);
2793
        mon_chr = s->mon_chr;
2794
        memset(s, 0, sizeof(GDBState));
2795
    }
2796
    s->c_cpu = first_cpu;
2797
    s->g_cpu = first_cpu;
2798
    s->chr = chr;
2799
    s->state = chr ? RS_IDLE : RS_INACTIVE;
2800
    s->mon_chr = mon_chr;
2801

    
2802
    return 0;
2803
}
2804
#endif