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/*
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 * ACPI implementation
3
 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License version 2 as published by the Free Software Foundation.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>
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 */
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#include "hw.h"
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#include "pc.h"
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#include "apm.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "acpi.h"
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#include "sysemu.h"
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#include "range.h"
26

    
27
//#define DEBUG
28

    
29
#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
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#else
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# define PIIX4_DPRINTF(format, ...)     do { } while (0)
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#endif
34

    
35
#define ACPI_DBG_IO_ADDR  0xb044
36

    
37
#define GPE_BASE 0xafe0
38
#define PCI_BASE 0xae00
39
#define PCI_EJ_BASE 0xae08
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#define PCI_RMV_BASE 0xae0c
41

    
42
#define PIIX4_PCI_HOTPLUG_STATUS 2
43

    
44
struct gpe_regs {
45
    uint16_t sts; /* status */
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    uint16_t en;  /* enabled */
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};
48

    
49
struct pci_status {
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    uint32_t up;
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    uint32_t down;
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};
53

    
54
typedef struct PIIX4PMState {
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    PCIDevice dev;
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    IORange ioport;
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    uint16_t pmsts;
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    uint16_t pmen;
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    uint16_t pmcntrl;
60

    
61
    APMState apm;
62

    
63
    QEMUTimer *tmr_timer;
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    int64_t tmr_overflow_time;
65

    
66
    PMSMBus smb;
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    uint32_t smb_io_base;
68

    
69
    qemu_irq irq;
70
    qemu_irq cmos_s3;
71
    qemu_irq smi_irq;
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    int kvm_enabled;
73

    
74
    /* for pci hotplug */
75
    struct gpe_regs gpe;
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    struct pci_status pci0_status;
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    uint32_t pci0_hotplug_enable;
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} PIIX4PMState;
79

    
80
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
81

    
82
#define ACPI_ENABLE 0xf1
83
#define ACPI_DISABLE 0xf0
84

    
85
static uint32_t get_pmtmr(PIIX4PMState *s)
86
{
87
    uint32_t d;
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    d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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    return d & 0xffffff;
90
}
91

    
92
static int get_pmsts(PIIX4PMState *s)
93
{
94
    int64_t d;
95

    
96
    d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY,
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                 get_ticks_per_sec());
98
    if (d >= s->tmr_overflow_time)
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        s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
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    return s->pmsts;
101
}
102

    
103
static void pm_update_sci(PIIX4PMState *s)
104
{
105
    int sci_level, pmsts;
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    int64_t expire_time;
107

    
108
    pmsts = get_pmsts(s);
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    sci_level = (((pmsts & s->pmen) &
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                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
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                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
112
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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                   ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
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        (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
115

    
116
    qemu_set_irq(s->irq, sci_level);
117
    /* schedule a timer interruption if needed */
118
    if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
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        !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
120
        expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
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                               PM_TIMER_FREQUENCY);
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        qemu_mod_timer(s->tmr_timer, expire_time);
123
    } else {
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        qemu_del_timer(s->tmr_timer);
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    }
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}
127

    
128
static void pm_tmr_timer(void *opaque)
129
{
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    PIIX4PMState *s = opaque;
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    pm_update_sci(s);
132
}
133

    
134
static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
135
                            uint64_t val)
136
{
137
    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
138

    
139
    if (width != 2) {
140
        PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
141
                      (unsigned)addr, width, (unsigned)val);
142
    }
143

    
144
    switch(addr) {
145
    case 0x00:
146
        {
147
            int64_t d;
148
            int pmsts;
149
            pmsts = get_pmsts(s);
150
            if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
151
                /* if TMRSTS is reset, then compute the new overflow time */
152
                d = muldiv64(qemu_get_clock_ns(vm_clock), PM_TIMER_FREQUENCY,
153
                             get_ticks_per_sec());
154
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
155
            }
156
            s->pmsts &= ~val;
157
            pm_update_sci(s);
158
        }
159
        break;
160
    case 0x02:
161
        s->pmen = val;
162
        pm_update_sci(s);
163
        break;
164
    case 0x04:
165
        {
166
            int sus_typ;
167
            s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
168
            if (val & ACPI_BITMASK_SLEEP_ENABLE) {
169
                /* change suspend type */
170
                sus_typ = (val >> 10) & 7;
171
                switch(sus_typ) {
172
                case 0: /* soft power off */
173
                    qemu_system_shutdown_request();
174
                    break;
175
                case 1:
176
                    /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
177
                       Pretend that resume was caused by power button */
178
                    s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
179
                                 ACPI_BITMASK_POWER_BUTTON_STATUS);
180
                    qemu_system_reset_request();
181
                    if (s->cmos_s3) {
182
                        qemu_irq_raise(s->cmos_s3);
183
                    }
184
                default:
185
                    break;
186
                }
187
            }
188
        }
189
        break;
190
    default:
191
        break;
192
    }
193
    PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
194
                  (unsigned int)val);
195
}
196

    
197
static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
198
                            uint64_t *data)
199
{
200
    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
201
    uint32_t val;
202

    
203
    switch(addr) {
204
    case 0x00:
205
        val = get_pmsts(s);
206
        break;
207
    case 0x02:
208
        val = s->pmen;
209
        break;
210
    case 0x04:
211
        val = s->pmcntrl;
212
        break;
213
    case 0x08:
214
        val = get_pmtmr(s);
215
        break;
216
    default:
217
        val = 0;
218
        break;
219
    }
220
    PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
221
    *data = val;
222
}
223

    
224
static const IORangeOps pm_iorange_ops = {
225
    .read = pm_ioport_read,
226
    .write = pm_ioport_write,
227
};
228

    
229
static void apm_ctrl_changed(uint32_t val, void *arg)
230
{
231
    PIIX4PMState *s = arg;
232

    
233
    /* ACPI specs 3.0, 4.7.2.5 */
234
    if (val == ACPI_ENABLE) {
235
        s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
236
    } else if (val == ACPI_DISABLE) {
237
        s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
238
    }
239

    
240
    if (s->dev.config[0x5b] & (1 << 1)) {
241
        if (s->smi_irq) {
242
            qemu_irq_raise(s->smi_irq);
243
        }
244
    }
245
}
246

    
247
static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
248
{
249
    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
250
}
251

    
252
static void pm_io_space_update(PIIX4PMState *s)
253
{
254
    uint32_t pm_io_base;
255

    
256
    if (s->dev.config[0x80] & 1) {
257
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
258
        pm_io_base &= 0xffc0;
259

    
260
        /* XXX: need to improve memory and ioport allocation */
261
        PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
262
        iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
263
        ioport_register(&s->ioport);
264
    }
265
}
266

    
267
static void pm_write_config(PCIDevice *d,
268
                            uint32_t address, uint32_t val, int len)
269
{
270
    pci_default_write_config(d, address, val, len);
271
    if (range_covers_byte(address, len, 0x80))
272
        pm_io_space_update((PIIX4PMState *)d);
273
}
274

    
275
static int vmstate_acpi_post_load(void *opaque, int version_id)
276
{
277
    PIIX4PMState *s = opaque;
278

    
279
    pm_io_space_update(s);
280
    return 0;
281
}
282

    
283
static const VMStateDescription vmstate_gpe = {
284
    .name = "gpe",
285
    .version_id = 1,
286
    .minimum_version_id = 1,
287
    .minimum_version_id_old = 1,
288
    .fields      = (VMStateField []) {
289
        VMSTATE_UINT16(sts, struct gpe_regs),
290
        VMSTATE_UINT16(en, struct gpe_regs),
291
        VMSTATE_END_OF_LIST()
292
    }
293
};
294

    
295
static const VMStateDescription vmstate_pci_status = {
296
    .name = "pci_status",
297
    .version_id = 1,
298
    .minimum_version_id = 1,
299
    .minimum_version_id_old = 1,
300
    .fields      = (VMStateField []) {
301
        VMSTATE_UINT32(up, struct pci_status),
302
        VMSTATE_UINT32(down, struct pci_status),
303
        VMSTATE_END_OF_LIST()
304
    }
305
};
306

    
307
static const VMStateDescription vmstate_acpi = {
308
    .name = "piix4_pm",
309
    .version_id = 2,
310
    .minimum_version_id = 1,
311
    .minimum_version_id_old = 1,
312
    .post_load = vmstate_acpi_post_load,
313
    .fields      = (VMStateField []) {
314
        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
315
        VMSTATE_UINT16(pmsts, PIIX4PMState),
316
        VMSTATE_UINT16(pmen, PIIX4PMState),
317
        VMSTATE_UINT16(pmcntrl, PIIX4PMState),
318
        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
319
        VMSTATE_TIMER(tmr_timer, PIIX4PMState),
320
        VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
321
        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
322
        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
323
                       struct pci_status),
324
        VMSTATE_END_OF_LIST()
325
    }
326
};
327

    
328
static void piix4_update_hotplug(PIIX4PMState *s)
329
{
330
    PCIDevice *dev = &s->dev;
331
    BusState *bus = qdev_get_parent_bus(&dev->qdev);
332
    DeviceState *qdev, *next;
333

    
334
    s->pci0_hotplug_enable = ~0;
335

    
336
    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
337
        PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
338
        PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
339
        int slot = PCI_SLOT(pdev->devfn);
340

    
341
        if (info->no_hotplug) {
342
            s->pci0_hotplug_enable &= ~(1 << slot);
343
        }
344
    }
345
}
346

    
347
static void piix4_reset(void *opaque)
348
{
349
    PIIX4PMState *s = opaque;
350
    uint8_t *pci_conf = s->dev.config;
351

    
352
    pci_conf[0x58] = 0;
353
    pci_conf[0x59] = 0;
354
    pci_conf[0x5a] = 0;
355
    pci_conf[0x5b] = 0;
356

    
357
    if (s->kvm_enabled) {
358
        /* Mark SMM as already inited (until KVM supports SMM). */
359
        pci_conf[0x5B] = 0x02;
360
    }
361
    piix4_update_hotplug(s);
362
}
363

    
364
static void piix4_powerdown(void *opaque, int irq, int power_failing)
365
{
366
    PIIX4PMState *s = opaque;
367

    
368
    if (!s) {
369
        qemu_system_shutdown_request();
370
    } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
371
        s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
372
        pm_update_sci(s);
373
    }
374
}
375

    
376
static int piix4_pm_initfn(PCIDevice *dev)
377
{
378
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
379
    uint8_t *pci_conf;
380

    
381
    pci_conf = s->dev.config;
382
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
383
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
384
    pci_conf[0x06] = 0x80;
385
    pci_conf[0x07] = 0x02;
386
    pci_conf[0x08] = 0x03; // revision number
387
    pci_conf[0x09] = 0x00;
388
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
389
    pci_conf[0x3d] = 0x01; // interrupt pin 1
390

    
391
    pci_conf[0x40] = 0x01; /* PM io base read only bit */
392

    
393
    /* APM */
394
    apm_init(&s->apm, apm_ctrl_changed, s);
395

    
396
    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
397

    
398
    if (s->kvm_enabled) {
399
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
400
         * support SMM mode. */
401
        pci_conf[0x5B] = 0x02;
402
    }
403

    
404
    /* XXX: which specification is used ? The i82731AB has different
405
       mappings */
406
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
407
    pci_conf[0x63] = 0x60;
408
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
409
        (serial_hds[1] != NULL ? 0x90 : 0);
410

    
411
    pci_conf[0x90] = s->smb_io_base | 1;
412
    pci_conf[0x91] = s->smb_io_base >> 8;
413
    pci_conf[0xd2] = 0x09;
414
    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
415
    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
416

    
417
    s->tmr_timer = qemu_new_timer_ns(vm_clock, pm_tmr_timer, s);
418

    
419
    qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
420

    
421
    pm_smbus_init(&s->dev.qdev, &s->smb);
422
    qemu_register_reset(piix4_reset, s);
423
    piix4_acpi_system_hot_add_init(dev->bus, s);
424

    
425
    return 0;
426
}
427

    
428
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
429
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
430
                       int kvm_enabled)
431
{
432
    PCIDevice *dev;
433
    PIIX4PMState *s;
434

    
435
    dev = pci_create(bus, devfn, "PIIX4_PM");
436
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
437

    
438
    s = DO_UPCAST(PIIX4PMState, dev, dev);
439
    s->irq = sci_irq;
440
    s->cmos_s3 = cmos_s3;
441
    s->smi_irq = smi_irq;
442
    s->kvm_enabled = kvm_enabled;
443

    
444
    qdev_init_nofail(&dev->qdev);
445

    
446
    return s->smb.smbus;
447
}
448

    
449
static PCIDeviceInfo piix4_pm_info = {
450
    .qdev.name          = "PIIX4_PM",
451
    .qdev.desc          = "PM",
452
    .qdev.size          = sizeof(PIIX4PMState),
453
    .qdev.vmsd          = &vmstate_acpi,
454
    .qdev.no_user       = 1,
455
    .no_hotplug         = 1,
456
    .init               = piix4_pm_initfn,
457
    .config_write       = pm_write_config,
458
    .qdev.props         = (Property[]) {
459
        DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
460
        DEFINE_PROP_END_OF_LIST(),
461
    }
462
};
463

    
464
static void piix4_pm_register(void)
465
{
466
    pci_qdev_register(&piix4_pm_info);
467
}
468

    
469
device_init(piix4_pm_register);
470

    
471
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
472
{
473
    if (addr & 1)
474
        return (val >> 8) & 0xff;
475
    return val & 0xff;
476
}
477

    
478
static uint32_t gpe_readb(void *opaque, uint32_t addr)
479
{
480
    uint32_t val = 0;
481
    PIIX4PMState *s = opaque;
482
    struct gpe_regs *g = &s->gpe;
483

    
484
    switch (addr) {
485
        case GPE_BASE:
486
        case GPE_BASE + 1:
487
            val = gpe_read_val(g->sts, addr);
488
            break;
489
        case GPE_BASE + 2:
490
        case GPE_BASE + 3:
491
            val = gpe_read_val(g->en, addr);
492
            break;
493
        default:
494
            break;
495
    }
496

    
497
    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
498
    return val;
499
}
500

    
501
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
502
{
503
    if (addr & 1)
504
        *cur = (*cur & 0xff) | (val << 8);
505
    else
506
        *cur = (*cur & 0xff00) | (val & 0xff);
507
}
508

    
509
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
510
{
511
    uint16_t x1, x0 = val & 0xff;
512
    int shift = (addr & 1) ? 8 : 0;
513

    
514
    x1 = (*cur >> shift) & 0xff;
515

    
516
    x1 = x1 & ~x0;
517

    
518
    *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
519
}
520

    
521
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
522
{
523
    PIIX4PMState *s = opaque;
524
    struct gpe_regs *g = &s->gpe;
525

    
526
    switch (addr) {
527
        case GPE_BASE:
528
        case GPE_BASE + 1:
529
            gpe_reset_val(&g->sts, addr, val);
530
            break;
531
        case GPE_BASE + 2:
532
        case GPE_BASE + 3:
533
            gpe_write_val(&g->en, addr, val);
534
            break;
535
        default:
536
            break;
537
    }
538

    
539
    pm_update_sci(s);
540

    
541
    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
542
}
543

    
544
static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
545
{
546
    uint32_t val = 0;
547
    struct pci_status *g = opaque;
548
    switch (addr) {
549
        case PCI_BASE:
550
            val = g->up;
551
            break;
552
        case PCI_BASE + 4:
553
            val = g->down;
554
            break;
555
        default:
556
            break;
557
    }
558

    
559
    PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
560
    return val;
561
}
562

    
563
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
564
{
565
    struct pci_status *g = opaque;
566
    switch (addr) {
567
        case PCI_BASE:
568
            g->up = val;
569
            break;
570
        case PCI_BASE + 4:
571
            g->down = val;
572
            break;
573
   }
574

    
575
    PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
576
}
577

    
578
static uint32_t pciej_read(void *opaque, uint32_t addr)
579
{
580
    PIIX4_DPRINTF("pciej read %x\n", addr);
581
    return 0;
582
}
583

    
584
static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
585
{
586
    BusState *bus = opaque;
587
    DeviceState *qdev, *next;
588
    PCIDevice *dev;
589
    int slot = ffs(val) - 1;
590

    
591
    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
592
        dev = DO_UPCAST(PCIDevice, qdev, qdev);
593
        if (PCI_SLOT(dev->devfn) == slot) {
594
            qdev_free(qdev);
595
        }
596
    }
597

    
598

    
599
    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
600
}
601

    
602
static uint32_t pcirmv_read(void *opaque, uint32_t addr)
603
{
604
    PIIX4PMState *s = opaque;
605

    
606
    return s->pci0_hotplug_enable;
607
}
608

    
609
static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
610
{
611
    return;
612
}
613

    
614
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
615
                                PCIHotplugState state);
616

    
617
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
618
{
619
    struct pci_status *pci0_status = &s->pci0_status;
620

    
621
    register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
622
    register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
623

    
624
    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
625
    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
626

    
627
    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
628
    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
629

    
630
    register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
631
    register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
632

    
633
    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
634
}
635

    
636
static void enable_device(PIIX4PMState *s, int slot)
637
{
638
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
639
    s->pci0_status.up |= (1 << slot);
640
}
641

    
642
static void disable_device(PIIX4PMState *s, int slot)
643
{
644
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
645
    s->pci0_status.down |= (1 << slot);
646
}
647

    
648
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
649
                                PCIHotplugState state)
650
{
651
    int slot = PCI_SLOT(dev->devfn);
652
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
653
                                DO_UPCAST(PCIDevice, qdev, qdev));
654

    
655
    /* Don't send event when device is enabled during qemu machine creation:
656
     * it is present on boot, no hotplug event is necessary. We do send an
657
     * event when the device is disabled later. */
658
    if (state == PCI_COLDPLUG_ENABLED) {
659
        return 0;
660
    }
661

    
662
    s->pci0_status.up = 0;
663
    s->pci0_status.down = 0;
664
    if (state == PCI_HOTPLUG_ENABLED) {
665
        enable_device(s, slot);
666
    } else {
667
        disable_device(s, slot);
668
    }
669

    
670
    pm_update_sci(s);
671

    
672
    return 0;
673
}