Revision 5a1e8ffb target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 1965 | 1965 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 1966 | 1966 |
DT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 1967 | 1967 |
RESTORE_ROUNDING_MODE; |
| 1968 |
update_fcr31(); |
|
| 1969 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 1970 |
DT2 = 0x7fffffffffffffffULL; |
|
| 1968 | 1971 |
DEBUG_FPU_STATE(); |
| 1969 | 1972 |
RETURN(); |
| 1970 | 1973 |
} |
| ... | ... | |
| 1973 | 1976 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 1974 | 1977 |
DT2 = float32_round_to_int(FST0, &env->fp_status); |
| 1975 | 1978 |
RESTORE_ROUNDING_MODE; |
| 1979 |
update_fcr31(); |
|
| 1980 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 1981 |
DT2 = 0x7fffffffffffffffULL; |
|
| 1976 | 1982 |
DEBUG_FPU_STATE(); |
| 1977 | 1983 |
RETURN(); |
| 1978 | 1984 |
} |
| ... | ... | |
| 1981 | 1987 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 1982 | 1988 |
WT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 1983 | 1989 |
RESTORE_ROUNDING_MODE; |
| 1990 |
update_fcr31(); |
|
| 1991 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 1992 |
WT2 = 0x7fffffff; |
|
| 1984 | 1993 |
DEBUG_FPU_STATE(); |
| 1985 | 1994 |
RETURN(); |
| 1986 | 1995 |
} |
| ... | ... | |
| 1989 | 1998 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
| 1990 | 1999 |
WT2 = float32_round_to_int(FST0, &env->fp_status); |
| 1991 | 2000 |
RESTORE_ROUNDING_MODE; |
| 2001 |
update_fcr31(); |
|
| 2002 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2003 |
WT2 = 0x7fffffff; |
|
| 1992 | 2004 |
DEBUG_FPU_STATE(); |
| 1993 | 2005 |
RETURN(); |
| 1994 | 2006 |
} |
| ... | ... | |
| 1996 | 2008 |
FLOAT_OP(truncl, d) |
| 1997 | 2009 |
{
|
| 1998 | 2010 |
DT2 = float64_to_int64_round_to_zero(FDT0, &env->fp_status); |
| 2011 |
update_fcr31(); |
|
| 2012 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2013 |
DT2 = 0x7fffffffffffffffULL; |
|
| 1999 | 2014 |
DEBUG_FPU_STATE(); |
| 2000 | 2015 |
RETURN(); |
| 2001 | 2016 |
} |
| 2002 | 2017 |
FLOAT_OP(truncl, s) |
| 2003 | 2018 |
{
|
| 2004 | 2019 |
DT2 = float32_to_int64_round_to_zero(FST0, &env->fp_status); |
| 2020 |
update_fcr31(); |
|
| 2021 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2022 |
DT2 = 0x7fffffffffffffffULL; |
|
| 2005 | 2023 |
DEBUG_FPU_STATE(); |
| 2006 | 2024 |
RETURN(); |
| 2007 | 2025 |
} |
| 2008 | 2026 |
FLOAT_OP(truncw, d) |
| 2009 | 2027 |
{
|
| 2010 | 2028 |
WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); |
| 2029 |
update_fcr31(); |
|
| 2030 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2031 |
WT2 = 0x7fffffff; |
|
| 2011 | 2032 |
DEBUG_FPU_STATE(); |
| 2012 | 2033 |
RETURN(); |
| 2013 | 2034 |
} |
| 2014 | 2035 |
FLOAT_OP(truncw, s) |
| 2015 | 2036 |
{
|
| 2016 | 2037 |
WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); |
| 2038 |
update_fcr31(); |
|
| 2039 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2040 |
WT2 = 0x7fffffff; |
|
| 2017 | 2041 |
DEBUG_FPU_STATE(); |
| 2018 | 2042 |
RETURN(); |
| 2019 | 2043 |
} |
| ... | ... | |
| 2023 | 2047 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
| 2024 | 2048 |
DT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 2025 | 2049 |
RESTORE_ROUNDING_MODE; |
| 2050 |
update_fcr31(); |
|
| 2051 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2052 |
DT2 = 0x7fffffffffffffffULL; |
|
| 2026 | 2053 |
DEBUG_FPU_STATE(); |
| 2027 | 2054 |
RETURN(); |
| 2028 | 2055 |
} |
| ... | ... | |
| 2031 | 2058 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
| 2032 | 2059 |
DT2 = float32_round_to_int(FST0, &env->fp_status); |
| 2033 | 2060 |
RESTORE_ROUNDING_MODE; |
| 2061 |
update_fcr31(); |
|
| 2062 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2063 |
DT2 = 0x7fffffffffffffffULL; |
|
| 2034 | 2064 |
DEBUG_FPU_STATE(); |
| 2035 | 2065 |
RETURN(); |
| 2036 | 2066 |
} |
| ... | ... | |
| 2039 | 2069 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
| 2040 | 2070 |
WT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 2041 | 2071 |
RESTORE_ROUNDING_MODE; |
| 2072 |
update_fcr31(); |
|
| 2073 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2074 |
WT2 = 0x7fffffff; |
|
| 2042 | 2075 |
DEBUG_FPU_STATE(); |
| 2043 | 2076 |
RETURN(); |
| 2044 | 2077 |
} |
| ... | ... | |
| 2047 | 2080 |
set_float_rounding_mode(float_round_up, &env->fp_status); |
| 2048 | 2081 |
WT2 = float32_round_to_int(FST0, &env->fp_status); |
| 2049 | 2082 |
RESTORE_ROUNDING_MODE; |
| 2083 |
update_fcr31(); |
|
| 2084 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2085 |
WT2 = 0x7fffffff; |
|
| 2050 | 2086 |
DEBUG_FPU_STATE(); |
| 2051 | 2087 |
RETURN(); |
| 2052 | 2088 |
} |
| ... | ... | |
| 2056 | 2092 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
| 2057 | 2093 |
DT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 2058 | 2094 |
RESTORE_ROUNDING_MODE; |
| 2095 |
update_fcr31(); |
|
| 2096 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2097 |
DT2 = 0x7fffffffffffffffULL; |
|
| 2059 | 2098 |
DEBUG_FPU_STATE(); |
| 2060 | 2099 |
RETURN(); |
| 2061 | 2100 |
} |
| ... | ... | |
| 2064 | 2103 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
| 2065 | 2104 |
DT2 = float32_round_to_int(FST0, &env->fp_status); |
| 2066 | 2105 |
RESTORE_ROUNDING_MODE; |
| 2106 |
update_fcr31(); |
|
| 2107 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2108 |
DT2 = 0x7fffffffffffffffULL; |
|
| 2067 | 2109 |
DEBUG_FPU_STATE(); |
| 2068 | 2110 |
RETURN(); |
| 2069 | 2111 |
} |
| ... | ... | |
| 2072 | 2114 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
| 2073 | 2115 |
WT2 = float64_round_to_int(FDT0, &env->fp_status); |
| 2074 | 2116 |
RESTORE_ROUNDING_MODE; |
| 2117 |
update_fcr31(); |
|
| 2118 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2119 |
WT2 = 0x7fffffff; |
|
| 2075 | 2120 |
DEBUG_FPU_STATE(); |
| 2076 | 2121 |
RETURN(); |
| 2077 | 2122 |
} |
| ... | ... | |
| 2080 | 2125 |
set_float_rounding_mode(float_round_down, &env->fp_status); |
| 2081 | 2126 |
WT2 = float32_round_to_int(FST0, &env->fp_status); |
| 2082 | 2127 |
RESTORE_ROUNDING_MODE; |
| 2128 |
update_fcr31(); |
|
| 2129 |
if (GET_FP_CAUSE(env->fcr31) & (FP_OVERFLOW | FP_INVALID)) |
|
| 2130 |
WT2 = 0x7fffffff; |
|
| 2083 | 2131 |
DEBUG_FPU_STATE(); |
| 2084 | 2132 |
RETURN(); |
| 2085 | 2133 |
} |
| ... | ... | |
| 2396 | 2444 |
CLEAR_FP_COND(PARAM1, env); \ |
| 2397 | 2445 |
DEBUG_FPU_STATE(); \ |
| 2398 | 2446 |
RETURN(); \ |
| 2447 |
} \ |
|
| 2448 |
void op_cmpabs_d_ ## op (void) \ |
|
| 2449 |
{ \
|
|
| 2450 |
int c; \ |
|
| 2451 |
FDT0 &= ~(1ULL << 63); \ |
|
| 2452 |
FDT1 &= ~(1ULL << 63); \ |
|
| 2453 |
c = cond; \ |
|
| 2454 |
update_fcr31(); \ |
|
| 2455 |
if (c) \ |
|
| 2456 |
SET_FP_COND(PARAM1, env); \ |
|
| 2457 |
else \ |
|
| 2458 |
CLEAR_FP_COND(PARAM1, env); \ |
|
| 2459 |
DEBUG_FPU_STATE(); \ |
|
| 2460 |
RETURN(); \ |
|
| 2399 | 2461 |
} |
| 2400 | 2462 |
|
| 2401 | 2463 |
int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
| ... | ... | |
| 2444 | 2506 |
CLEAR_FP_COND(PARAM1, env); \ |
| 2445 | 2507 |
DEBUG_FPU_STATE(); \ |
| 2446 | 2508 |
RETURN(); \ |
| 2509 |
} \ |
|
| 2510 |
void op_cmpabs_s_ ## op (void) \ |
|
| 2511 |
{ \
|
|
| 2512 |
int c; \ |
|
| 2513 |
FST0 &= ~(1 << 31); \ |
|
| 2514 |
FST1 &= ~(1 << 31); \ |
|
| 2515 |
c = cond; \ |
|
| 2516 |
update_fcr31(); \ |
|
| 2517 |
if (c) \ |
|
| 2518 |
SET_FP_COND(PARAM1, env); \ |
|
| 2519 |
else \ |
|
| 2520 |
CLEAR_FP_COND(PARAM1, env); \ |
|
| 2521 |
DEBUG_FPU_STATE(); \ |
|
| 2522 |
RETURN(); \ |
|
| 2447 | 2523 |
} |
| 2448 | 2524 |
|
| 2449 | 2525 |
flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) |
| ... | ... | |
| 2498 | 2574 |
CLEAR_FP_COND(PARAM1 + 1, env); \ |
| 2499 | 2575 |
DEBUG_FPU_STATE(); \ |
| 2500 | 2576 |
RETURN(); \ |
| 2577 |
} \ |
|
| 2578 |
void op_cmpabs_ps_ ## op (void) \ |
|
| 2579 |
{ \
|
|
| 2580 |
int cl, ch; \ |
|
| 2581 |
FST0 &= ~(1 << 31); \ |
|
| 2582 |
FSTH0 &= ~(1 << 31); \ |
|
| 2583 |
FST1 &= ~(1 << 31); \ |
|
| 2584 |
FSTH1 &= ~(1 << 31); \ |
|
| 2585 |
cl = condl; \ |
|
| 2586 |
ch = condh; \ |
|
| 2587 |
update_fcr31(); \ |
|
| 2588 |
if (cl) \ |
|
| 2589 |
SET_FP_COND(PARAM1, env); \ |
|
| 2590 |
else \ |
|
| 2591 |
CLEAR_FP_COND(PARAM1, env); \ |
|
| 2592 |
if (ch) \ |
|
| 2593 |
SET_FP_COND(PARAM1 + 1, env); \ |
|
| 2594 |
else \ |
|
| 2595 |
CLEAR_FP_COND(PARAM1 + 1, env); \ |
|
| 2596 |
DEBUG_FPU_STATE(); \ |
|
| 2597 |
RETURN(); \ |
|
| 2501 | 2598 |
} |
| 2502 | 2599 |
|
| 2503 | 2600 |
/* NOTE: the comma operator will make "cond" to eval to false, |
Also available in: Unified diff