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Name Size
README.sh4 4.8 kB
cpu.h 10 kB
exec.h 1.3 kB
helper.c 17.1 kB
helper.h 1.6 kB
machine.c 0 Bytes
op_helper.c 12 kB
translate.c 60.7 kB

Latest revisions

# Date Author Comment
5a25cc2b 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: separate execute and read/write permissions

On SH4, the ITLB and UTLB configurations are memory mapped, so loading
ITLB entries from UTLB has to be simulated correctly. For that the QEMU
TLB has to be handle the execute (ITLB) and read/write permissions...
1f486815 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: fix mem_idx computation

The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0
corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to user
mode (SR_MD = 0).

Signed-off-by: Aurelien Jarno <>
0f3f1ec7 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: simplify call to tlb_set_page()

tlb_set_page() doesn't need addresses with offset, but simply the
page aligned addresses.

Signed-off-by: Aurelien Jarno <>
4d1e4ff6 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: fix ITLB priviledge check

There is an ITLB access violation if SR_MD=0 (user mode) while
the high bit of the protection key is 0 (priviledge mode).

Signed-off-by: Aurelien Jarno <>
628b61a0 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: optimize UTLB accesses

With the current code, the QEMU TLB is setup to match the read/write
mode of the MMU fault. This means when read access is done, the page
is setup in read-only mode. When the page is later accessed in write
mode, an MMU fault happened, and the page is switch in write-only...
af090497 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: reduce the size of a TLB entry

Reduce the size of the TLB entry from 32 to 16 bytes, reorganising
members and using a bit field.

Signed-off-by: Aurelien Jarno <>
55ff33a4 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: remove dead code

Signed-off-by: Aurelien Jarno <>
03e3b61e 02/09/2010 10:08 pm Aurelien Jarno

target-sh4: MMU: fix store queue addresses

The store queues are located from 0xe0000000 to 0xe3ffffff.

Signed-off-by: Aurelien Jarno <>
e0bcb9ca 02/09/2010 10:07 pm Aurelien Jarno

sh7750: handle MMUCR TI bit

When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.

Signed-off-by: Aurelien Jarno <>
3101e99c 02/08/2010 01:21 pm Aurelien Jarno

target-sh4: minor optimisations

Signed-off-by: Aurelien Jarno <>

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