Revision 5a5012ec target-mips/cpu.h
b/target-mips/cpu.h | ||
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21 | 21 |
union fpr_t { |
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float64 fd; /* ieee double precision */ |
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float32 fs[2];/* ieee single precision */ |
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uint64_t d; /* binary single fixed-point */
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|
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uint64_t d; /* binary double fixed-point */
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|
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uint32_t w[2]; /* binary single fixed-point */ |
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}; |
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/* define FP_ENDIAN_IDX to access the same location |
... | ... | |
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target_ulong HI, LO; |
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/* Floating point registers */ |
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fpr_t fpr[32]; |
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#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) |
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#define FPR_FD(cpu, n) (FPR(cpu, n)->fd) |
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#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) |
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#define FPR_D(cpu, n) (FPR(cpu, n)->d) |
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#define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX]) |
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#ifndef USE_HOST_FLOAT_REGS |
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fpr_t ft0; |
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fpr_t ft1; |
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fpr_t ft2; |
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#endif |
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float_status fp_status; |
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/* fpu implementation/revision register */ |
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/* fpu implementation/revision register (fir) */
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uint32_t fcr0; |
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#define FCR0_F64 22 |
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#define FCR0_L 21 |
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#define FCR0_W 20 |
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#define FCR0_3D 19 |
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#define FCR0_PS 18 |
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#define FCR0_D 17 |
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#define FCR0_S 16 |
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#define FCR0_PRID 8 |
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#define FCR0_REV 0 |
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/* fcsr */ |
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uint32_t fcr31; |
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#define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0) |
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#define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0) |
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#define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0) |
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#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
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#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
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#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0) |
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#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0) |
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#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0) |
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#define SET_FP_COND(num,env) do { (env->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0) |
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#define CLEAR_FP_COND(num,env) do { (env->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23))); } while(0) |
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#define IS_FP_COND_SET(num,env) (((env->fcr31) & ((num) ? (1 << ((num) + 24)) : (1 << ((num) + 23)))) != 0) |
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#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
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#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
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#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
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#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
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#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
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#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
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#define FP_INEXACT 1 |
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#define FP_UNDERFLOW 2 |
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#define FP_OVERFLOW 4 |
... | ... | |
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|
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int SYNCI_Step; /* Address step size for SYNCI */ |
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int CCRes; /* Cycle count resolution/divisor */ |
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int Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
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#if defined(CONFIG_USER_ONLY) |
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target_ulong tls_value; |
... | ... | |
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EXCP_RI, |
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EXCP_OVERFLOW, |
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EXCP_TRAP, |
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EXCP_FPE, |
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EXCP_DDBS, |
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EXCP_DWATCH, |
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EXCP_LAE, |
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EXCP_SAE, /* 24 */
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EXCP_LAE, /* 24 */
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EXCP_SAE, |
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EXCP_LTLBL, |
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EXCP_TLBL, |
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EXCP_TLBS, |
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