Revision 5a834bb4 target-sparc/cpu.h

b/target-sparc/cpu.h
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    sparc_def_t *def;
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} CPUSPARCState;
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#ifndef NO_CPU_IO_DEFS
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/* helper.c */
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CPUSPARCState *cpu_sparc_init(const char *cpu_model);
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
......
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/* cpu-exec.c */
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int cpu_sparc_exec(CPUSPARCState *s);
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#if !defined (TARGET_SPARC64)
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#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
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                      (env->psref? PSR_EF : 0) |                        \
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                      (env->psrpil << 8) |                              \
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                      (env->psrs? PSR_S : 0) |                          \
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                      (env->psrps? PSR_PS : 0) |                        \
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                      (env->psret? PSR_ET : 0) | env->cwp)
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#else
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#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
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                      (env->psref? PSR_EF : 0) |                        \
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                      (env->psrpil << 8) |                              \
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                      (env->psrs? PSR_S : 0) |                          \
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                      (env->psrps? PSR_PS : 0) |                        \
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                      env->cwp)
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#endif
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#ifndef NO_CPU_IO_DEFS
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static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
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{
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    if (unlikely(cwp >= env1->nwindows))
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        cwp -= env1->nwindows;
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    return cwp;
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}
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static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
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{
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    if (unlikely(cwp < 0))
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        cwp += env1->nwindows;
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    return cwp;
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}
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/* op_helper.c */
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target_ulong cpu_get_psr(CPUState *env1);
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void cpu_put_psr(CPUState *env1, target_ulong val);
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#ifdef TARGET_SPARC64
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target_ulong cpu_get_ccr(CPUState *env1);
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void cpu_put_ccr(CPUState *env1, target_ulong val);
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target_ulong cpu_get_cwp64(CPUState *env1);
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void cpu_put_cwp64(CPUState *env1, int cwp);
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#endif
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static inline void memcpy32(target_ulong *dst, const target_ulong *src)
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{
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    dst[0] = src[0];
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    dst[1] = src[1];
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    dst[2] = src[2];
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    dst[3] = src[3];
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    dst[4] = src[4];
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    dst[5] = src[5];
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    dst[6] = src[6];
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    dst[7] = src[7];
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}
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static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
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{
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    /* put the modified wrap registers at their proper location */
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    if (env1->cwp == env1->nwindows - 1)
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        memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
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    env1->cwp = new_cwp;
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    /* put the wrap registers at their temporary location */
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    if (new_cwp == env1->nwindows - 1)
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        memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
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    env1->regwptr = env1->regbase + (new_cwp * 16);
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}
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int cpu_cwp_inc(CPUState *env1, int cwp);
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int cpu_cwp_dec(CPUState *env1, int cwp);
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void cpu_set_cwp(CPUState *env1, int new_cwp);
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/* sun4m.c, sun4u.c */
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void cpu_check_irqs(CPUSPARCState *env);
......
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}
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#endif
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static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val)
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{
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    env1->psr = val & PSR_ICC;
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    env1->psref = (val & PSR_EF)? 1 : 0;
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    env1->psrpil = (val & PSR_PIL) >> 8;
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#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
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    cpu_check_irqs(env1);
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#endif
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    env1->psrs = (val & PSR_S)? 1 : 0;
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    env1->psrps = (val & PSR_PS)? 1 : 0;
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#if !defined (TARGET_SPARC64)
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    env1->psret = (val & PSR_ET)? 1 : 0;
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#endif
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    cpu_set_cwp(env1, val & PSR_CWP);
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    env1->cc_op = CC_OP_FLAGS;
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}
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#ifdef TARGET_SPARC64
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#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
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#define PUT_CCR(env, val) do { int _tmp = val;                          \
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        env->xcc = (_tmp >> 4) << 20;                                   \
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        env->psr = (_tmp & 0xf) << 20;                                  \
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        CC_OP = CC_OP_FLAGS;                                            \
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    } while (0)
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#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
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#ifndef NO_CPU_IO_DEFS
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static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
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{
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    if (unlikely(cwp >= env1->nwindows || cwp < 0))
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        cwp %= env1->nwindows;
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    cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
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}
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#endif
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#endif
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/* cpu-exec.c */

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