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#ifndef CPU_SPARC_H
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#define CPU_SPARC_H
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#include "config.h"
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#if !defined(TARGET_SPARC64)
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#define TARGET_LONG_BITS 32
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#define TARGET_FPREGS 32
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#define TARGET_PAGE_BITS 12 /* 4k */
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#define TARGET_PHYS_ADDR_SPACE_BITS 36
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#else
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#define TARGET_LONG_BITS 64
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#define TARGET_FPREGS 64
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#define TARGET_PAGE_BITS 13 /* 8k */
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#define TARGET_PHYS_ADDR_SPACE_BITS 41
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# ifdef TARGET_ABI32
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#  define TARGET_VIRT_ADDR_SPACE_BITS 32
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# else
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#  define TARGET_VIRT_ADDR_SPACE_BITS 44
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# endif
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#endif
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#define CPUState struct CPUSPARCState
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#include "cpu-defs.h"
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#if !defined(TARGET_SPARC64)
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#define ELF_MACHINE     EM_SPARC
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#else
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#define ELF_MACHINE     EM_SPARCV9
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#endif
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/*#define EXCP_INTERRUPT 0x100*/
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/* trap definitions */
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#ifndef TARGET_SPARC64
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#define TT_TFAULT   0x01
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#define TT_ILL_INSN 0x02
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#define TT_PRIV_INSN 0x03
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#define TT_NFPU_INSN 0x04
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#define TT_WIN_OVF  0x05
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#define TT_WIN_UNF  0x06
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#define TT_UNALIGNED 0x07
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#define TT_FP_EXCP  0x08
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#define TT_DFAULT   0x09
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#define TT_TOVF     0x0a
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#define TT_EXTINT   0x10
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#define TT_CODE_ACCESS 0x21
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#define TT_UNIMP_FLUSH 0x25
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#define TT_DATA_ACCESS 0x29
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#define TT_DIV_ZERO 0x2a
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#define TT_NCP_INSN 0x24
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#define TT_TRAP     0x80
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#else
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#define TT_POWER_ON_RESET 0x01
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#define TT_TFAULT   0x08
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#define TT_CODE_ACCESS 0x0a
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#define TT_ILL_INSN 0x10
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#define TT_UNIMP_FLUSH TT_ILL_INSN
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#define TT_PRIV_INSN 0x11
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#define TT_NFPU_INSN 0x20
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#define TT_FP_EXCP  0x21
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#define TT_TOVF     0x23
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#define TT_CLRWIN   0x24
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#define TT_DIV_ZERO 0x28
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#define TT_DFAULT   0x30
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#define TT_DATA_ACCESS 0x32
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#define TT_UNALIGNED 0x34
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#define TT_PRIV_ACT 0x37
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#define TT_EXTINT   0x40
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#define TT_IVEC     0x60
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#define TT_TMISS    0x64
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#define TT_DMISS    0x68
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#define TT_DPROT    0x6c
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#define TT_SPILL    0x80
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#define TT_FILL     0xc0
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#define TT_WOTHER   0x10
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#define TT_TRAP     0x100
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#endif
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#define PSR_NEG_SHIFT 23
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#define PSR_NEG   (1 << PSR_NEG_SHIFT)
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#define PSR_ZERO_SHIFT 22
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#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
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#define PSR_OVF_SHIFT 21
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#define PSR_OVF   (1 << PSR_OVF_SHIFT)
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#define PSR_CARRY_SHIFT 20
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#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
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#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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#define PSR_EF    (1<<12)
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#define PSR_PIL   0xf00
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#define PSR_S     (1<<7)
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#define PSR_PS    (1<<6)
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#define PSR_ET    (1<<5)
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#define PSR_CWP   0x1f
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#define CC_SRC (env->cc_src)
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#define CC_SRC2 (env->cc_src2)
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#define CC_DST (env->cc_dst)
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#define CC_OP  (env->cc_op)
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enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_FLAGS,   /* all cc are back in status register */
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    CC_OP_DIV,     /* modify N, Z and V, C = 0*/
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    CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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    CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
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    CC_OP_NB,
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};
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/* Trap base register */
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#define TBR_BASE_MASK 0xfffff000
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#if defined(TARGET_SPARC64)
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#define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
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#define PS_IG    (1<<11) /* v9, zero on UA2007 */
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#define PS_MG    (1<<10) /* v9, zero on UA2007 */
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#define PS_CLE   (1<<9) /* UA2007 */
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#define PS_TLE   (1<<8) /* UA2007 */
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#define PS_RMO   (1<<7)
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#define PS_RED   (1<<5) /* v9, zero on UA2007 */
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#define PS_PEF   (1<<4) /* enable fpu */
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#define PS_AM    (1<<3) /* address mask */
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#define PS_PRIV  (1<<2)
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#define PS_IE    (1<<1)
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#define PS_AG    (1<<0) /* v9, zero on UA2007 */
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#define FPRS_FEF (1<<2)
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#define HS_PRIV  (1<<2)
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#endif
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/* Fcc */
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#define FSR_RD1        (1ULL << 31)
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#define FSR_RD0        (1ULL << 30)
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#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
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#define FSR_RD_NEAREST 0
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#define FSR_RD_ZERO    FSR_RD0
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#define FSR_RD_POS     FSR_RD1
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#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
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#define FSR_NVM   (1ULL << 27)
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#define FSR_OFM   (1ULL << 26)
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#define FSR_UFM   (1ULL << 25)
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#define FSR_DZM   (1ULL << 24)
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#define FSR_NXM   (1ULL << 23)
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#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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#define FSR_NVA   (1ULL << 9)
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#define FSR_OFA   (1ULL << 8)
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#define FSR_UFA   (1ULL << 7)
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#define FSR_DZA   (1ULL << 6)
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#define FSR_NXA   (1ULL << 5)
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#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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#define FSR_NVC   (1ULL << 4)
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#define FSR_OFC   (1ULL << 3)
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#define FSR_UFC   (1ULL << 2)
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#define FSR_DZC   (1ULL << 1)
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#define FSR_NXC   (1ULL << 0)
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#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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#define FSR_FTT2   (1ULL << 16)
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#define FSR_FTT1   (1ULL << 15)
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#define FSR_FTT0   (1ULL << 14)
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//gcc warns about constant overflow for ~FSR_FTT_MASK
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//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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#ifdef TARGET_SPARC64
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#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
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#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
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#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
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#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
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#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
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#else
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#define FSR_FTT_NMASK      0xfffe3fffULL
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#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
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#define FSR_LDFSR_OLDMASK  0x000fc000ULL
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#endif
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#define FSR_LDFSR_MASK     0xcfc00fffULL
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#define FSR_FTT_IEEE_EXCP (1ULL << 14)
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#define FSR_FTT_UNIMPFPOP (3ULL << 14)
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#define FSR_FTT_SEQ_ERROR (4ULL << 14)
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#define FSR_FTT_INVAL_FPR (6ULL << 14)
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#define FSR_FCC1_SHIFT 11
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#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
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#define FSR_FCC0_SHIFT 10
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#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
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/* MMU */
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#define MMU_E     (1<<0)
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#define MMU_NF    (1<<1)
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#define PTE_ENTRYTYPE_MASK 3
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#define PTE_ACCESS_MASK    0x1c
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#define PTE_ACCESS_SHIFT   2
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#define PTE_PPN_SHIFT      7
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#define PTE_ADDR_MASK      0xffffff00
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#define PG_ACCESSED_BIT 5
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#define PG_MODIFIED_BIT 6
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#define PG_CACHE_BIT    7
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
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#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
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/* 3 <= NWINDOWS <= 32. */
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#define MIN_NWINDOWS 3
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#define MAX_NWINDOWS 32
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#if !defined(TARGET_SPARC64)
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#define NB_MMU_MODES 2
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#else
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#define NB_MMU_MODES 6
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typedef struct trap_state {
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    uint64_t tpc;
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    uint64_t tnpc;
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    uint64_t tstate;
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    uint32_t tt;
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} trap_state;
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#endif
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typedef struct sparc_def_t {
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    const char *name;
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    target_ulong iu_version;
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    uint32_t fpu_version;
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    uint32_t mmu_version;
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    uint32_t mmu_bm;
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    uint32_t mmu_ctpr_mask;
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    uint32_t mmu_cxr_mask;
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    uint32_t mmu_sfsr_mask;
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    uint32_t mmu_trcr_mask;
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    uint32_t mxcc_version;
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    uint32_t features;
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    uint32_t nwindows;
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    uint32_t maxtl;
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} sparc_def_t;
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#define CPU_FEATURE_FLOAT    (1 << 0)
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#define CPU_FEATURE_FLOAT128 (1 << 1)
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#define CPU_FEATURE_SWAP     (1 << 2)
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#define CPU_FEATURE_MUL      (1 << 3)
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#define CPU_FEATURE_DIV      (1 << 4)
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#define CPU_FEATURE_FLUSH    (1 << 5)
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#define CPU_FEATURE_FSQRT    (1 << 6)
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#define CPU_FEATURE_FMUL     (1 << 7)
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#define CPU_FEATURE_VIS1     (1 << 8)
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#define CPU_FEATURE_VIS2     (1 << 9)
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#define CPU_FEATURE_FSMULD   (1 << 10)
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#define CPU_FEATURE_HYPV     (1 << 11)
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#define CPU_FEATURE_CMT      (1 << 12)
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#define CPU_FEATURE_GL       (1 << 13)
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#ifndef TARGET_SPARC64
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#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
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                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
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                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
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                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
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#else
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#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
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                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
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                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
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                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
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                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
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enum {
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    mmu_us_12, // Ultrasparc < III (64 entry TLB)
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    mmu_us_3,  // Ultrasparc III (512 entry TLB)
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    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
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    mmu_sun4v, // T1, T2
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};
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#endif
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#define TTE_VALID_BIT       (1ULL << 63)
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#define TTE_USED_BIT        (1ULL << 41)
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#define TTE_LOCKED_BIT      (1ULL <<  6)
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#define TTE_GLOBAL_BIT      (1ULL <<  0)
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#define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
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#define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
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#define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
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#define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
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#define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
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#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
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typedef struct SparcTLBEntry {
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    uint64_t tag;
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    uint64_t tte;
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} SparcTLBEntry;
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struct CPUTimer
304
{
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    const char *name;
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    uint32_t    frequency;
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    uint32_t    disabled;
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    uint64_t    disabled_mask;
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    int64_t     clock_offset;
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    struct QEMUTimer  *qtimer;
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};
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typedef struct CPUTimer CPUTimer;
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struct QEMUFile;
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void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
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void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
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typedef struct CPUSPARCState {
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    target_ulong gregs[8]; /* general registers */
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    target_ulong *regwptr; /* pointer to current register window */
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    target_ulong pc;       /* program counter */
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    target_ulong npc;      /* next program counter */
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    target_ulong y;        /* multiply/divide register */
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    /* emulator internal flags handling */
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    target_ulong cc_src, cc_src2;
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    target_ulong cc_dst;
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    uint32_t cc_op;
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    target_ulong t0, t1; /* temporaries live across basic blocks */
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    target_ulong cond; /* conditional branch result (XXX: save it in a
333
                          temporary register when possible) */
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    uint32_t psr;      /* processor state register */
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    target_ulong fsr;      /* FPU state register */
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    float32 fpr[TARGET_FPREGS];  /* floating point registers */
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    uint32_t cwp;      /* index of current register window (extracted
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                          from PSR) */
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#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
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    uint32_t wim;      /* window invalid mask */
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#endif
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    target_ulong tbr;  /* trap base register */
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    int      psrs;     /* supervisor mode (extracted from PSR) */
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    int      psrps;    /* previous supervisor mode */
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#if !defined(TARGET_SPARC64)
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    int      psret;    /* enable traps */
348
#endif
349
    uint32_t psrpil;   /* interrupt blocking level */
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    uint32_t pil_in;   /* incoming interrupt level bitmap */
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    int      psref;    /* enable fpu */
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    target_ulong version;
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    int interrupt_index;
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    uint32_t nwindows;
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    /* NOTE: we allow 8 more registers to handle wrapping */
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    target_ulong regbase[MAX_NWINDOWS * 16 + 8];
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    CPU_COMMON
359

    
360
    /* MMU regs */
361
#if defined(TARGET_SPARC64)
362
    uint64_t lsu;
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#define DMMU_E 0x8
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#define IMMU_E 0x4
365
    //typedef struct SparcMMU
366
    union {
367
        uint64_t immuregs[16];
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        struct {
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            uint64_t tsb_tag_target;
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            uint64_t unused_mmu_primary_context;   // use DMMU
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            uint64_t unused_mmu_secondary_context; // use DMMU
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            uint64_t sfsr;
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            uint64_t sfar;
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            uint64_t tsb;
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            uint64_t tag_access;
376
        } immu;
377
    };
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    union {
379
        uint64_t dmmuregs[16];
380
        struct {
381
            uint64_t tsb_tag_target;
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            uint64_t mmu_primary_context;
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            uint64_t mmu_secondary_context;
384
            uint64_t sfsr;
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            uint64_t sfar;
386
            uint64_t tsb;
387
            uint64_t tag_access;
388
        } dmmu;
389
    };
390
    SparcTLBEntry itlb[64];
391
    SparcTLBEntry dtlb[64];
392
    uint32_t mmu_version;
393
#else
394
    uint32_t mmuregs[32];
395
    uint64_t mxccdata[4];
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    uint64_t mxccregs[8];
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    uint64_t mmubpregs[4];
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    uint64_t prom_addr;
399
#endif
400
    /* temporary float registers */
401
    float64 dt0, dt1;
402
    float128 qt0, qt1;
403
    float_status fp_status;
404
#if defined(TARGET_SPARC64)
405
#define MAXTL_MAX 8
406
#define MAXTL_MASK (MAXTL_MAX - 1)
407
    trap_state ts[MAXTL_MAX];
408
    uint32_t xcc;               /* Extended integer condition codes */
409
    uint32_t asi;
410
    uint32_t pstate;
411
    uint32_t tl;
412
    uint32_t maxtl;
413
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
414
    uint64_t agregs[8]; /* alternate general registers */
415
    uint64_t bgregs[8]; /* backup for normal global registers */
416
    uint64_t igregs[8]; /* interrupt general registers */
417
    uint64_t mgregs[8]; /* mmu general registers */
418
    uint64_t fprs;
419
    uint64_t tick_cmpr, stick_cmpr;
420
    CPUTimer *tick, *stick;
421
#define TICK_NPT_MASK        0x8000000000000000ULL
422
#define TICK_INT_DIS         0x8000000000000000ULL
423
    uint64_t gsr;
424
    uint32_t gl; // UA2005
425
    /* UA 2005 hyperprivileged registers */
426
    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
427
    CPUTimer *hstick; // UA 2005
428
    uint32_t softint;
429
#define SOFTINT_TIMER   1
430
#define SOFTINT_STIMER  (1 << 16)
431
#define SOFTINT_INTRMASK (0xFFFE)
432
#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
433
#endif
434
    sparc_def_t *def;
435
} CPUSPARCState;
436

    
437
#ifndef NO_CPU_IO_DEFS
438
/* helper.c */
439
CPUSPARCState *cpu_sparc_init(const char *cpu_model);
440
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
441
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
442
                                                 ...));
443
void cpu_lock(void);
444
void cpu_unlock(void);
445
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
446
                               int mmu_idx, int is_softmmu);
447
#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
448
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
449
void dump_mmu(CPUSPARCState *env);
450

    
451
/* translate.c */
452
void gen_intermediate_code_init(CPUSPARCState *env);
453

    
454
/* cpu-exec.c */
455
int cpu_sparc_exec(CPUSPARCState *s);
456

    
457
/* op_helper.c */
458
target_ulong cpu_get_psr(CPUState *env1);
459
void cpu_put_psr(CPUState *env1, target_ulong val);
460
#ifdef TARGET_SPARC64
461
target_ulong cpu_get_ccr(CPUState *env1);
462
void cpu_put_ccr(CPUState *env1, target_ulong val);
463
target_ulong cpu_get_cwp64(CPUState *env1);
464
void cpu_put_cwp64(CPUState *env1, int cwp);
465
#endif
466
int cpu_cwp_inc(CPUState *env1, int cwp);
467
int cpu_cwp_dec(CPUState *env1, int cwp);
468
void cpu_set_cwp(CPUState *env1, int new_cwp);
469

    
470
/* sun4m.c, sun4u.c */
471
void cpu_check_irqs(CPUSPARCState *env);
472

    
473
#if defined (TARGET_SPARC64)
474

    
475
static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
476
{
477
    return (x & mask) == (y & mask);
478
}
479

    
480
#define MMU_CONTEXT_BITS 13
481
#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
482

    
483
static inline int tlb_compare_context(const SparcTLBEntry *tlb,
484
                                      uint64_t context)
485
{
486
    return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
487
}
488

    
489
#endif
490
#endif
491

    
492
/* cpu-exec.c */
493
#if !defined(CONFIG_USER_ONLY)
494
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
495
                          int is_asi, int size);
496
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
497
                                           int mmu_idx);
498

    
499
#endif
500
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
501

    
502
#define cpu_init cpu_sparc_init
503
#define cpu_exec cpu_sparc_exec
504
#define cpu_gen_code cpu_sparc_gen_code
505
#define cpu_signal_handler cpu_sparc_signal_handler
506
#define cpu_list sparc_cpu_list
507

    
508
#define CPU_SAVE_VERSION 6
509

    
510
/* MMU modes definitions */
511
#define MMU_MODE0_SUFFIX _user
512
#define MMU_MODE1_SUFFIX _kernel
513
#ifdef TARGET_SPARC64
514
#define MMU_MODE2_SUFFIX _hypv
515
#define MMU_MODE3_SUFFIX _nucleus
516
#define MMU_MODE4_SUFFIX _user_secondary
517
#define MMU_MODE5_SUFFIX _kernel_secondary
518
#endif
519
#define MMU_USER_IDX   0
520
#define MMU_KERNEL_IDX 1
521
#define MMU_HYPV_IDX   2
522
#ifdef TARGET_SPARC64
523
#define MMU_NUCLEUS_IDX 3
524
#define MMU_USER_SECONDARY_IDX   4
525
#define MMU_KERNEL_SECONDARY_IDX 5
526
#endif
527

    
528
static inline int cpu_mmu_index(CPUState *env1)
529
{
530
#if defined(CONFIG_USER_ONLY)
531
    return MMU_USER_IDX;
532
#elif !defined(TARGET_SPARC64)
533
    return env1->psrs;
534
#else
535
    if (!env1->psrs)
536
        return MMU_USER_IDX;
537
    else if ((env1->hpstate & HS_PRIV) == 0)
538
        return MMU_KERNEL_IDX;
539
    else
540
        return MMU_HYPV_IDX;
541
#endif
542
}
543

    
544
static inline int cpu_interrupts_enabled(CPUState *env1)
545
{
546
#if !defined (TARGET_SPARC64)
547
    if (env1->psret != 0)
548
        return 1;
549
#else
550
    if (env1->pstate & PS_IE)
551
        return 1;
552
#endif
553

    
554
    return 0;
555
}
556

    
557
static inline int cpu_pil_allowed(CPUState *env1, int pil)
558
{
559
#if !defined(TARGET_SPARC64)
560
    /* level 15 is non-maskable on sparc v8 */
561
    return pil == 15 || pil > env1->psrpil;
562
#else
563
    return pil > env1->psrpil;
564
#endif
565
}
566

    
567
static inline int cpu_fpu_enabled(CPUState *env1)
568
{
569
#if defined(CONFIG_USER_ONLY)
570
    return 1;
571
#elif !defined(TARGET_SPARC64)
572
    return env1->psref;
573
#else
574
    return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
575
#endif
576
}
577

    
578
#if defined(CONFIG_USER_ONLY)
579
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
580
{
581
    if (newsp)
582
        env->regwptr[22] = newsp;
583
    env->regwptr[0] = 0;
584
    /* FIXME: Do we also need to clear CF?  */
585
    /* XXXXX */
586
    printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
587
}
588
#endif
589

    
590
#include "cpu-all.h"
591
#include "exec-all.h"
592

    
593
#ifdef TARGET_SPARC64
594
/* sun4u.c */
595
void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
596
uint64_t cpu_tick_get_count(CPUTimer *timer);
597
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
598
trap_state* cpu_tsptr(CPUState* env);
599
#endif
600

    
601
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
602
{
603
    env->pc = tb->pc;
604
    env->npc = tb->cs_base;
605
}
606

    
607
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
608
                                        target_ulong *cs_base, int *flags)
609
{
610
    *pc = env->pc;
611
    *cs_base = env->npc;
612
#ifdef TARGET_SPARC64
613
    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
614
    *flags = ((env->pstate & PS_AM) << 2)
615
        | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
616
        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
617
#else
618
    // FPU enable . Supervisor
619
    *flags = (env->psref << 4) | env->psrs;
620
#endif
621
}
622

    
623
#endif