Archipelago » qemu

 * In addition to Crystal CS4231 there is a DMA controller on Sparc.

 */

#define CS_MAXADDR 0x3f

#define CS_REGS 16

#define CS_DREGS 32

#define CS_MAXDREG (CS_DREGS - 1)

        return;

    cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);

    register_savevm("cs4231", base, 1, cs_save, cs_load, s);

    qemu_register_reset(cs_reset, s);

    cs_reset(s);

#define DPRINTF(fmt, args...)

#endif

#define TI_BUFSZ 32

/* The HBA is ID 7, so for simplicitly limit to 7 devices.  */

#define ESP_MAX_DEVS      7

struct ESPState {

    BlockDriverState **bd;

    int32_t ti_size;

    uint32_t ti_rptr, ti_wptr;

    uint8_t ti_buf[TI_BUFSZ];

    }

}

{

    ESPState *s = opaque;

    s->rregs[0x0e] = 0x4; // Indicate fas100a

    s->ti_size = 0;

    s->ti_rptr = 0;

    ESPState *s = opaque;

    uint32_t saddr;

    DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);

    switch (saddr) {

    case 2:

    ESPState *s = opaque;

    uint32_t saddr;

    DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);

    switch (saddr) {

    case 0:

{

    ESPState *s = opaque;

    qemu_put_be32s(f, &s->ti_size);

    qemu_put_be32s(f, &s->ti_rptr);

    qemu_put_be32s(f, &s->ti_wptr);

    if (version_id != 3)

        return -EINVAL; // Cannot emulate 2

    qemu_get_be32s(f, &s->ti_size);

    qemu_get_be32s(f, &s->ti_rptr);

    qemu_get_be32s(f, &s->ti_wptr);

    s->bd = bd;

    s->dma_opaque = dma_opaque;

    esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);

    esp_reset(s);

    return val;

}

{

    PCNetState *s = opaque;

    int i;

        cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);

    d->dma_opaque = dma_opaque;

    cpu_register_physical_memory(leaddr, 4, lance_io_memory);

    d->irq = irq;

} SLAVIO_INTCTLState;

#define INTCTL_MAXADDR 0xf

#define INTCTLM_MAXADDR 0x13

#define INTCTLM_MASK 0x1f

static void slavio_check_interrupts(void *opaque);

    s->intbit_to_level = intbit_to_level;

    for (i = 0; i < MAX_CPUS; i++) {

	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);

    }

    slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);

    qemu_register_reset(slavio_intctl_reset, s);

    uint8_t diag, mctrl, sysctrl;

} MiscState;

static void slavio_misc_update_irq(void *opaque)

{

    slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);

    // Slavio control

    // AUX 1

    // AUX 2

    // Diagnostics

    // Modem control

    // System control

    // Power management

    s->irq = irq;

};

#define SERIAL_MAXADDR 7

static void handle_kbd_command(ChannelState *s, int val);

static int serial_can_receive(void *opaque);

    int i;

    s->reg = 0;

	s->rregs[i] = 0;

	s->wregs[i] = 0;

    }

        return NULL;

    slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);

    s->chn[0].chr = chr1;

    s->chn[1].chr = chr2;

    s->chn[1].type = kbd;

    slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);

    qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, "QEMU Sun Mouse");

    qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);

} SLAVIO_TIMERState;

#define TIMER_MAXADDR 0x1f

// Update count, set irq, update expire_time

// Convert from ptimer countdown units

    slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,

						    slavio_timer_mem_write, s);

    register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);

    qemu_register_reset(slavio_timer_reset, s);

    slavio_timer_reset(s);

#define DPRINTF(fmt, args...)

#endif

#define DMA_VER 0xa0000000

#define DMA_INTR 1

#define DMA_INTREN 0x10

#define DMA_WRITE_MEM 0x100

#define DMA_LOADED 0x04000000

#define DMA_RESET 0x80

typedef struct DMAState DMAState;

struct DMAState {

    uint32_t dmaregs[DMA_REGS];

    qemu_irq *pic;

};

    DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",

            s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);

    if (do_bswap) {

        sparc_iommu_memory_read(s->iommu, addr, buf, len);

    } else {

    DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",

            s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);

    if (do_bswap) {

        sparc_iommu_memory_write(s->iommu, addr, buf, len);

    } else {

    DPRINTF("Raise ESP IRQ\n");

    s->dmaregs[0] |= DMA_INTR;

}

void espdma_clear_irq(void *opaque)

    s->dmaregs[0] &= ~DMA_INTR;

    DPRINTF("Lower ESP IRQ\n");

}

void espdma_memory_read(void *opaque, uint8_t *buf, int len)

    uint32_t saddr;

    saddr = (addr & DMA_MAXADDR) >> 2;

    return s->dmaregs[saddr];

}

    uint32_t saddr;

    saddr = (addr & DMA_MAXADDR) >> 2;

    switch (saddr) {

    case 0:

        if (!(val & DMA_INTREN)) {

        }

        if (val & DMA_RESET) {

        } else if (val == 0)

        val &= 0x0fffffff;

        val |= DMA_VER;

        break;

    case 1:

        s->dmaregs[0] |= DMA_LOADED;

        break;

    default:

        break;

    }

{

    DMAState *s = opaque;

    s->dmaregs[0] = DMA_VER;

}

static void dma_save(QEMUFile *f, void *opaque)

    DMAState *s = opaque;

    unsigned int i;

        return -EINVAL;

    for (i = 0; i < DMA_REGS; i++)

        qemu_get_be32s(f, &s->dmaregs[i]);

    return 0;

}

{

    DMAState *s;

    int dma_io_memory;

    if (!s)

        return NULL;

    s->iommu = iommu;

    dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);

    qemu_register_reset(dma_reset, s);

    return s;

}

{

    DMAState *s = opaque;

}

{

    CPUState *env, *envs[MAX_CPUS];

    unsigned int i;

    const sparc_def_t *def;

    qemu_irq *slavio_irq;

    for(i = 0; i < smp_cpus; i++) {

        slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);

    }

    if (graphic_depth != 8 && graphic_depth != 24) {

        fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);

    if (nd_table[0].vlan) {

        if (nd_table[0].model == NULL

            || strcmp(nd_table[0].model, "lance") == 0) {

                                    slavio_irq[hwdef->le_irq]);

        } else {

            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);

    slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],

                       serial_hds[1], serial_hds[0]);

    fdctrl_init(slavio_irq[hwdef->fd_irq], 0, 1, hwdef->fd_base, fd_table);

    for (i = 0; i < MAX_DISKS; i++) {

        if (bs_table[i]) {

                                   slavio_irq[hwdef->me_irq]);

    if (hwdef->cs_base != (target_phys_addr_t)-1)

        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);

}

static void sun4m_load_kernel(long vram_size, int ram_size, int boot_device,

/* pcnet.c */

void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);

void *lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,

                 qemu_irq irq);

void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);

void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,

               void *dma_opaque);

/* sparc32_dma.c */

void ledma_set_irq(void *opaque, int isr);

void ledma_memory_read(void *opaque, target_phys_addr_t addr, 

                       uint8_t *buf, int len, int do_bswap);

void espdma_clear_irq(void *opaque);

void espdma_memory_read(void *opaque, uint8_t *buf, int len);

void espdma_memory_write(void *opaque, uint8_t *buf, int len);

/* cs4231.c */

void cs_init(target_phys_addr_t base, int irq, void *intctl);