Revision 5aca8c3b hw/cs4231.c

b/hw/cs4231.c
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 * In addition to Crystal CS4231 there is a DMA controller on Sparc.
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 */
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#define CS_MAXADDR 0x3f
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#define CS_SIZE (CS_MAXADDR + 1)
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#define CS_REGS 16
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#define CS_DREGS 32
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#define CS_MAXDREG (CS_DREGS - 1)
......
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        return;
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    cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);


  		





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    cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);


  		





  
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    cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);


  		





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    register_savevm("cs4231", base, 1, cs_save, cs_load, s);


  		





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    qemu_register_reset(cs_reset, s);


  		





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    cs_reset(s);


  		












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