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root / target-i386 @ 5af45186

Name Size
cpu.h 21.2 kB
exec.h 13.9 kB
helper.c 131.8 kB
helper.h 383 Bytes
helper2.c 39.2 kB
machine.c 7 kB
op.c 38.9 kB
opreg_template.h 1.4 kB
ops_sse.h 34 kB
ops_sse_header.h 8.3 kB
ops_template.h 13 kB
ops_template_mem.h 10.6 kB
svm.h 10.4 kB
translate.c 212.5 kB

Latest revisions

# Date Author Comment
5af45186 05/12/2008 07:47 pm bellard

converted SSE/MMX ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162

8686c490 05/12/2008 04:55 pm bellard

use TCG for MMX/SSE memory accesses

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4439 c046a42c-6fe2-441c-8c8c-71466251a162

75d28b05 05/12/2008 03:08 pm bellard

char is only for strings

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4436 c046a42c-6fe2-441c-8c8c-71466251a162

edea5f01 05/10/2008 02:01 pm bellard

no need to define global registers in cpu-exec.c

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4409 c046a42c-6fe2-441c-8c8c-71466251a162

7caa33f7 05/04/2008 11:11 pm aurel32

Correctly save and restore env->a20_mask now that it is a 64-bit
variable. Noticed by Erik de Castro Lopo.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4334 c046a42c-6fe2-441c-8c8c-71466251a162

8dd3dca3 05/04/2008 04:11 pm aurel32

remove target ifdefs from vl.c

(Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162

d2856f1a 04/28/2008 03:32 am aurel32

Factorize code in translate.c

(Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162

00f82b8a 04/28/2008 12:12 am aurel32

Use correct types to enable > 2G support, based on a patch from
Anthony Liguori.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4265 c046a42c-6fe2-441c-8c8c-71466251a162

a23a663b 04/23/2008 12:57 am aurel32

Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
long. Thanks to Paul Brook for noticing that.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4242 c046a42c-6fe2-441c-8c8c-71466251a162

0ba5f006 04/22/2008 11:37 pm aurel32

x86/x86-64 MMU PAE fixes

This patch fixes MMU emulation in PAE mode for > 4GB physical addresses:
- a20_mask should have the correct size to not clear the high part of
the addresses.
- PHYS_ADDR_MASK should not clear the high part of the addresses.
- pdpe, pde and pte could be located anywhere in memory on x86-64, but...

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