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1 | dec9c2d4 | Andreas Färber | /*
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2 | dec9c2d4 | Andreas Färber | * QEMU ARM CPU
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3 | dec9c2d4 | Andreas Färber | *
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4 | dec9c2d4 | Andreas Färber | * Copyright (c) 2012 SUSE LINUX Products GmbH
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5 | dec9c2d4 | Andreas Färber | *
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6 | dec9c2d4 | Andreas Färber | * This program is free software; you can redistribute it and/or
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7 | dec9c2d4 | Andreas Färber | * modify it under the terms of the GNU General Public License
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8 | dec9c2d4 | Andreas Färber | * as published by the Free Software Foundation; either version 2
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9 | dec9c2d4 | Andreas Färber | * of the License, or (at your option) any later version.
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10 | dec9c2d4 | Andreas Färber | *
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11 | dec9c2d4 | Andreas Färber | * This program is distributed in the hope that it will be useful,
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12 | dec9c2d4 | Andreas Färber | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | dec9c2d4 | Andreas Färber | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | dec9c2d4 | Andreas Färber | * GNU General Public License for more details.
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15 | dec9c2d4 | Andreas Färber | *
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16 | dec9c2d4 | Andreas Färber | * You should have received a copy of the GNU General Public License
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17 | dec9c2d4 | Andreas Färber | * along with this program; if not, see
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18 | dec9c2d4 | Andreas Färber | * <http://www.gnu.org/licenses/gpl-2.0.html>
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19 | dec9c2d4 | Andreas Färber | */
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20 | dec9c2d4 | Andreas Färber | |
21 | 778c3a06 | Andreas Färber | #include "cpu.h" |
22 | dec9c2d4 | Andreas Färber | #include "qemu-common.h" |
23 | 3c30dd5a | Peter Maydell | #if !defined(CONFIG_USER_ONLY)
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24 | 3c30dd5a | Peter Maydell | #include "hw/loader.h" |
25 | 3c30dd5a | Peter Maydell | #endif
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26 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
27 | dec9c2d4 | Andreas Färber | |
28 | f45748f1 | Andreas Färber | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
29 | f45748f1 | Andreas Färber | { |
30 | f45748f1 | Andreas Färber | ARMCPU *cpu = ARM_CPU(cs); |
31 | f45748f1 | Andreas Färber | |
32 | f45748f1 | Andreas Färber | cpu->env.regs[15] = value;
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33 | f45748f1 | Andreas Färber | } |
34 | f45748f1 | Andreas Färber | |
35 | 4b6a83fb | Peter Maydell | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
36 | 4b6a83fb | Peter Maydell | { |
37 | 4b6a83fb | Peter Maydell | /* Reset a single ARMCPRegInfo register */
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38 | 4b6a83fb | Peter Maydell | ARMCPRegInfo *ri = value; |
39 | 4b6a83fb | Peter Maydell | ARMCPU *cpu = opaque; |
40 | 4b6a83fb | Peter Maydell | |
41 | 4b6a83fb | Peter Maydell | if (ri->type & ARM_CP_SPECIAL) {
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42 | 4b6a83fb | Peter Maydell | return;
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43 | 4b6a83fb | Peter Maydell | } |
44 | 4b6a83fb | Peter Maydell | |
45 | 4b6a83fb | Peter Maydell | if (ri->resetfn) {
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46 | 4b6a83fb | Peter Maydell | ri->resetfn(&cpu->env, ri); |
47 | 4b6a83fb | Peter Maydell | return;
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48 | 4b6a83fb | Peter Maydell | } |
49 | 4b6a83fb | Peter Maydell | |
50 | 4b6a83fb | Peter Maydell | /* A zero offset is never possible as it would be regs[0]
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51 | 4b6a83fb | Peter Maydell | * so we use it to indicate that reset is being handled elsewhere.
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52 | 4b6a83fb | Peter Maydell | * This is basically only used for fields in non-core coprocessors
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53 | 4b6a83fb | Peter Maydell | * (like the pxa2xx ones).
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54 | 4b6a83fb | Peter Maydell | */
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55 | 4b6a83fb | Peter Maydell | if (!ri->fieldoffset) {
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56 | 4b6a83fb | Peter Maydell | return;
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57 | 4b6a83fb | Peter Maydell | } |
58 | 4b6a83fb | Peter Maydell | |
59 | 4b6a83fb | Peter Maydell | if (ri->type & ARM_CP_64BIT) {
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60 | 4b6a83fb | Peter Maydell | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
61 | 4b6a83fb | Peter Maydell | } else {
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62 | 4b6a83fb | Peter Maydell | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; |
63 | 4b6a83fb | Peter Maydell | } |
64 | 4b6a83fb | Peter Maydell | } |
65 | 4b6a83fb | Peter Maydell | |
66 | dec9c2d4 | Andreas Färber | /* CPUClass::reset() */
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67 | dec9c2d4 | Andreas Färber | static void arm_cpu_reset(CPUState *s) |
68 | dec9c2d4 | Andreas Färber | { |
69 | dec9c2d4 | Andreas Färber | ARMCPU *cpu = ARM_CPU(s); |
70 | dec9c2d4 | Andreas Färber | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); |
71 | 3c30dd5a | Peter Maydell | CPUARMState *env = &cpu->env; |
72 | 3c30dd5a | Peter Maydell | |
73 | dec9c2d4 | Andreas Färber | acc->parent_reset(s); |
74 | dec9c2d4 | Andreas Färber | |
75 | 3c30dd5a | Peter Maydell | memset(env, 0, offsetof(CPUARMState, breakpoints));
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76 | 4b6a83fb | Peter Maydell | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
77 | 3c30dd5a | Peter Maydell | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
78 | 3c30dd5a | Peter Maydell | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |
79 | 3c30dd5a | Peter Maydell | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
80 | 3c30dd5a | Peter Maydell | |
81 | 3c30dd5a | Peter Maydell | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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82 | 3c30dd5a | Peter Maydell | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
83 | 3c30dd5a | Peter Maydell | } |
84 | 3c30dd5a | Peter Maydell | |
85 | 3c30dd5a | Peter Maydell | #if defined(CONFIG_USER_ONLY)
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86 | 3c30dd5a | Peter Maydell | env->uncached_cpsr = ARM_CPU_MODE_USR; |
87 | 3c30dd5a | Peter Maydell | /* For user mode we must enable access to coprocessors */
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88 | 3c30dd5a | Peter Maydell | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
89 | 3c30dd5a | Peter Maydell | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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90 | 3c30dd5a | Peter Maydell | env->cp15.c15_cpar = 3;
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91 | 3c30dd5a | Peter Maydell | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
92 | 3c30dd5a | Peter Maydell | env->cp15.c15_cpar = 1;
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93 | 3c30dd5a | Peter Maydell | } |
94 | 3c30dd5a | Peter Maydell | #else
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95 | 3c30dd5a | Peter Maydell | /* SVC mode with interrupts disabled. */
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96 | 3c30dd5a | Peter Maydell | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
97 | 3c30dd5a | Peter Maydell | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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98 | 3c30dd5a | Peter Maydell | clear at reset. Initial SP and PC are loaded from ROM. */
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99 | 3c30dd5a | Peter Maydell | if (IS_M(env)) {
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100 | 3c30dd5a | Peter Maydell | uint32_t pc; |
101 | 3c30dd5a | Peter Maydell | uint8_t *rom; |
102 | 3c30dd5a | Peter Maydell | env->uncached_cpsr &= ~CPSR_I; |
103 | 3c30dd5a | Peter Maydell | rom = rom_ptr(0);
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104 | 3c30dd5a | Peter Maydell | if (rom) {
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105 | 3c30dd5a | Peter Maydell | /* We should really use ldl_phys here, in case the guest
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106 | 3c30dd5a | Peter Maydell | modified flash and reset itself. However images
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107 | 3c30dd5a | Peter Maydell | loaded via -kernel have not been copied yet, so load the
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108 | 3c30dd5a | Peter Maydell | values directly from there. */
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109 | 3c30dd5a | Peter Maydell | env->regs[13] = ldl_p(rom);
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110 | 3c30dd5a | Peter Maydell | pc = ldl_p(rom + 4);
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111 | 3c30dd5a | Peter Maydell | env->thumb = pc & 1;
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112 | 3c30dd5a | Peter Maydell | env->regs[15] = pc & ~1; |
113 | 3c30dd5a | Peter Maydell | } |
114 | 3c30dd5a | Peter Maydell | } |
115 | 3c30dd5a | Peter Maydell | env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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116 | 3c30dd5a | Peter Maydell | #endif
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117 | 3c30dd5a | Peter Maydell | set_flush_to_zero(1, &env->vfp.standard_fp_status);
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118 | 3c30dd5a | Peter Maydell | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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119 | 3c30dd5a | Peter Maydell | set_default_nan_mode(1, &env->vfp.standard_fp_status);
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120 | 3c30dd5a | Peter Maydell | set_float_detect_tininess(float_tininess_before_rounding, |
121 | 3c30dd5a | Peter Maydell | &env->vfp.fp_status); |
122 | 3c30dd5a | Peter Maydell | set_float_detect_tininess(float_tininess_before_rounding, |
123 | 3c30dd5a | Peter Maydell | &env->vfp.standard_fp_status); |
124 | 3c30dd5a | Peter Maydell | tlb_flush(env, 1);
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125 | 3c30dd5a | Peter Maydell | /* Reset is a state change for some CPUARMState fields which we
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126 | 3c30dd5a | Peter Maydell | * bake assumptions about into translated code, so we need to
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127 | 3c30dd5a | Peter Maydell | * tb_flush().
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128 | 3c30dd5a | Peter Maydell | */
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129 | 3c30dd5a | Peter Maydell | tb_flush(env); |
130 | dec9c2d4 | Andreas Färber | } |
131 | dec9c2d4 | Andreas Färber | |
132 | 581be094 | Peter Maydell | static inline void set_feature(CPUARMState *env, int feature) |
133 | 581be094 | Peter Maydell | { |
134 | 918f5dca | Peter Maydell | env->features |= 1ULL << feature;
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135 | 581be094 | Peter Maydell | } |
136 | 581be094 | Peter Maydell | |
137 | 777dc784 | Peter Maydell | static void arm_cpu_initfn(Object *obj) |
138 | 777dc784 | Peter Maydell | { |
139 | c05efcb1 | Andreas Färber | CPUState *cs = CPU(obj); |
140 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
141 | 79614b78 | Andreas Färber | static bool inited; |
142 | 777dc784 | Peter Maydell | |
143 | c05efcb1 | Andreas Färber | cs->env_ptr = &cpu->env; |
144 | 777dc784 | Peter Maydell | cpu_exec_init(&cpu->env); |
145 | 4b6a83fb | Peter Maydell | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
146 | 4b6a83fb | Peter Maydell | g_free, g_free); |
147 | 79614b78 | Andreas Färber | |
148 | 79614b78 | Andreas Färber | if (tcg_enabled() && !inited) {
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149 | 79614b78 | Andreas Färber | inited = true;
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150 | 79614b78 | Andreas Färber | arm_translate_init(); |
151 | 79614b78 | Andreas Färber | } |
152 | 4b6a83fb | Peter Maydell | } |
153 | 4b6a83fb | Peter Maydell | |
154 | 4b6a83fb | Peter Maydell | static void arm_cpu_finalizefn(Object *obj) |
155 | 4b6a83fb | Peter Maydell | { |
156 | 4b6a83fb | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
157 | 4b6a83fb | Peter Maydell | g_hash_table_destroy(cpu->cp_regs); |
158 | 777dc784 | Peter Maydell | } |
159 | 777dc784 | Peter Maydell | |
160 | 14969266 | Andreas Färber | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
161 | 581be094 | Peter Maydell | { |
162 | 14969266 | Andreas Färber | ARMCPU *cpu = ARM_CPU(dev); |
163 | 14969266 | Andreas Färber | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); |
164 | 581be094 | Peter Maydell | CPUARMState *env = &cpu->env; |
165 | 14969266 | Andreas Färber | |
166 | 581be094 | Peter Maydell | /* Some features automatically imply others: */
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167 | 81e69fb0 | Mans Rullgard | if (arm_feature(env, ARM_FEATURE_V8)) {
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168 | 81e69fb0 | Mans Rullgard | set_feature(env, ARM_FEATURE_V7); |
169 | 81e69fb0 | Mans Rullgard | set_feature(env, ARM_FEATURE_ARM_DIV); |
170 | 81e69fb0 | Mans Rullgard | set_feature(env, ARM_FEATURE_LPAE); |
171 | 81e69fb0 | Mans Rullgard | } |
172 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_V7)) {
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173 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_VAPA); |
174 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_THUMB2); |
175 | 81bdde9d | Peter Maydell | set_feature(env, ARM_FEATURE_MPIDR); |
176 | 581be094 | Peter Maydell | if (!arm_feature(env, ARM_FEATURE_M)) {
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177 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_V6K); |
178 | 581be094 | Peter Maydell | } else {
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179 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_V6); |
180 | 581be094 | Peter Maydell | } |
181 | 581be094 | Peter Maydell | } |
182 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_V6K)) {
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183 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_V6); |
184 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_MVFR); |
185 | 581be094 | Peter Maydell | } |
186 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_V6)) {
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187 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_V5); |
188 | 581be094 | Peter Maydell | if (!arm_feature(env, ARM_FEATURE_M)) {
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189 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_AUXCR); |
190 | 581be094 | Peter Maydell | } |
191 | 581be094 | Peter Maydell | } |
192 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_V5)) {
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193 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_V4T); |
194 | 581be094 | Peter Maydell | } |
195 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_M)) {
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196 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_THUMB_DIV); |
197 | 581be094 | Peter Maydell | } |
198 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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199 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_THUMB_DIV); |
200 | 581be094 | Peter Maydell | } |
201 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_VFP4)) {
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202 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_VFP3); |
203 | 581be094 | Peter Maydell | } |
204 | 581be094 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_VFP3)) {
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205 | 581be094 | Peter Maydell | set_feature(env, ARM_FEATURE_VFP); |
206 | 581be094 | Peter Maydell | } |
207 | de9b05b8 | Peter Maydell | if (arm_feature(env, ARM_FEATURE_LPAE)) {
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208 | bdcc150d | Peter Maydell | set_feature(env, ARM_FEATURE_V7MP); |
209 | de9b05b8 | Peter Maydell | set_feature(env, ARM_FEATURE_PXN); |
210 | de9b05b8 | Peter Maydell | } |
211 | 2ceb98c0 | Peter Maydell | |
212 | 2ceb98c0 | Peter Maydell | register_cp_regs_for_features(cpu); |
213 | 14969266 | Andreas Färber | arm_cpu_register_gdb_regs_for_features(cpu); |
214 | 14969266 | Andreas Färber | |
215 | 721fae12 | Peter Maydell | init_cpreg_list(cpu); |
216 | 721fae12 | Peter Maydell | |
217 | 14969266 | Andreas Färber | cpu_reset(CPU(cpu)); |
218 | 14969266 | Andreas Färber | |
219 | 14969266 | Andreas Färber | acc->parent_realize(dev, errp); |
220 | 581be094 | Peter Maydell | } |
221 | 581be094 | Peter Maydell | |
222 | 777dc784 | Peter Maydell | /* CPU models */
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223 | 777dc784 | Peter Maydell | |
224 | 5900d6b2 | Andreas Färber | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
225 | 5900d6b2 | Andreas Färber | { |
226 | 5900d6b2 | Andreas Färber | ObjectClass *oc; |
227 | 51492fd1 | Andreas Färber | char *typename;
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228 | 5900d6b2 | Andreas Färber | |
229 | 5900d6b2 | Andreas Färber | if (!cpu_model) {
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230 | 5900d6b2 | Andreas Färber | return NULL; |
231 | 5900d6b2 | Andreas Färber | } |
232 | 5900d6b2 | Andreas Färber | |
233 | 51492fd1 | Andreas Färber | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
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234 | 51492fd1 | Andreas Färber | oc = object_class_by_name(typename); |
235 | 51492fd1 | Andreas Färber | g_free(typename); |
236 | 245fb54d | Andreas Färber | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
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237 | 245fb54d | Andreas Färber | object_class_is_abstract(oc)) { |
238 | 5900d6b2 | Andreas Färber | return NULL; |
239 | 5900d6b2 | Andreas Färber | } |
240 | 5900d6b2 | Andreas Färber | return oc;
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241 | 5900d6b2 | Andreas Färber | } |
242 | 5900d6b2 | Andreas Färber | |
243 | 777dc784 | Peter Maydell | static void arm926_initfn(Object *obj) |
244 | 777dc784 | Peter Maydell | { |
245 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
246 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
247 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP); |
248 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
249 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
250 | b2d06f96 | Peter Maydell | cpu->midr = 0x41069265;
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251 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x41011090;
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252 | 64e1671f | Peter Maydell | cpu->ctr = 0x1dd20d2;
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253 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00090078;
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254 | 777dc784 | Peter Maydell | } |
255 | 777dc784 | Peter Maydell | |
256 | 777dc784 | Peter Maydell | static void arm946_initfn(Object *obj) |
257 | 777dc784 | Peter Maydell | { |
258 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
259 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
260 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_MPU); |
261 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
262 | b2d06f96 | Peter Maydell | cpu->midr = 0x41059461;
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263 | 64e1671f | Peter Maydell | cpu->ctr = 0x0f004006;
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264 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
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265 | 777dc784 | Peter Maydell | } |
266 | 777dc784 | Peter Maydell | |
267 | 777dc784 | Peter Maydell | static void arm1026_initfn(Object *obj) |
268 | 777dc784 | Peter Maydell | { |
269 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
270 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
271 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP); |
272 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
273 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
274 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
275 | b2d06f96 | Peter Maydell | cpu->midr = 0x4106a262;
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276 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410110a0;
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277 | 64e1671f | Peter Maydell | cpu->ctr = 0x1dd20d2;
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278 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00090078;
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279 | 2771db27 | Peter Maydell | cpu->reset_auxcr = 1;
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280 | 06d76f31 | Peter Maydell | { |
281 | 06d76f31 | Peter Maydell | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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282 | 06d76f31 | Peter Maydell | ARMCPRegInfo ifar = { |
283 | 06d76f31 | Peter Maydell | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
284 | 06d76f31 | Peter Maydell | .access = PL1_RW, |
285 | 06d76f31 | Peter Maydell | .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
286 | 06d76f31 | Peter Maydell | .resetvalue = 0
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287 | 06d76f31 | Peter Maydell | }; |
288 | 06d76f31 | Peter Maydell | define_one_arm_cp_reg(cpu, &ifar); |
289 | 06d76f31 | Peter Maydell | } |
290 | 777dc784 | Peter Maydell | } |
291 | 777dc784 | Peter Maydell | |
292 | 777dc784 | Peter Maydell | static void arm1136_r2_initfn(Object *obj) |
293 | 777dc784 | Peter Maydell | { |
294 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
295 | 2e4d7e3e | Peter Maydell | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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296 | 2e4d7e3e | Peter Maydell | * older core than plain "arm1136". In particular this does not
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297 | 2e4d7e3e | Peter Maydell | * have the v6K features.
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298 | 2e4d7e3e | Peter Maydell | * These ID register values are correct for 1136 but may be wrong
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299 | 2e4d7e3e | Peter Maydell | * for 1136_r2 (in particular r0p2 does not actually implement most
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300 | 2e4d7e3e | Peter Maydell | * of the ID registers).
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301 | 2e4d7e3e | Peter Maydell | */
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302 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V6); |
303 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP); |
304 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
305 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
306 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
307 | b2d06f96 | Peter Maydell | cpu->midr = 0x4107b362;
|
308 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410120b4;
|
309 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x11111111;
|
310 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x00000000;
|
311 | 64e1671f | Peter Maydell | cpu->ctr = 0x1dd20d2;
|
312 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00050078;
|
313 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x111;
|
314 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x1;
|
315 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0x2;
|
316 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0x3;
|
317 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x01130003;
|
318 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x10030302;
|
319 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01222110;
|
320 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x00140011;
|
321 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x12002111;
|
322 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x11231111;
|
323 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x01102131;
|
324 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x141;
|
325 | 2771db27 | Peter Maydell | cpu->reset_auxcr = 7;
|
326 | 777dc784 | Peter Maydell | } |
327 | 777dc784 | Peter Maydell | |
328 | 777dc784 | Peter Maydell | static void arm1136_initfn(Object *obj) |
329 | 777dc784 | Peter Maydell | { |
330 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
331 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V6K); |
332 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V6); |
333 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP); |
334 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
335 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
336 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
337 | b2d06f96 | Peter Maydell | cpu->midr = 0x4117b363;
|
338 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410120b4;
|
339 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x11111111;
|
340 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x00000000;
|
341 | 64e1671f | Peter Maydell | cpu->ctr = 0x1dd20d2;
|
342 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00050078;
|
343 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x111;
|
344 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x1;
|
345 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0x2;
|
346 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0x3;
|
347 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x01130003;
|
348 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x10030302;
|
349 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01222110;
|
350 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x00140011;
|
351 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x12002111;
|
352 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x11231111;
|
353 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x01102131;
|
354 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x141;
|
355 | 2771db27 | Peter Maydell | cpu->reset_auxcr = 7;
|
356 | 777dc784 | Peter Maydell | } |
357 | 777dc784 | Peter Maydell | |
358 | 777dc784 | Peter Maydell | static void arm1176_initfn(Object *obj) |
359 | 777dc784 | Peter Maydell | { |
360 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
361 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V6K); |
362 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP); |
363 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VAPA); |
364 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
365 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
366 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
367 | b2d06f96 | Peter Maydell | cpu->midr = 0x410fb767;
|
368 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410120b5;
|
369 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x11111111;
|
370 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x00000000;
|
371 | 64e1671f | Peter Maydell | cpu->ctr = 0x1dd20d2;
|
372 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00050078;
|
373 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x111;
|
374 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x11;
|
375 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0x33;
|
376 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0;
|
377 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x01130003;
|
378 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x10030302;
|
379 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01222100;
|
380 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x0140011;
|
381 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x12002111;
|
382 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x11231121;
|
383 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x01102131;
|
384 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x01141;
|
385 | 2771db27 | Peter Maydell | cpu->reset_auxcr = 7;
|
386 | 777dc784 | Peter Maydell | } |
387 | 777dc784 | Peter Maydell | |
388 | 777dc784 | Peter Maydell | static void arm11mpcore_initfn(Object *obj) |
389 | 777dc784 | Peter Maydell | { |
390 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
391 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V6K); |
392 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP); |
393 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VAPA); |
394 | 81bdde9d | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
395 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
396 | b2d06f96 | Peter Maydell | cpu->midr = 0x410fb022;
|
397 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410120b4;
|
398 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x11111111;
|
399 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x00000000;
|
400 | 200bf596 | Peter Maydell | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
401 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x111;
|
402 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x1;
|
403 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0;
|
404 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0x2;
|
405 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x01100103;
|
406 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x10020302;
|
407 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01222000;
|
408 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x00100011;
|
409 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x12002111;
|
410 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x11221011;
|
411 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x01102131;
|
412 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x141;
|
413 | 2771db27 | Peter Maydell | cpu->reset_auxcr = 1;
|
414 | 777dc784 | Peter Maydell | } |
415 | 777dc784 | Peter Maydell | |
416 | 777dc784 | Peter Maydell | static void cortex_m3_initfn(Object *obj) |
417 | 777dc784 | Peter Maydell | { |
418 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
419 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V7); |
420 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_M); |
421 | b2d06f96 | Peter Maydell | cpu->midr = 0x410fc231;
|
422 | 777dc784 | Peter Maydell | } |
423 | 777dc784 | Peter Maydell | |
424 | e6f010cc | Andreas Färber | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
425 | e6f010cc | Andreas Färber | { |
426 | e6f010cc | Andreas Färber | #ifndef CONFIG_USER_ONLY
|
427 | e6f010cc | Andreas Färber | CPUClass *cc = CPU_CLASS(oc); |
428 | e6f010cc | Andreas Färber | |
429 | e6f010cc | Andreas Färber | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
430 | e6f010cc | Andreas Färber | #endif
|
431 | e6f010cc | Andreas Färber | } |
432 | e6f010cc | Andreas Färber | |
433 | 34f90529 | Peter Maydell | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
434 | 34f90529 | Peter Maydell | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, |
435 | 34f90529 | Peter Maydell | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
436 | 34f90529 | Peter Maydell | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
437 | 34f90529 | Peter Maydell | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
438 | 34f90529 | Peter Maydell | REGINFO_SENTINEL |
439 | 34f90529 | Peter Maydell | }; |
440 | 34f90529 | Peter Maydell | |
441 | 777dc784 | Peter Maydell | static void cortex_a8_initfn(Object *obj) |
442 | 777dc784 | Peter Maydell | { |
443 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
444 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V7); |
445 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP3); |
446 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_NEON); |
447 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
448 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
449 | b2d06f96 | Peter Maydell | cpu->midr = 0x410fc080;
|
450 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410330c0;
|
451 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x11110222;
|
452 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x00011100;
|
453 | 64e1671f | Peter Maydell | cpu->ctr = 0x82048004;
|
454 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00c50078;
|
455 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x1031;
|
456 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x11;
|
457 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0x400;
|
458 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0;
|
459 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x31100003;
|
460 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x20000000;
|
461 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01202000;
|
462 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr3 = 0x11;
|
463 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x00101111;
|
464 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x12112111;
|
465 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x21232031;
|
466 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x11112131;
|
467 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x00111142;
|
468 | 85df3786 | Peter Maydell | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
469 | 85df3786 | Peter Maydell | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
470 | 85df3786 | Peter Maydell | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
471 | 85df3786 | Peter Maydell | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
472 | 2771db27 | Peter Maydell | cpu->reset_auxcr = 2;
|
473 | 34f90529 | Peter Maydell | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
474 | 777dc784 | Peter Maydell | } |
475 | 777dc784 | Peter Maydell | |
476 | 1047b9d7 | Peter Maydell | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
477 | 1047b9d7 | Peter Maydell | /* power_control should be set to maximum latency. Again,
|
478 | 1047b9d7 | Peter Maydell | * default to 0 and set by private hook
|
479 | 1047b9d7 | Peter Maydell | */
|
480 | 1047b9d7 | Peter Maydell | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
481 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0,
|
482 | 1047b9d7 | Peter Maydell | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, |
483 | 1047b9d7 | Peter Maydell | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, |
484 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0,
|
485 | 1047b9d7 | Peter Maydell | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, |
486 | 1047b9d7 | Peter Maydell | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, |
487 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0,
|
488 | 1047b9d7 | Peter Maydell | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, |
489 | 1047b9d7 | Peter Maydell | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, |
490 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
491 | 1047b9d7 | Peter Maydell | /* TLB lockdown control */
|
492 | 1047b9d7 | Peter Maydell | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, |
493 | 1047b9d7 | Peter Maydell | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
494 | 1047b9d7 | Peter Maydell | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, |
495 | 1047b9d7 | Peter Maydell | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
496 | 1047b9d7 | Peter Maydell | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, |
497 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
498 | 1047b9d7 | Peter Maydell | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, |
499 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
500 | 1047b9d7 | Peter Maydell | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, |
501 | 1047b9d7 | Peter Maydell | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
502 | 1047b9d7 | Peter Maydell | REGINFO_SENTINEL |
503 | 1047b9d7 | Peter Maydell | }; |
504 | 1047b9d7 | Peter Maydell | |
505 | 777dc784 | Peter Maydell | static void cortex_a9_initfn(Object *obj) |
506 | 777dc784 | Peter Maydell | { |
507 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
508 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V7); |
509 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP3); |
510 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
511 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_NEON); |
512 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
513 | 581be094 | Peter Maydell | /* Note that A9 supports the MP extensions even for
|
514 | 581be094 | Peter Maydell | * A9UP and single-core A9MP (which are both different
|
515 | 581be094 | Peter Maydell | * and valid configurations; we don't model A9UP).
|
516 | 581be094 | Peter Maydell | */
|
517 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V7MP); |
518 | b2d06f96 | Peter Maydell | cpu->midr = 0x410fc090;
|
519 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x41033090;
|
520 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x11110222;
|
521 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x01111111;
|
522 | 64e1671f | Peter Maydell | cpu->ctr = 0x80038003;
|
523 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00c50078;
|
524 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x1031;
|
525 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x11;
|
526 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0x000;
|
527 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0;
|
528 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x00100103;
|
529 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x20000000;
|
530 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01230000;
|
531 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr3 = 0x00002111;
|
532 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x00101111;
|
533 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x13112111;
|
534 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x21232041;
|
535 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x11112131;
|
536 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x00111142;
|
537 | 85df3786 | Peter Maydell | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
538 | 85df3786 | Peter Maydell | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
539 | 85df3786 | Peter Maydell | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
540 | 1047b9d7 | Peter Maydell | { |
541 | 1047b9d7 | Peter Maydell | ARMCPRegInfo cbar = { |
542 | 1047b9d7 | Peter Maydell | .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, |
543 | 1047b9d7 | Peter Maydell | .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
|
544 | 1047b9d7 | Peter Maydell | .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) |
545 | 1047b9d7 | Peter Maydell | }; |
546 | 1047b9d7 | Peter Maydell | define_one_arm_cp_reg(cpu, &cbar); |
547 | 1047b9d7 | Peter Maydell | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
548 | 1047b9d7 | Peter Maydell | } |
549 | 777dc784 | Peter Maydell | } |
550 | 777dc784 | Peter Maydell | |
551 | 34f90529 | Peter Maydell | #ifndef CONFIG_USER_ONLY
|
552 | 34f90529 | Peter Maydell | static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
553 | 34f90529 | Peter Maydell | uint64_t *value) |
554 | 34f90529 | Peter Maydell | { |
555 | 34f90529 | Peter Maydell | /* Linux wants the number of processors from here.
|
556 | 34f90529 | Peter Maydell | * Might as well set the interrupt-controller bit too.
|
557 | 34f90529 | Peter Maydell | */
|
558 | 34f90529 | Peter Maydell | *value = ((smp_cpus - 1) << 24) | (1 << 23); |
559 | 34f90529 | Peter Maydell | return 0; |
560 | 34f90529 | Peter Maydell | } |
561 | 34f90529 | Peter Maydell | #endif
|
562 | 34f90529 | Peter Maydell | |
563 | 34f90529 | Peter Maydell | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { |
564 | 34f90529 | Peter Maydell | #ifndef CONFIG_USER_ONLY
|
565 | 34f90529 | Peter Maydell | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
566 | 34f90529 | Peter Maydell | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
567 | 34f90529 | Peter Maydell | .writefn = arm_cp_write_ignore, }, |
568 | 34f90529 | Peter Maydell | #endif
|
569 | 34f90529 | Peter Maydell | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, |
570 | 34f90529 | Peter Maydell | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
571 | 34f90529 | Peter Maydell | REGINFO_SENTINEL |
572 | 34f90529 | Peter Maydell | }; |
573 | 34f90529 | Peter Maydell | |
574 | 777dc784 | Peter Maydell | static void cortex_a15_initfn(Object *obj) |
575 | 777dc784 | Peter Maydell | { |
576 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
577 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V7); |
578 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
579 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
580 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_NEON); |
581 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
582 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
583 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
584 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
585 | de9b05b8 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
586 | b2d06f96 | Peter Maydell | cpu->midr = 0x412fc0f1;
|
587 | 325b3cef | Peter Maydell | cpu->reset_fpsid = 0x410430f0;
|
588 | bd35c355 | Peter Maydell | cpu->mvfr0 = 0x10110222;
|
589 | bd35c355 | Peter Maydell | cpu->mvfr1 = 0x11111111;
|
590 | 64e1671f | Peter Maydell | cpu->ctr = 0x8444c004;
|
591 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00c50078;
|
592 | 2e4d7e3e | Peter Maydell | cpu->id_pfr0 = 0x00001131;
|
593 | 2e4d7e3e | Peter Maydell | cpu->id_pfr1 = 0x00011011;
|
594 | 2e4d7e3e | Peter Maydell | cpu->id_dfr0 = 0x02010555;
|
595 | 2e4d7e3e | Peter Maydell | cpu->id_afr0 = 0x00000000;
|
596 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr0 = 0x10201105;
|
597 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr1 = 0x20000000;
|
598 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr2 = 0x01240000;
|
599 | 2e4d7e3e | Peter Maydell | cpu->id_mmfr3 = 0x02102211;
|
600 | 2e4d7e3e | Peter Maydell | cpu->id_isar0 = 0x02101110;
|
601 | 2e4d7e3e | Peter Maydell | cpu->id_isar1 = 0x13112111;
|
602 | 2e4d7e3e | Peter Maydell | cpu->id_isar2 = 0x21232041;
|
603 | 2e4d7e3e | Peter Maydell | cpu->id_isar3 = 0x11112131;
|
604 | 2e4d7e3e | Peter Maydell | cpu->id_isar4 = 0x10011142;
|
605 | 85df3786 | Peter Maydell | cpu->clidr = 0x0a200023;
|
606 | 85df3786 | Peter Maydell | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
607 | 85df3786 | Peter Maydell | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
608 | 85df3786 | Peter Maydell | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
609 | 34f90529 | Peter Maydell | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
610 | 777dc784 | Peter Maydell | } |
611 | 777dc784 | Peter Maydell | |
612 | 777dc784 | Peter Maydell | static void ti925t_initfn(Object *obj) |
613 | 777dc784 | Peter Maydell | { |
614 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
615 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V4T); |
616 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); |
617 | 777dc784 | Peter Maydell | cpu->midr = ARM_CPUID_TI925T; |
618 | 64e1671f | Peter Maydell | cpu->ctr = 0x5109149;
|
619 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000070;
|
620 | 777dc784 | Peter Maydell | } |
621 | 777dc784 | Peter Maydell | |
622 | 777dc784 | Peter Maydell | static void sa1100_initfn(Object *obj) |
623 | 777dc784 | Peter Maydell | { |
624 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
625 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
626 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
627 | b2d06f96 | Peter Maydell | cpu->midr = 0x4401A11B;
|
628 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000070;
|
629 | 777dc784 | Peter Maydell | } |
630 | 777dc784 | Peter Maydell | |
631 | 777dc784 | Peter Maydell | static void sa1110_initfn(Object *obj) |
632 | 777dc784 | Peter Maydell | { |
633 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
634 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
635 | c4804214 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
636 | b2d06f96 | Peter Maydell | cpu->midr = 0x6901B119;
|
637 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000070;
|
638 | 777dc784 | Peter Maydell | } |
639 | 777dc784 | Peter Maydell | |
640 | 777dc784 | Peter Maydell | static void pxa250_initfn(Object *obj) |
641 | 777dc784 | Peter Maydell | { |
642 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
643 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
644 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
645 | b2d06f96 | Peter Maydell | cpu->midr = 0x69052100;
|
646 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
647 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
648 | 777dc784 | Peter Maydell | } |
649 | 777dc784 | Peter Maydell | |
650 | 777dc784 | Peter Maydell | static void pxa255_initfn(Object *obj) |
651 | 777dc784 | Peter Maydell | { |
652 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
653 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
654 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
655 | b2d06f96 | Peter Maydell | cpu->midr = 0x69052d00;
|
656 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
657 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
658 | 777dc784 | Peter Maydell | } |
659 | 777dc784 | Peter Maydell | |
660 | 777dc784 | Peter Maydell | static void pxa260_initfn(Object *obj) |
661 | 777dc784 | Peter Maydell | { |
662 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
663 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
664 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
665 | b2d06f96 | Peter Maydell | cpu->midr = 0x69052903;
|
666 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
667 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
668 | 777dc784 | Peter Maydell | } |
669 | 777dc784 | Peter Maydell | |
670 | 777dc784 | Peter Maydell | static void pxa261_initfn(Object *obj) |
671 | 777dc784 | Peter Maydell | { |
672 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
673 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
674 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
675 | b2d06f96 | Peter Maydell | cpu->midr = 0x69052d05;
|
676 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
677 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
678 | 777dc784 | Peter Maydell | } |
679 | 777dc784 | Peter Maydell | |
680 | 777dc784 | Peter Maydell | static void pxa262_initfn(Object *obj) |
681 | 777dc784 | Peter Maydell | { |
682 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
683 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
684 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
685 | b2d06f96 | Peter Maydell | cpu->midr = 0x69052d06;
|
686 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
687 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
688 | 777dc784 | Peter Maydell | } |
689 | 777dc784 | Peter Maydell | |
690 | 777dc784 | Peter Maydell | static void pxa270a0_initfn(Object *obj) |
691 | 777dc784 | Peter Maydell | { |
692 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
693 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
694 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
695 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
696 | b2d06f96 | Peter Maydell | cpu->midr = 0x69054110;
|
697 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
698 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
699 | 777dc784 | Peter Maydell | } |
700 | 777dc784 | Peter Maydell | |
701 | 777dc784 | Peter Maydell | static void pxa270a1_initfn(Object *obj) |
702 | 777dc784 | Peter Maydell | { |
703 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
704 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
705 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
706 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
707 | b2d06f96 | Peter Maydell | cpu->midr = 0x69054111;
|
708 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
709 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
710 | 777dc784 | Peter Maydell | } |
711 | 777dc784 | Peter Maydell | |
712 | 777dc784 | Peter Maydell | static void pxa270b0_initfn(Object *obj) |
713 | 777dc784 | Peter Maydell | { |
714 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
715 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
716 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
717 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
718 | b2d06f96 | Peter Maydell | cpu->midr = 0x69054112;
|
719 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
720 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
721 | 777dc784 | Peter Maydell | } |
722 | 777dc784 | Peter Maydell | |
723 | 777dc784 | Peter Maydell | static void pxa270b1_initfn(Object *obj) |
724 | 777dc784 | Peter Maydell | { |
725 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
726 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
727 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
728 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
729 | b2d06f96 | Peter Maydell | cpu->midr = 0x69054113;
|
730 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
731 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
732 | 777dc784 | Peter Maydell | } |
733 | 777dc784 | Peter Maydell | |
734 | 777dc784 | Peter Maydell | static void pxa270c0_initfn(Object *obj) |
735 | 777dc784 | Peter Maydell | { |
736 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
737 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
738 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
739 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
740 | b2d06f96 | Peter Maydell | cpu->midr = 0x69054114;
|
741 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
742 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
743 | 777dc784 | Peter Maydell | } |
744 | 777dc784 | Peter Maydell | |
745 | 777dc784 | Peter Maydell | static void pxa270c5_initfn(Object *obj) |
746 | 777dc784 | Peter Maydell | { |
747 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
748 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V5); |
749 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
750 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
751 | b2d06f96 | Peter Maydell | cpu->midr = 0x69054117;
|
752 | 64e1671f | Peter Maydell | cpu->ctr = 0xd172172;
|
753 | 0ca7e01c | Peter Maydell | cpu->reset_sctlr = 0x00000078;
|
754 | 777dc784 | Peter Maydell | } |
755 | 777dc784 | Peter Maydell | |
756 | 777dc784 | Peter Maydell | static void arm_any_initfn(Object *obj) |
757 | 777dc784 | Peter Maydell | { |
758 | 777dc784 | Peter Maydell | ARMCPU *cpu = ARM_CPU(obj); |
759 | 81e69fb0 | Mans Rullgard | set_feature(&cpu->env, ARM_FEATURE_V8); |
760 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
761 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
762 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_NEON); |
763 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
764 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
765 | 581be094 | Peter Maydell | set_feature(&cpu->env, ARM_FEATURE_V7MP); |
766 | b2d06f96 | Peter Maydell | cpu->midr = 0xffffffff;
|
767 | 777dc784 | Peter Maydell | } |
768 | 777dc784 | Peter Maydell | |
769 | 777dc784 | Peter Maydell | typedef struct ARMCPUInfo { |
770 | 777dc784 | Peter Maydell | const char *name; |
771 | 777dc784 | Peter Maydell | void (*initfn)(Object *obj);
|
772 | e6f010cc | Andreas Färber | void (*class_init)(ObjectClass *oc, void *data); |
773 | 777dc784 | Peter Maydell | } ARMCPUInfo; |
774 | 777dc784 | Peter Maydell | |
775 | 777dc784 | Peter Maydell | static const ARMCPUInfo arm_cpus[] = { |
776 | 777dc784 | Peter Maydell | { .name = "arm926", .initfn = arm926_initfn },
|
777 | 777dc784 | Peter Maydell | { .name = "arm946", .initfn = arm946_initfn },
|
778 | 777dc784 | Peter Maydell | { .name = "arm1026", .initfn = arm1026_initfn },
|
779 | 777dc784 | Peter Maydell | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
780 | 777dc784 | Peter Maydell | * older core than plain "arm1136". In particular this does not
|
781 | 777dc784 | Peter Maydell | * have the v6K features.
|
782 | 777dc784 | Peter Maydell | */
|
783 | 777dc784 | Peter Maydell | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
784 | 777dc784 | Peter Maydell | { .name = "arm1136", .initfn = arm1136_initfn },
|
785 | 777dc784 | Peter Maydell | { .name = "arm1176", .initfn = arm1176_initfn },
|
786 | 777dc784 | Peter Maydell | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
787 | e6f010cc | Andreas Färber | { .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
788 | e6f010cc | Andreas Färber | .class_init = arm_v7m_class_init }, |
789 | 777dc784 | Peter Maydell | { .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
790 | 777dc784 | Peter Maydell | { .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
791 | 777dc784 | Peter Maydell | { .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
792 | 777dc784 | Peter Maydell | { .name = "ti925t", .initfn = ti925t_initfn },
|
793 | 777dc784 | Peter Maydell | { .name = "sa1100", .initfn = sa1100_initfn },
|
794 | 777dc784 | Peter Maydell | { .name = "sa1110", .initfn = sa1110_initfn },
|
795 | 777dc784 | Peter Maydell | { .name = "pxa250", .initfn = pxa250_initfn },
|
796 | 777dc784 | Peter Maydell | { .name = "pxa255", .initfn = pxa255_initfn },
|
797 | 777dc784 | Peter Maydell | { .name = "pxa260", .initfn = pxa260_initfn },
|
798 | 777dc784 | Peter Maydell | { .name = "pxa261", .initfn = pxa261_initfn },
|
799 | 777dc784 | Peter Maydell | { .name = "pxa262", .initfn = pxa262_initfn },
|
800 | 777dc784 | Peter Maydell | /* "pxa270" is an alias for "pxa270-a0" */
|
801 | 777dc784 | Peter Maydell | { .name = "pxa270", .initfn = pxa270a0_initfn },
|
802 | 777dc784 | Peter Maydell | { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
803 | 777dc784 | Peter Maydell | { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
804 | 777dc784 | Peter Maydell | { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
805 | 777dc784 | Peter Maydell | { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
806 | 777dc784 | Peter Maydell | { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
807 | 777dc784 | Peter Maydell | { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
808 | 777dc784 | Peter Maydell | { .name = "any", .initfn = arm_any_initfn },
|
809 | 777dc784 | Peter Maydell | }; |
810 | 777dc784 | Peter Maydell | |
811 | dec9c2d4 | Andreas Färber | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
812 | dec9c2d4 | Andreas Färber | { |
813 | dec9c2d4 | Andreas Färber | ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
814 | dec9c2d4 | Andreas Färber | CPUClass *cc = CPU_CLASS(acc); |
815 | 14969266 | Andreas Färber | DeviceClass *dc = DEVICE_CLASS(oc); |
816 | 14969266 | Andreas Färber | |
817 | 14969266 | Andreas Färber | acc->parent_realize = dc->realize; |
818 | 14969266 | Andreas Färber | dc->realize = arm_cpu_realizefn; |
819 | dec9c2d4 | Andreas Färber | |
820 | dec9c2d4 | Andreas Färber | acc->parent_reset = cc->reset; |
821 | dec9c2d4 | Andreas Färber | cc->reset = arm_cpu_reset; |
822 | 5900d6b2 | Andreas Färber | |
823 | 5900d6b2 | Andreas Färber | cc->class_by_name = arm_cpu_class_by_name; |
824 | 97a8ea5a | Andreas Färber | cc->do_interrupt = arm_cpu_do_interrupt; |
825 | 878096ee | Andreas Färber | cc->dump_state = arm_cpu_dump_state; |
826 | f45748f1 | Andreas Färber | cc->set_pc = arm_cpu_set_pc; |
827 | 5b50e790 | Andreas Färber | cc->gdb_read_register = arm_cpu_gdb_read_register; |
828 | 5b50e790 | Andreas Färber | cc->gdb_write_register = arm_cpu_gdb_write_register; |
829 | 00b941e5 | Andreas Färber | #ifndef CONFIG_USER_ONLY
|
830 | 00b941e5 | Andreas Färber | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
831 | 00b941e5 | Andreas Färber | cc->vmsd = &vmstate_arm_cpu; |
832 | 00b941e5 | Andreas Färber | #endif
|
833 | a0e372f0 | Andreas Färber | cc->gdb_num_core_regs = 26;
|
834 | dec9c2d4 | Andreas Färber | } |
835 | dec9c2d4 | Andreas Färber | |
836 | 777dc784 | Peter Maydell | static void cpu_register(const ARMCPUInfo *info) |
837 | 777dc784 | Peter Maydell | { |
838 | 777dc784 | Peter Maydell | TypeInfo type_info = { |
839 | 777dc784 | Peter Maydell | .parent = TYPE_ARM_CPU, |
840 | 777dc784 | Peter Maydell | .instance_size = sizeof(ARMCPU),
|
841 | 777dc784 | Peter Maydell | .instance_init = info->initfn, |
842 | 777dc784 | Peter Maydell | .class_size = sizeof(ARMCPUClass),
|
843 | e6f010cc | Andreas Färber | .class_init = info->class_init, |
844 | 777dc784 | Peter Maydell | }; |
845 | 777dc784 | Peter Maydell | |
846 | 51492fd1 | Andreas Färber | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
847 | 918fd083 | Eduardo Habkost | type_register(&type_info); |
848 | 51492fd1 | Andreas Färber | g_free((void *)type_info.name);
|
849 | 777dc784 | Peter Maydell | } |
850 | 777dc784 | Peter Maydell | |
851 | dec9c2d4 | Andreas Färber | static const TypeInfo arm_cpu_type_info = { |
852 | dec9c2d4 | Andreas Färber | .name = TYPE_ARM_CPU, |
853 | dec9c2d4 | Andreas Färber | .parent = TYPE_CPU, |
854 | dec9c2d4 | Andreas Färber | .instance_size = sizeof(ARMCPU),
|
855 | 777dc784 | Peter Maydell | .instance_init = arm_cpu_initfn, |
856 | 4b6a83fb | Peter Maydell | .instance_finalize = arm_cpu_finalizefn, |
857 | 777dc784 | Peter Maydell | .abstract = true,
|
858 | dec9c2d4 | Andreas Färber | .class_size = sizeof(ARMCPUClass),
|
859 | dec9c2d4 | Andreas Färber | .class_init = arm_cpu_class_init, |
860 | dec9c2d4 | Andreas Färber | }; |
861 | dec9c2d4 | Andreas Färber | |
862 | dec9c2d4 | Andreas Färber | static void arm_cpu_register_types(void) |
863 | dec9c2d4 | Andreas Färber | { |
864 | 777dc784 | Peter Maydell | int i;
|
865 | 777dc784 | Peter Maydell | |
866 | dec9c2d4 | Andreas Färber | type_register_static(&arm_cpu_type_info); |
867 | 777dc784 | Peter Maydell | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
868 | 777dc784 | Peter Maydell | cpu_register(&arm_cpus[i]); |
869 | 777dc784 | Peter Maydell | } |
870 | dec9c2d4 | Andreas Färber | } |
871 | dec9c2d4 | Andreas Färber | |
872 | dec9c2d4 | Andreas Färber | type_init(arm_cpu_register_types) |