root / target-openrisc / cpu.h @ 5b50e790
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1 | e67db06e | Jia Liu | /*
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2 | e67db06e | Jia Liu | * OpenRISC virtual CPU header.
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3 | e67db06e | Jia Liu | *
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4 | e67db06e | Jia Liu | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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5 | e67db06e | Jia Liu | *
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6 | e67db06e | Jia Liu | * This library is free software; you can redistribute it and/or
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7 | e67db06e | Jia Liu | * modify it under the terms of the GNU Lesser General Public
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8 | e67db06e | Jia Liu | * License as published by the Free Software Foundation; either
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9 | e67db06e | Jia Liu | * version 2 of the License, or (at your option) any later version.
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10 | e67db06e | Jia Liu | *
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11 | e67db06e | Jia Liu | * This library is distributed in the hope that it will be useful,
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12 | e67db06e | Jia Liu | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e67db06e | Jia Liu | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e67db06e | Jia Liu | * Lesser General Public License for more details.
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15 | e67db06e | Jia Liu | *
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16 | e67db06e | Jia Liu | * You should have received a copy of the GNU Lesser General Public
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17 | e67db06e | Jia Liu | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | e67db06e | Jia Liu | */
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19 | e67db06e | Jia Liu | |
20 | e67db06e | Jia Liu | #ifndef CPU_OPENRISC_H
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21 | e67db06e | Jia Liu | #define CPU_OPENRISC_H
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22 | e67db06e | Jia Liu | |
23 | e67db06e | Jia Liu | #define TARGET_LONG_BITS 32 |
24 | e67db06e | Jia Liu | #define ELF_MACHINE EM_OPENRISC
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25 | e67db06e | Jia Liu | |
26 | e67db06e | Jia Liu | #define CPUArchState struct CPUOpenRISCState |
27 | e67db06e | Jia Liu | |
28 | 726fe045 | Jia Liu | /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
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29 | 726fe045 | Jia Liu | struct OpenRISCCPU;
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30 | 726fe045 | Jia Liu | |
31 | e67db06e | Jia Liu | #include "config.h" |
32 | e67db06e | Jia Liu | #include "qemu-common.h" |
33 | 022c62cb | Paolo Bonzini | #include "exec/cpu-defs.h" |
34 | 6b4c305c | Paolo Bonzini | #include "fpu/softfloat.h" |
35 | 14cccb61 | Paolo Bonzini | #include "qom/cpu.h" |
36 | e67db06e | Jia Liu | |
37 | e67db06e | Jia Liu | #define TYPE_OPENRISC_CPU "or32-cpu" |
38 | e67db06e | Jia Liu | |
39 | e67db06e | Jia Liu | #define OPENRISC_CPU_CLASS(klass) \
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40 | e67db06e | Jia Liu | OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU) |
41 | e67db06e | Jia Liu | #define OPENRISC_CPU(obj) \
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42 | e67db06e | Jia Liu | OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU) |
43 | e67db06e | Jia Liu | #define OPENRISC_CPU_GET_CLASS(obj) \
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44 | e67db06e | Jia Liu | OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU) |
45 | e67db06e | Jia Liu | |
46 | e67db06e | Jia Liu | /**
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47 | e67db06e | Jia Liu | * OpenRISCCPUClass:
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48 | c296262b | Andreas Färber | * @parent_realize: The parent class' realize handler.
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49 | e67db06e | Jia Liu | * @parent_reset: The parent class' reset handler.
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50 | e67db06e | Jia Liu | *
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51 | e67db06e | Jia Liu | * A OpenRISC CPU model.
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52 | e67db06e | Jia Liu | */
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53 | e67db06e | Jia Liu | typedef struct OpenRISCCPUClass { |
54 | e67db06e | Jia Liu | /*< private >*/
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55 | e67db06e | Jia Liu | CPUClass parent_class; |
56 | e67db06e | Jia Liu | /*< public >*/
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57 | e67db06e | Jia Liu | |
58 | c296262b | Andreas Färber | DeviceRealize parent_realize; |
59 | e67db06e | Jia Liu | void (*parent_reset)(CPUState *cpu);
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60 | e67db06e | Jia Liu | } OpenRISCCPUClass; |
61 | e67db06e | Jia Liu | |
62 | e67db06e | Jia Liu | #define NB_MMU_MODES 3 |
63 | e67db06e | Jia Liu | |
64 | 726fe045 | Jia Liu | enum {
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65 | 726fe045 | Jia Liu | MMU_NOMMU_IDX = 0,
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66 | 726fe045 | Jia Liu | MMU_SUPERVISOR_IDX = 1,
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67 | 726fe045 | Jia Liu | MMU_USER_IDX = 2,
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68 | 726fe045 | Jia Liu | }; |
69 | 726fe045 | Jia Liu | |
70 | e67db06e | Jia Liu | #define TARGET_PAGE_BITS 13 |
71 | e67db06e | Jia Liu | |
72 | e67db06e | Jia Liu | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
73 | e67db06e | Jia Liu | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
74 | e67db06e | Jia Liu | |
75 | e67db06e | Jia Liu | #define SET_FP_CAUSE(reg, v) do {\ |
76 | e67db06e | Jia Liu | (reg) = ((reg) & ~(0x3f << 12)) | \ |
77 | e67db06e | Jia Liu | ((v & 0x3f) << 12);\ |
78 | e67db06e | Jia Liu | } while (0) |
79 | e67db06e | Jia Liu | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
80 | e67db06e | Jia Liu | #define UPDATE_FP_FLAGS(reg, v) do {\ |
81 | e67db06e | Jia Liu | (reg) |= ((v & 0x1f) << 2);\ |
82 | e67db06e | Jia Liu | } while (0) |
83 | e67db06e | Jia Liu | |
84 | 4dd044c6 | Jia Liu | /* Version Register */
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85 | 4dd044c6 | Jia Liu | #define SPR_VR 0xFFFF003F |
86 | 4dd044c6 | Jia Liu | |
87 | e67db06e | Jia Liu | /* Internal flags, delay slot flag */
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88 | e67db06e | Jia Liu | #define D_FLAG 1 |
89 | e67db06e | Jia Liu | |
90 | b6a71ef7 | Jia Liu | /* Interrupt */
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91 | b6a71ef7 | Jia Liu | #define NR_IRQS 32 |
92 | b6a71ef7 | Jia Liu | |
93 | e67db06e | Jia Liu | /* Unit presece register */
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94 | e67db06e | Jia Liu | enum {
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95 | e67db06e | Jia Liu | UPR_UP = (1 << 0), |
96 | e67db06e | Jia Liu | UPR_DCP = (1 << 1), |
97 | e67db06e | Jia Liu | UPR_ICP = (1 << 2), |
98 | e67db06e | Jia Liu | UPR_DMP = (1 << 3), |
99 | e67db06e | Jia Liu | UPR_IMP = (1 << 4), |
100 | e67db06e | Jia Liu | UPR_MP = (1 << 5), |
101 | e67db06e | Jia Liu | UPR_DUP = (1 << 6), |
102 | e67db06e | Jia Liu | UPR_PCUR = (1 << 7), |
103 | e67db06e | Jia Liu | UPR_PMP = (1 << 8), |
104 | e67db06e | Jia Liu | UPR_PICP = (1 << 9), |
105 | e67db06e | Jia Liu | UPR_TTP = (1 << 10), |
106 | e67db06e | Jia Liu | UPR_CUP = (255 << 24), |
107 | e67db06e | Jia Liu | }; |
108 | e67db06e | Jia Liu | |
109 | e67db06e | Jia Liu | /* CPU configure register */
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110 | e67db06e | Jia Liu | enum {
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111 | e67db06e | Jia Liu | CPUCFGR_NSGF = (15 << 0), |
112 | e67db06e | Jia Liu | CPUCFGR_CGF = (1 << 4), |
113 | e67db06e | Jia Liu | CPUCFGR_OB32S = (1 << 5), |
114 | e67db06e | Jia Liu | CPUCFGR_OB64S = (1 << 6), |
115 | e67db06e | Jia Liu | CPUCFGR_OF32S = (1 << 7), |
116 | e67db06e | Jia Liu | CPUCFGR_OF64S = (1 << 8), |
117 | e67db06e | Jia Liu | CPUCFGR_OV64S = (1 << 9), |
118 | e67db06e | Jia Liu | }; |
119 | e67db06e | Jia Liu | |
120 | e67db06e | Jia Liu | /* DMMU configure register */
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121 | e67db06e | Jia Liu | enum {
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122 | e67db06e | Jia Liu | DMMUCFGR_NTW = (3 << 0), |
123 | e67db06e | Jia Liu | DMMUCFGR_NTS = (7 << 2), |
124 | e67db06e | Jia Liu | DMMUCFGR_NAE = (7 << 5), |
125 | e67db06e | Jia Liu | DMMUCFGR_CRI = (1 << 8), |
126 | e67db06e | Jia Liu | DMMUCFGR_PRI = (1 << 9), |
127 | e67db06e | Jia Liu | DMMUCFGR_TEIRI = (1 << 10), |
128 | e67db06e | Jia Liu | DMMUCFGR_HTR = (1 << 11), |
129 | e67db06e | Jia Liu | }; |
130 | e67db06e | Jia Liu | |
131 | e67db06e | Jia Liu | /* IMMU configure register */
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132 | e67db06e | Jia Liu | enum {
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133 | e67db06e | Jia Liu | IMMUCFGR_NTW = (3 << 0), |
134 | e67db06e | Jia Liu | IMMUCFGR_NTS = (7 << 2), |
135 | e67db06e | Jia Liu | IMMUCFGR_NAE = (7 << 5), |
136 | e67db06e | Jia Liu | IMMUCFGR_CRI = (1 << 8), |
137 | e67db06e | Jia Liu | IMMUCFGR_PRI = (1 << 9), |
138 | e67db06e | Jia Liu | IMMUCFGR_TEIRI = (1 << 10), |
139 | e67db06e | Jia Liu | IMMUCFGR_HTR = (1 << 11), |
140 | e67db06e | Jia Liu | }; |
141 | e67db06e | Jia Liu | |
142 | e67db06e | Jia Liu | /* Float point control status register */
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143 | e67db06e | Jia Liu | enum {
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144 | e67db06e | Jia Liu | FPCSR_FPEE = 1,
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145 | e67db06e | Jia Liu | FPCSR_RM = (3 << 1), |
146 | e67db06e | Jia Liu | FPCSR_OVF = (1 << 3), |
147 | e67db06e | Jia Liu | FPCSR_UNF = (1 << 4), |
148 | e67db06e | Jia Liu | FPCSR_SNF = (1 << 5), |
149 | e67db06e | Jia Liu | FPCSR_QNF = (1 << 6), |
150 | e67db06e | Jia Liu | FPCSR_ZF = (1 << 7), |
151 | e67db06e | Jia Liu | FPCSR_IXF = (1 << 8), |
152 | e67db06e | Jia Liu | FPCSR_IVF = (1 << 9), |
153 | e67db06e | Jia Liu | FPCSR_INF = (1 << 10), |
154 | e67db06e | Jia Liu | FPCSR_DZF = (1 << 11), |
155 | e67db06e | Jia Liu | }; |
156 | e67db06e | Jia Liu | |
157 | e67db06e | Jia Liu | /* Exceptions indices */
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158 | e67db06e | Jia Liu | enum {
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159 | e67db06e | Jia Liu | EXCP_RESET = 0x1,
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160 | e67db06e | Jia Liu | EXCP_BUSERR = 0x2,
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161 | e67db06e | Jia Liu | EXCP_DPF = 0x3,
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162 | e67db06e | Jia Liu | EXCP_IPF = 0x4,
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163 | e67db06e | Jia Liu | EXCP_TICK = 0x5,
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164 | e67db06e | Jia Liu | EXCP_ALIGN = 0x6,
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165 | e67db06e | Jia Liu | EXCP_ILLEGAL = 0x7,
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166 | e67db06e | Jia Liu | EXCP_INT = 0x8,
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167 | e67db06e | Jia Liu | EXCP_DTLBMISS = 0x9,
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168 | e67db06e | Jia Liu | EXCP_ITLBMISS = 0xa,
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169 | e67db06e | Jia Liu | EXCP_RANGE = 0xb,
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170 | e67db06e | Jia Liu | EXCP_SYSCALL = 0xc,
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171 | e67db06e | Jia Liu | EXCP_FPE = 0xd,
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172 | e67db06e | Jia Liu | EXCP_TRAP = 0xe,
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173 | e67db06e | Jia Liu | EXCP_NR, |
174 | e67db06e | Jia Liu | }; |
175 | e67db06e | Jia Liu | |
176 | e67db06e | Jia Liu | /* Supervisor register */
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177 | e67db06e | Jia Liu | enum {
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178 | e67db06e | Jia Liu | SR_SM = (1 << 0), |
179 | e67db06e | Jia Liu | SR_TEE = (1 << 1), |
180 | e67db06e | Jia Liu | SR_IEE = (1 << 2), |
181 | e67db06e | Jia Liu | SR_DCE = (1 << 3), |
182 | e67db06e | Jia Liu | SR_ICE = (1 << 4), |
183 | e67db06e | Jia Liu | SR_DME = (1 << 5), |
184 | e67db06e | Jia Liu | SR_IME = (1 << 6), |
185 | e67db06e | Jia Liu | SR_LEE = (1 << 7), |
186 | e67db06e | Jia Liu | SR_CE = (1 << 8), |
187 | e67db06e | Jia Liu | SR_F = (1 << 9), |
188 | e67db06e | Jia Liu | SR_CY = (1 << 10), |
189 | e67db06e | Jia Liu | SR_OV = (1 << 11), |
190 | e67db06e | Jia Liu | SR_OVE = (1 << 12), |
191 | e67db06e | Jia Liu | SR_DSX = (1 << 13), |
192 | e67db06e | Jia Liu | SR_EPH = (1 << 14), |
193 | e67db06e | Jia Liu | SR_FO = (1 << 15), |
194 | e67db06e | Jia Liu | SR_SUMRA = (1 << 16), |
195 | e67db06e | Jia Liu | SR_SCE = (1 << 17), |
196 | e67db06e | Jia Liu | }; |
197 | e67db06e | Jia Liu | |
198 | e67db06e | Jia Liu | /* OpenRISC Hardware Capabilities */
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199 | e67db06e | Jia Liu | enum {
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200 | e67db06e | Jia Liu | OPENRISC_FEATURE_NSGF = (15 << 0), |
201 | e67db06e | Jia Liu | OPENRISC_FEATURE_CGF = (1 << 4), |
202 | e67db06e | Jia Liu | OPENRISC_FEATURE_OB32S = (1 << 5), |
203 | e67db06e | Jia Liu | OPENRISC_FEATURE_OB64S = (1 << 6), |
204 | e67db06e | Jia Liu | OPENRISC_FEATURE_OF32S = (1 << 7), |
205 | e67db06e | Jia Liu | OPENRISC_FEATURE_OF64S = (1 << 8), |
206 | e67db06e | Jia Liu | OPENRISC_FEATURE_OV64S = (1 << 9), |
207 | e67db06e | Jia Liu | }; |
208 | e67db06e | Jia Liu | |
209 | 99f575ed | Jia Liu | /* Tick Timer Mode Register */
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210 | 99f575ed | Jia Liu | enum {
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211 | 99f575ed | Jia Liu | TTMR_TP = (0xfffffff),
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212 | 99f575ed | Jia Liu | TTMR_IP = (1 << 28), |
213 | 99f575ed | Jia Liu | TTMR_IE = (1 << 29), |
214 | 99f575ed | Jia Liu | TTMR_M = (3 << 30), |
215 | 99f575ed | Jia Liu | }; |
216 | 99f575ed | Jia Liu | |
217 | 99f575ed | Jia Liu | /* Timer Mode */
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218 | 99f575ed | Jia Liu | enum {
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219 | 99f575ed | Jia Liu | TIMER_NONE = (0 << 30), |
220 | 99f575ed | Jia Liu | TIMER_INTR = (1 << 30), |
221 | 99f575ed | Jia Liu | TIMER_SHOT = (2 << 30), |
222 | 99f575ed | Jia Liu | TIMER_CONT = (3 << 30), |
223 | 99f575ed | Jia Liu | }; |
224 | 99f575ed | Jia Liu | |
225 | 726fe045 | Jia Liu | /* TLB size */
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226 | 726fe045 | Jia Liu | enum {
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227 | 726fe045 | Jia Liu | DTLB_WAYS = 1,
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228 | 726fe045 | Jia Liu | DTLB_SIZE = 64,
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229 | 726fe045 | Jia Liu | DTLB_MASK = (DTLB_SIZE-1),
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230 | 726fe045 | Jia Liu | ITLB_WAYS = 1,
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231 | 726fe045 | Jia Liu | ITLB_SIZE = 64,
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232 | 726fe045 | Jia Liu | ITLB_MASK = (ITLB_SIZE-1),
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233 | 726fe045 | Jia Liu | }; |
234 | 726fe045 | Jia Liu | |
235 | 726fe045 | Jia Liu | /* TLB prot */
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236 | 726fe045 | Jia Liu | enum {
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237 | 726fe045 | Jia Liu | URE = (1 << 6), |
238 | 726fe045 | Jia Liu | UWE = (1 << 7), |
239 | 726fe045 | Jia Liu | SRE = (1 << 8), |
240 | 726fe045 | Jia Liu | SWE = (1 << 9), |
241 | 726fe045 | Jia Liu | |
242 | 726fe045 | Jia Liu | SXE = (1 << 6), |
243 | 726fe045 | Jia Liu | UXE = (1 << 7), |
244 | 726fe045 | Jia Liu | }; |
245 | 726fe045 | Jia Liu | |
246 | 726fe045 | Jia Liu | /* check if tlb available */
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247 | 726fe045 | Jia Liu | enum {
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248 | 726fe045 | Jia Liu | TLBRET_INVALID = -3,
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249 | 726fe045 | Jia Liu | TLBRET_NOMATCH = -2,
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250 | 726fe045 | Jia Liu | TLBRET_BADADDR = -1,
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251 | 726fe045 | Jia Liu | TLBRET_MATCH = 0
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252 | 726fe045 | Jia Liu | }; |
253 | 726fe045 | Jia Liu | |
254 | 726fe045 | Jia Liu | typedef struct OpenRISCTLBEntry { |
255 | 726fe045 | Jia Liu | uint32_t mr; |
256 | 726fe045 | Jia Liu | uint32_t tr; |
257 | 726fe045 | Jia Liu | } OpenRISCTLBEntry; |
258 | 726fe045 | Jia Liu | |
259 | 726fe045 | Jia Liu | #ifndef CONFIG_USER_ONLY
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260 | 726fe045 | Jia Liu | typedef struct CPUOpenRISCTLBContext { |
261 | 726fe045 | Jia Liu | OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE]; |
262 | 726fe045 | Jia Liu | OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE]; |
263 | 726fe045 | Jia Liu | |
264 | 726fe045 | Jia Liu | int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, |
265 | a8170e5e | Avi Kivity | hwaddr *physical, |
266 | 726fe045 | Jia Liu | int *prot,
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267 | 726fe045 | Jia Liu | target_ulong address, int rw);
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268 | 726fe045 | Jia Liu | int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, |
269 | a8170e5e | Avi Kivity | hwaddr *physical, |
270 | 726fe045 | Jia Liu | int *prot,
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271 | 726fe045 | Jia Liu | target_ulong address, int rw);
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272 | 726fe045 | Jia Liu | } CPUOpenRISCTLBContext; |
273 | 726fe045 | Jia Liu | #endif
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274 | 726fe045 | Jia Liu | |
275 | e67db06e | Jia Liu | typedef struct CPUOpenRISCState { |
276 | e67db06e | Jia Liu | target_ulong gpr[32]; /* General registers */ |
277 | e67db06e | Jia Liu | target_ulong pc; /* Program counter */
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278 | e67db06e | Jia Liu | target_ulong npc; /* Next PC */
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279 | e67db06e | Jia Liu | target_ulong ppc; /* Prev PC */
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280 | e67db06e | Jia Liu | target_ulong jmp_pc; /* Jump PC */
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281 | e67db06e | Jia Liu | |
282 | e67db06e | Jia Liu | target_ulong machi; /* Multiply register MACHI */
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283 | e67db06e | Jia Liu | target_ulong maclo; /* Multiply register MACLO */
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284 | e67db06e | Jia Liu | |
285 | e67db06e | Jia Liu | target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
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286 | e67db06e | Jia Liu | target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
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287 | e67db06e | Jia Liu | |
288 | e67db06e | Jia Liu | target_ulong epcr; /* Exception PC register */
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289 | e67db06e | Jia Liu | target_ulong eear; /* Exception EA register */
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290 | e67db06e | Jia Liu | |
291 | e67db06e | Jia Liu | uint32_t sr; /* Supervisor register */
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292 | e67db06e | Jia Liu | uint32_t vr; /* Version register */
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293 | e67db06e | Jia Liu | uint32_t upr; /* Unit presence register */
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294 | e67db06e | Jia Liu | uint32_t cpucfgr; /* CPU configure register */
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295 | e67db06e | Jia Liu | uint32_t dmmucfgr; /* DMMU configure register */
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296 | e67db06e | Jia Liu | uint32_t immucfgr; /* IMMU configure register */
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297 | e67db06e | Jia Liu | uint32_t esr; /* Exception supervisor register */
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298 | e67db06e | Jia Liu | uint32_t fpcsr; /* Float register */
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299 | e67db06e | Jia Liu | float_status fp_status; |
300 | e67db06e | Jia Liu | |
301 | e67db06e | Jia Liu | uint32_t flags; /* cpu_flags, we only use it for exception
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302 | e67db06e | Jia Liu | in solt so far. */
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303 | e67db06e | Jia Liu | uint32_t btaken; /* the SR_F bit */
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304 | e67db06e | Jia Liu | |
305 | e67db06e | Jia Liu | CPU_COMMON |
306 | e67db06e | Jia Liu | |
307 | e67db06e | Jia Liu | #ifndef CONFIG_USER_ONLY
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308 | 726fe045 | Jia Liu | CPUOpenRISCTLBContext * tlb; |
309 | 726fe045 | Jia Liu | |
310 | e67db06e | Jia Liu | struct QEMUTimer *timer;
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311 | e67db06e | Jia Liu | uint32_t ttmr; /* Timer tick mode register */
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312 | e67db06e | Jia Liu | uint32_t ttcr; /* Timer tick count register */
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313 | e67db06e | Jia Liu | |
314 | e67db06e | Jia Liu | uint32_t picmr; /* Interrupt mask register */
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315 | e67db06e | Jia Liu | uint32_t picsr; /* Interrupt contrl register*/
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316 | e67db06e | Jia Liu | #endif
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317 | b6a71ef7 | Jia Liu | void *irq[32]; /* Interrupt irq input */ |
318 | e67db06e | Jia Liu | } CPUOpenRISCState; |
319 | e67db06e | Jia Liu | |
320 | e67db06e | Jia Liu | /**
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321 | e67db06e | Jia Liu | * OpenRISCCPU:
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322 | e67db06e | Jia Liu | * @env: #CPUOpenRISCState
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323 | e67db06e | Jia Liu | *
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324 | e67db06e | Jia Liu | * A OpenRISC CPU.
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325 | e67db06e | Jia Liu | */
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326 | e67db06e | Jia Liu | typedef struct OpenRISCCPU { |
327 | e67db06e | Jia Liu | /*< private >*/
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328 | e67db06e | Jia Liu | CPUState parent_obj; |
329 | e67db06e | Jia Liu | /*< public >*/
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330 | e67db06e | Jia Liu | |
331 | e67db06e | Jia Liu | CPUOpenRISCState env; |
332 | e67db06e | Jia Liu | |
333 | e67db06e | Jia Liu | uint32_t feature; /* CPU Capabilities */
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334 | e67db06e | Jia Liu | } OpenRISCCPU; |
335 | e67db06e | Jia Liu | |
336 | e67db06e | Jia Liu | static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) |
337 | e67db06e | Jia Liu | { |
338 | 6e42be7c | Andreas Färber | return container_of(env, OpenRISCCPU, env);
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339 | e67db06e | Jia Liu | } |
340 | e67db06e | Jia Liu | |
341 | e67db06e | Jia Liu | #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
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342 | e67db06e | Jia Liu | |
343 | fadf9825 | Andreas Färber | #define ENV_OFFSET offsetof(OpenRISCCPU, env)
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344 | fadf9825 | Andreas Färber | |
345 | e67db06e | Jia Liu | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); |
346 | e67db06e | Jia Liu | |
347 | e67db06e | Jia Liu | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
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348 | e67db06e | Jia Liu | int cpu_openrisc_exec(CPUOpenRISCState *s);
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349 | 97a8ea5a | Andreas Färber | void openrisc_cpu_do_interrupt(CPUState *cpu);
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350 | 878096ee | Andreas Färber | void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
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351 | 878096ee | Andreas Färber | fprintf_function cpu_fprintf, int flags);
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352 | 00b941e5 | Andreas Färber | hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
353 | 5b50e790 | Andreas Färber | int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
354 | 5b50e790 | Andreas Färber | int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
355 | e67db06e | Jia Liu | void openrisc_translate_init(void); |
356 | 726fe045 | Jia Liu | int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
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357 | 726fe045 | Jia Liu | target_ulong address, |
358 | 726fe045 | Jia Liu | int rw, int mmu_idx); |
359 | d962783e | Jia Liu | int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); |
360 | e67db06e | Jia Liu | |
361 | e67db06e | Jia Liu | #define cpu_list cpu_openrisc_list
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362 | e67db06e | Jia Liu | #define cpu_exec cpu_openrisc_exec
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363 | e67db06e | Jia Liu | #define cpu_gen_code cpu_openrisc_gen_code
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364 | 726fe045 | Jia Liu | #define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
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365 | d962783e | Jia Liu | #define cpu_signal_handler cpu_openrisc_signal_handler
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366 | e67db06e | Jia Liu | |
367 | e67db06e | Jia Liu | #ifndef CONFIG_USER_ONLY
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368 | da697214 | Andreas Färber | extern const struct VMStateDescription vmstate_openrisc_cpu; |
369 | da697214 | Andreas Färber | |
370 | dd29c7fb | Jia Liu | /* hw/openrisc_pic.c */
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371 | dd29c7fb | Jia Liu | void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
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372 | dd29c7fb | Jia Liu | |
373 | 99f575ed | Jia Liu | /* hw/openrisc_timer.c */
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374 | 99f575ed | Jia Liu | void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
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375 | 99f575ed | Jia Liu | void cpu_openrisc_count_update(OpenRISCCPU *cpu);
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376 | 99f575ed | Jia Liu | void cpu_openrisc_count_start(OpenRISCCPU *cpu);
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377 | 99f575ed | Jia Liu | void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
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378 | 99f575ed | Jia Liu | |
379 | e67db06e | Jia Liu | void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
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380 | 726fe045 | Jia Liu | int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
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381 | a8170e5e | Avi Kivity | hwaddr *physical, |
382 | 726fe045 | Jia Liu | int *prot, target_ulong address, int rw); |
383 | 726fe045 | Jia Liu | int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
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384 | a8170e5e | Avi Kivity | hwaddr *physical, |
385 | 726fe045 | Jia Liu | int *prot, target_ulong address, int rw); |
386 | 726fe045 | Jia Liu | int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
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387 | a8170e5e | Avi Kivity | hwaddr *physical, |
388 | 726fe045 | Jia Liu | int *prot, target_ulong address, int rw); |
389 | e67db06e | Jia Liu | #endif
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390 | e67db06e | Jia Liu | |
391 | e67db06e | Jia Liu | static inline CPUOpenRISCState *cpu_init(const char *cpu_model) |
392 | e67db06e | Jia Liu | { |
393 | e67db06e | Jia Liu | OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model); |
394 | e67db06e | Jia Liu | if (cpu) {
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395 | e67db06e | Jia Liu | return &cpu->env;
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396 | e67db06e | Jia Liu | } |
397 | e67db06e | Jia Liu | return NULL; |
398 | e67db06e | Jia Liu | } |
399 | e67db06e | Jia Liu | |
400 | 022c62cb | Paolo Bonzini | #include "exec/cpu-all.h" |
401 | e67db06e | Jia Liu | |
402 | e67db06e | Jia Liu | static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, |
403 | e67db06e | Jia Liu | target_ulong *pc, |
404 | e67db06e | Jia Liu | target_ulong *cs_base, int *flags)
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405 | e67db06e | Jia Liu | { |
406 | e67db06e | Jia Liu | *pc = env->pc; |
407 | e67db06e | Jia Liu | *cs_base = 0;
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408 | e67db06e | Jia Liu | /* D_FLAG -- branch instruction exception */
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409 | e67db06e | Jia Liu | *flags = (env->flags & D_FLAG); |
410 | e67db06e | Jia Liu | } |
411 | e67db06e | Jia Liu | |
412 | e67db06e | Jia Liu | static inline int cpu_mmu_index(CPUOpenRISCState *env) |
413 | e67db06e | Jia Liu | { |
414 | 726fe045 | Jia Liu | if (!(env->sr & SR_IME)) {
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415 | 726fe045 | Jia Liu | return MMU_NOMMU_IDX;
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416 | 726fe045 | Jia Liu | } |
417 | 726fe045 | Jia Liu | return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; |
418 | e67db06e | Jia Liu | } |
419 | e67db06e | Jia Liu | |
420 | b6a71ef7 | Jia Liu | #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
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421 | 3993c6bd | Andreas Färber | static inline bool cpu_has_work(CPUState *cpu) |
422 | e67db06e | Jia Liu | { |
423 | 259186a7 | Andreas Färber | return cpu->interrupt_request & (CPU_INTERRUPT_HARD |
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424 | b6a71ef7 | Jia Liu | CPU_INTERRUPT_TIMER); |
425 | e67db06e | Jia Liu | } |
426 | e67db06e | Jia Liu | |
427 | 022c62cb | Paolo Bonzini | #include "exec/exec-all.h" |
428 | e67db06e | Jia Liu | |
429 | e67db06e | Jia Liu | static inline target_ulong cpu_get_pc(CPUOpenRISCState *env) |
430 | e67db06e | Jia Liu | { |
431 | e67db06e | Jia Liu | return env->pc;
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432 | e67db06e | Jia Liu | } |
433 | e67db06e | Jia Liu | |
434 | e67db06e | Jia Liu | #endif /* CPU_OPENRISC_H */ |