gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro andmakes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g., sed i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target*/gdbstub.c...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: Move cpu_gdb_{read,write}_register()
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
exec: Change cpu_memory_rw_debug() argument to CPUState
Propagate X86CPU in kvmvapic for simplicity.
gdbstub: Change gdb_register_coprocessor() argument to CPUState
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
gdbstub: Change syscall callback argument to CPUState
Callback implementations were specific to arm and m68k, so can easilycast to ARMCPU and M68kCPU respectively.
Prepares for changing GDBState::c_cpu to CPUState.
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
target-arm: implement LDA/STL instructions
This adds support for the ARMv8 load acquire/store release instructions.Since qemu does nothing special for memory barriers, these can beemulated like their non-acquire/release counterparts.
Signed-off-by: Mans Rullgard <mans@mansr.com>...
target-arm: explicitly decode SEVL instruction
The ARMv8 SEVL instruction is in the architectural hint space alreadyemulated as nop. This makes the decoding of SEVL explicit for clarity.
Signed-off-by: Mans Rullgard <mans@mansr.com>Message-id: 1370606786-5650-3-git-send-email-mans@mansr.com...
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo.access fields in place. So there is no need to replicate the callto define_arm_cp_reg(). Dropped, and let the OMAP case fall through...
target-arm/helper.c: Implement MIDR aliases
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space defaultto aliasing the MIDR register. Set all registers in the space to accessMIDR by default.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
target-arm/helper.c: Allow const opaques in arm CP
Allow for defining const opaque data in ARM CP register definitions bysetting .opaque = foo. If non null opaque is passed intodefine_one_arm_cp_reg_with_opaque then that opaque will takeprecedence, otherwise if null opaque is passed, the original opaque...
target-arm: avoid undefined behaviour when writing TTBCR
LPAE CPUs have more potentially valid bits in the TTBCR, and so thesimple masking out of invalid bits is no longer sufficient to obtainthe base address width field of the register, which is what we use to...
target-arm: Avoid g_hash_table_get_keys()
g_hash_table_get_keys() was only introduced in glib 2.14, and we'restill targeting a minimum version of 2.12. Rewrite the offendingcode (introduced in commit 721fae1) to use g_hash_table_foreach()to build the list of keys....
target-arm: add feature flag for ARMv8
Signed-off-by: Mans Rullgard <mans@mansr.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPUrelated -- they are specific to the TLS ABI for a a particular OS.Move them into the linux-user/ tree where they belong....
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
A transition from CPUFooState to FooCPU can be considered safe,just like FooCPU::env access in the opposite direction.The only benefit of the FOO_CPU() casts would be protection againstbogus CPUFooState pointers, but then surrounding code would likely...
memory: add ref/unref calls
Add ref/unref calls at the following places:
- places where memory regions are stashed by a listener and used outside the BQL (including in Xen or KVM).
- memory_region_find callsites
- creation of aliases and containers (only the aliased/contained...
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-arm: Convert TCG to using (index,value) list for cp migration
Convert the TCG ARM target to using an (index,value) list for migratingcoprocessors. The primary benefit of the (index,value) list is forpassing state between KVM and QEMU, but it works for TCG-to-TCG...
target-arm: Initialize cpreg list from KVM when using KVM
When using KVM, use the kernel's initial state to set up thecpreg list, and sync to and from the kernel when doingmigration.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Reinitialize all KVM VCPU registers on reset
Since the ARM KVM API doesn't include a "reset this VCPU" ioctl, we have to capture the initial values of everyregister it knows about so that we can reset the VCPUby feeding those values back again....
target-arm: Use tuple list to sync cp regs with KVM
Use the tuple list of cp registers for syncing KVM state to QEMU,rather than only syncing a very minimal set by hand.
target-arm: Make LPAE feature imply V7MP
The v7 ARM ARM specifies that the Large Physical AddressExtension requires implementation of the MultiprocessingExtensions, so make our LPAE feature imply V7MP ratherthan specifying both in the A15 CPU initfn....
target-arm: Allow special cpregs to have flags set
Relax the "is this a valid ARMCPRegInfo type value?" check to permit"special" cpregs to have flags other than ARM_CP_SPECIAL set. Atthe moment none of the other flags are relevant for special regs,but the migration related flag we're about to introduce can apply...
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
For reading and writing register values from the kernel for KVM,we need to provide accessor functions which are guaranteed to succeedand don't impose access checks, mask out unwritable bits, etc....
target-arm: mark up cpregs for no-migrate or raw access
Mark up coprocessor register definitions to add raw accessfunctions or mark the register as non-migratable where necessary.
Merge remote-tracking branch 'mjt/trivial-patches-next' into staging
Merge remote-tracking branch 'pmaydell/target-arm.next' into staging
Message-id: 1370268884-25945-1-git-send-email-peter.maydell@linaro.orgSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
KVM: ARM: Add dummy kvm_arch_init_irq_routing()
The common KVM code insists on calling kvm_arch_init_irq_routing()as soon as it sees kernel header support for it (regardless of whetherQEMU supports it). Provide a dummy function to satisfy this.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>...
Fix rfe instruction
The rfe instruction has been broken since patch5a839c0d54fac9db0516904db873a4fe01f50f4b because of a typo.
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Remove unnecessary break statements
Fix these warnings from cppcheck:
hw/display/cirrus_vga.c:2603:hw/sd/sd.c:348:hw/timer/exynos4210_mct.c:1033:target-arm/translate.c:9886:target-s390x/mem_helper.c:518:target-unicore32/translate.c:1936: style: Consecutive return, break, continue, goto or throw statements are unnecessary....
target-arm: Remove gen_{ld,st}* definitions
All the uses of the gen_{ld,st}* functions are gone now, so removethe functions themselves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove uses of gen_{ld,st}* from Neon code
target-arm: Remove use of gen_{ld,st}* from ldrex/strex
target-arm: Remove gen_{ld,st}* from basic ARM insns
target-arm: Remove gen_{ld,st}* from Thumb insns
target-arm: Remove gen_{ld,st}* from thumb2 decoder
target-arm: Remove uses of gen_{ld,st}* from iWMMXt code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove gen_ld64() and gen_st64()
gen_ld64() and gen_st64() are used only in one place, so justexpand them out.
target-arm: Don't use TCGv when we mean TCGv_i32
TCGv changes size depending on the compile time value ofTARGET_LONG_BITS. This is useful for generating code for MIPS style"instructions are the same but the register width changes" CPUs, andalso for the generic bits of QEMU which operate on "width of a...
target-arm: Fix incorrect check of kvm_vcpu_ioctl return value
kvm_vcpu_ioctl() returns ETHING on error, not ETHING - correctan incorrect check in kvm_arch_init_vcpu(). This would not havehad any significant ill-effects -- we would just have propagated...
target-arm: port ARM CPU save/load to use VMState
Port the ARM CPU save/load code to use VMState. Some state issaved in a slightly different order to simplify things -- forexample arrays are saved one after the other rather than 'striped',and we always save all 32 VFP registers even if the CPU happens...
target-arm: Add some missing CPU state fields to VMState
A number of CPU state fields were accidentally omitted fromour migration state: some OMAP specific cp15 registers, andsome related to state for load/store exclusive insns. Add them.
target-arm: Correctly restore FPSCR
Use the helper functions to save and restore the FPSCR, so thatwe correctly propagate rounding mode and flushing behaviour intothe float_status fields. This also allows us to stop saving thevector length/stride fields separately....
target-arm: Reinsert missing return statement in ARM mode SRS decode
Since patch 81465888c5306cd94abb9847e560796fd13d3c2f target-arm: factor out handling of SRS instructionthe ARM mode SRS instruction has not worked in QEMU.
The problem is a missing return directive that was removed in the...
arm: fix location of some include files
The recent rearrangement of include files had some minor errors: devices.h is not ARM specific and should not be in arm/ arm.h should be in arm/
Move these two headers to correct this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions.Introduce arm_v7m_class_init() and use it for "cortex-m3" model.
Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(),override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt()...
target-arm: Use MemoryListener to identify GIC base address for KVM
When using an in-kernel GIC with KVM, we need to tell the kernel wherethe GIC's memory mapped registers live. Do this by registering aMemoryListener which tracks where the board model maps the A15's...
ARM KVM: save and load VFP registers from kernel
Add support for saving and restoring VFP register state from thekernel. This includes a check that the KVM-created CPU has fullVFP support (as the TCG Cortex-A15 model always does), since forthe moment ARM QEMU doesn't have any way to tweak optional features...
ARM: KVM: Add support for KVM on ARM architecture
Add basic support for KVM on ARM architecture.
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>[PMM: Minor tweaks and code cleanup, switch to ONE_REG]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Drop CPUARMState* argument from bank_number()
Drop the CPUARMState* argument from bank_number(), since we onlyuse it for passing to cpu_abort(). Use hw_error() instead.This avoids propagating further interfaces using env pointers.
In the long term this function's callers need auditing to fix...
target-arm: Factor out handling of SRS instruction
Factor out the handling of the SRS instruction rather thanduplicating it between the Thumb and ARM decoders. This inpassing fixes two bugs in the Thumb decoder's SRS handlingwhich didn't exist in the ARM decoder:...
target-arm: Don't decode RFE or SRS on M profile cores
M profile cores do not have the RFE or SRS instructions, socorrectly UNDEF these insn patterns on those cores.
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specificcode that needs to generate TCG instructions which reference CPUStatefields given the cpu_env register that TCG targets set up with apointer to the CPUArchState struct....
arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CCand sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)...
target-arm: Fix sbc_CC carry
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits,it does not produce the correct carry-out to bit 33. Doexactly what the manual says.
Using the ~T1 makes the add and subtract code paths nearlyidentical, so have sbc_CC use adc_CC....
target-arm: Use mul[us]2 in gen_mul[us]_i64_i32
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Use mul[us]2 and add2 in umlal et al
target-arm: Use add2 in gen_add_CC
target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.
target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.
target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer calledvia cpu.h prototype. To maintain the semantics of cpu_init(), setrealized = true explicitly in cpu_arm_init().
Move GDB coprocessor registration, CPU reset and vCPU initialization...
target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names weremapped 1:1 to type names. As a side effect this gained us a type "any",which is now a device.
To avoid "-device any" silliness and to pave the way for compiling...
target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes
Fix a leak of a TCG temporary in code paths for VFP system registerwrites for cases which UNDEF or are write-ignored.
target-arm: Catch attempt to instantiate abstract type in cpu_init()
This fixes -cpu arm-cpu asserting.
Cc: qemu-stable@nongnu.orgAcked-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().
If the name matches an existing type, also check whether that type isactually (a sub-type of) TYPE_ARM_CPU.
This fixes, e.g., -cpu tmp105 asserting....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-arm: use type_register() instead of type_register_static()
The type_register_static() interface is documented as:
type_register_static: @info: The #TypeInfo of the new type.
@info and all of the strings it points to should exist for the life...
target-arm: Fix SWI (SVC) instruction in M profile.
When do_interrupt_v7m is called with EXCP_SWI, the PC alreadypoints to the next instruction. Don't modify it here.
Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.
cpu: Introduce CPUListState struct
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it foreach target. Place it in cpu-common.h to avoid circular dependencies.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Igor Mammedov <imammedo@redhat.com>...
fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
softmmu: move include files to include/sysemu/
misc: move include files to include/qemu/
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>