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# Date Author Comment
a4bcea3d 02/27/2013 09:06 pm Richard Henderson

target-i386: Use mulu2 and muls2

These correspond very closely to the insns that we're emulating.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
f1300734 02/20/2013 09:05 am Richard Henderson

target-i386: Use clz/ctz for bsf/bsr helpers

And mark the helpers as NO_RWG_SE.

Signed-off-by: Richard Henderson <>
321c5351 02/20/2013 09:05 am Richard Henderson

target-i386: Implement tzcnt and fix lzcnt

We weren't computing flags for lzcnt at all. At the same time,
adjust the implementation of bsf/bsr to avoid the local branch,
using movcond instead.

Signed-off-by: Richard Henderson <>
5f1f4b17 02/19/2013 01:52 am Richard Henderson

target-i386: Implement MULX

Signed-off-by: Richard Henderson <>
0592f74a 02/19/2013 01:52 am Richard Henderson

target-i386: Implement PDEP, PEXT

Signed-off-by: Richard Henderson <>
988c3eb0 02/19/2013 01:39 am Richard Henderson

target-i386: Use CC_SRC2 for ADC and SBB

Add another slot in ENV and store two of the three inputs. This lets us
do less work when carry-out is not needed, and avoids the unpredictable
CC_OP after translating these insns.

Signed-off-by: Richard Henderson <>
db9f2597 02/19/2013 01:25 am Richard Henderson

target-i386: Make helper_cc_compute_{all,c} const

Pass the data in explicitly, rather than indirectly via env.
This avoids all sorts of unnecessary register spillage.

Signed-off-by: Richard Henderson <>
022c62cb 12/19/2012 09:31 am Paolo Bonzini

exec: move include files to include/exec/

Signed-off-by: Paolo Bonzini <>
95b638a2 10/28/2012 03:54 pm Aurelien Jarno

target-i386: rename helper flags

Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
a9321a4d 10/01/2012 04:04 pm H. Peter Anvin

x86: Implement SMEP and SMAP

This patch implements Supervisor Mode Execution Prevention (SMEP) and
Supervisor Mode Access Prevention (SMAP) for x86. The purpose of the
patch, obviously, is to help kernel developers debug the support for
those features.
...
4a7443be 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 for misc helpers

Add an explicit CPUX86State parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
2999a0b2 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 in segmentation helpers

Add an explicit CPUX86State parameter instead of relying on AREG0.

Rename remains of op_helper.c to seg_helper.c.

Signed-off-by: Blue Swirl <>
92fc4b58 08/14/2012 10:01 pm Blue Swirl

x86: switch to AREG0 free mode

Add an explicit CPUX86State parameter instead of relying on AREG0.

Remove temporary wrappers and switch to AREG0 free mode.

Signed-off-by: Blue Swirl <>
d3eb5eae 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 for FPU helpers

Make FPU helpers take a parameter for CPUState instead
of relying on global env.

Introduce temporary wrappers for FPU load and store ops. Remove
wrappers for non-AREG0 code. Don't call unconverted helpers
directly.

Signed-off-by: Blue Swirl <>
f0967a1a 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 for condition code helpers

Add an explicit CPUX86State parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
7923057b 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 for integer helpers

Add an explicit CPUX86State parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
052e80d5 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 for SVM helpers

Add an explicit CPUX86State parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
608badfc 08/14/2012 10:01 pm Blue Swirl

x86: avoid AREG0 for SMM helpers

Add an explicit CPUX86State parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
77b2bc2c 06/28/2012 11:28 pm Blue Swirl

x86: avoid AREG0 for exceptions

Add an explicit CPUX86State parameter instead of relying on AREG0.

Merge raise_exception_env() to raise_exception(), likewise with
raise_exception_err_env() and raise_exception_err().

Introduce cpu_svm_check_intercept_param() and cpu_vmexit()...
2355c16e 01/11/2012 10:55 am Aurelien Jarno

target-i386: fix SSE rounding and flush to zero

SSE rounding and flush to zero control has never been implemented. However
given that softfloat-native was using a single state for FPU and SSE and
given that glibc is setting both FPU and SSE state in fesetround(), this...
31501a71 10/23/2009 06:10 pm Andre Przywara

target-i386: implement lzcnt emulation

lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always...
1b050077 10/04/2009 03:46 pm Andre Przywara

target-i386: add RDTSCP support

RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()...
a2397807 05/22/2009 06:50 pm Jan Kiszka

x86: Add support for resume flag

Signed-off-by: Jan Kiszka <>
a7812ae4 11/17/2008 04:43 pm pbrook

TCG variable type checking.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2436b61a 09/25/2008 09:16 pm balrog

SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).

On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch
makes both 64-bit aware and enables them for Intel CPUs.
Add cpu save/load for 64-bit wide sysenter variables.

Signed-off-by: Alexander Graf <>...
79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
94451178 06/18/2008 12:32 pm bellard

HLT, MWAIT and MONITOR insn fixes (initial patch by Alexander Graf)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4746 c046a42c-6fe2-441c-8c8c-71466251a162
db620f46 06/04/2008 08:02 pm bellard

reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworked cr8 handling - added CPUState.hflags2

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4662 c046a42c-6fe2-441c-8c8c-71466251a162
914178d3 06/04/2008 04:53 pm bellard

32 bit SVM fixes - INVLPG and INVLPGA updates

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4660 c046a42c-6fe2-441c-8c8c-71466251a162
872929aa 05/28/2008 07:16 pm bellard

SVM rework

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4605 c046a42c-6fe2-441c-8c8c-71466251a162
437a88a5 05/22/2008 07:11 pm bellard

proper helper definition registering (all targets must do that)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
1b9d9ebb 05/22/2008 12:52 pm bellard

cmpxchg8b fix - added cmpxchg16b

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4522 c046a42c-6fe2-441c-8c8c-71466251a162
bd7a7b33 05/21/2008 08:07 pm bellard

convert eflags manipulation insns to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4515 c046a42c-6fe2-441c-8c8c-71466251a162
cec6843e 05/21/2008 07:25 pm bellard

converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LAR

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4513 c046a42c-6fe2-441c-8c8c-71466251a162
07be379f 05/21/2008 04:29 pm bellard

converted INTO/CMPXCHG8B to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4510 c046a42c-6fe2-441c-8c8c-71466251a162
6191b059 05/17/2008 09:44 pm bellard

BSR/BSF TCG conversion

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4477 c046a42c-6fe2-441c-8c8c-71466251a162
b6abf97d 05/17/2008 03:44 pm bellard

converted condition code supprot to TCG - converted shift ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4470 c046a42c-6fe2-441c-8c8c-71466251a162
b8b6a50b 05/15/2008 07:46 pm bellard

converted more helpers to TCG - fixed some SVM issues

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
b5b38f61 05/13/2008 01:05 am bellard

converted more helpers to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4447 c046a42c-6fe2-441c-8c8c-71466251a162
19e6c4b8 05/12/2008 10:10 pm bellard

converted x87 FPU ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4444 c046a42c-6fe2-441c-8c8c-71466251a162
5af45186 05/12/2008 07:47 pm bellard

converted SSE/MMX ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
57fec1fe 02/01/2008 12:50 pm bellard

use the TCG code generator

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162