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target-i386: add AES-NI instructions
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: add pclmulqdq instruction
Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode
Fix the order of the of the comparisons to match the "Intel 64 andIA-32 Architectures Software Developer's Manual".
target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" mode
pcmpXstrX instructions in "Equal each" mode force both invalid elementpair to true. It means (upper - MAX) bits should be setto 1, not (upper - MAX + 1)....
target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" mode
The inner loop should only change the current bit of the result, insteadof the whole result.
target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarity
valids can equals to -1 if the reg/mem string is empty. Change theexpression to have an empty xor mask in that case.
target-i386: SSE4.2: fix pcmpgtq instruction
The "Intel 64 and IA-32 Architectures Software Developer's Manual" (atleast recent versions) clearly says that the comparison is signed.
target-i386: SSE4.2: fix pcmpXstri instructions
ffs1 returns the first bit set to one starting counting from the mostsignificant bit.
pcmpXstri returns the most significant bit set to one, starting countingfrom the least significant bit.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-i386: SSE4.2: fix pcmpXstrm instructions
pcmpXstrm instructions returns their result in the XMM0 register andnot in the first operand.
x86: avoid AREG0 for FPU helpers
Make FPU helpers take a parameter for CPUState insteadof relying on global env.
Introduce temporary wrappers for FPU load and store ops. Removewrappers for non-AREG0 code. Don't call unconverted helpersdirectly.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
x86: fix coding style in ops_sse.h
Fix coding style in ops_sse.h before next commit.
target-i386: fix {min,max}{pd,ps,sd,ss} SSE2 instructions
minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2instructions have been broken when switching target-i386 to softfloat.It's not possible to use comparison instructions on float types anymore...
target-i386: fix round{pd,ps,sd,ss} SSE2 instructions
roundps and roundss SSE2 instructions have been broken when switchingtarget-i386 to softfloat. They use float64_round_to_int to convert afloat32, and while the implicit conversion from float32 to float64 was...
target-i386: fix dpps and dppd SSE2 instructions
The helpers implemented dpps and dppd SSE instructions are not passingthe correct argument types to the softfloat functions. While they dowork anyway providing a correct behaviour, this patch fixes that....
x86: fix pcmpestrm and pcmpistrm
Fix obvious typos (decrement and off-by-one error) in pcmpestrm and pcmpistrmwhich resulted in infinite loop. Reported by Frank Mehnert,spotted also by Coverity (bug 84752853).
Reported-by: Frank Mehnert <frank.mehnert@oracle.com>...
target-i386: Fix several SSE3 instructions.
haddp[sd], hsubp[sd] and addsubp[sd] operate on floats, thus it isnecessary to use the appropriate floating point calculation functions.If this is not done, those functions operate merely on integers, whichis not correct....
target-i386: replace approx_rsqrt and approx_rcp by softfloat ops
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: fix CMPUNORDPS/D and CMPORDPS/D instructions
SSE instructions CMPUNORDPS/D and CMPORDPS/D do not trigger an invalidexception if operands are qNANs.
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.Those include insertq and extrq, which are doing shift and mask onXMM registers, in two versions (immediate shift/length values andstored in another XMM register)....
Fix Sparse warnings: add "static"
Update to a hopefully more future proof FSF address
Replace gcc variadic macro extension with C99 version
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Remove FORCE_RET() and RETURN
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
Fix pmovsx* / pmovzx* SSE instructions (original fix by Frank Mehnert).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5841 c046a42c-6fe2-441c-8c8c-71466251a162
target-i386: fix helper_pmovmskb_mmx helper
(malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5728 c046a42c-6fe2-441c-8c8c-71466251a162
Fix crc32w decoding, fix a constant width in blendvpd.
Forced the constant's width to long long so that it doesn't overflow,problem spotted by C. W. Betts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5417 c046a42c-6fe2-441c-8c8c-71466251a162
Implement SSE4.1, SSE4.2 (x86).
This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNTextensions. Most instructions haven't been tested yet.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
Implement x86 SSSE3 instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5315 c046a42c-6fe2-441c-8c8c-71466251a162
converted more helpers to TCG - fixed some SVM issues
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
converted SSE/MMX ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
3DNow! instruction set emulation
(Michael Tross)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4180 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
fixed movd mmx/sse insn
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2321 c046a42c-6fe2-441c-8c8c-71466251a162
removed switches in op.c (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1400 c046a42c-6fe2-441c-8c8c-71466251a162
NaN support in FPU comparisons
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1341 c046a42c-6fe2-441c-8c8c-71466251a162
soft float support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1336 c046a42c-6fe2-441c-8c8c-71466251a162
FORCE_RET() fixes - fpu fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1236 c046a42c-6fe2-441c-8c8c-71466251a162
sse fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1224 c046a42c-6fe2-441c-8c8c-71466251a162
MMX/SSE support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1205 c046a42c-6fe2-441c-8c8c-71466251a162