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cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-mips: add missing check_dspr2 for multiply instructions
The emulator needs to check in hflags if DSP unit has been turned off beforeit generates code for MUL_PH, MUL_S_PH, MULQ_S_W, and MULQ_RS_W.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
mips64-linux-user: Enable 64-bit address mode and fpu
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix accumulator selection for MIPS16 and microMIPS
Add accumulator arguments to gen_HILO and gen_muldiv, rather thanextracting the accumulator directly from ctx->opcode. The extractionwas only right for the standard encoding: MIPS16 doesn't have access...
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-mips: Use mul[us]2 in [D]MULT[U] insns
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: Move TCG initialization to MIPSCPU initfn
Make mips_tcg_init() non-static and add tcg_enabled() check to suppressit for qtest.
target-mips: Introduce QOM realizefn for MIPSCPU
Introduce a realizefn and set realized = true from cpu_mips_init().
target-mips: enable access to DSP ASE if implemented
compute_hflags() will reset DSP h-flags, so MX bit should be initially setfor usermode in cpu_state_reset() if DSP ASE is implemented.This change will bring back user-mode support for DSP ASE, since one of the...
target-mips: Sign-extend the result of LWR
Sign-extend the result of LWR, as is already done for LWL. This is necessaryin the case where LWR loads the full word (i.e. the address is actuallyaligned). In the other cases, it is implementation defined whether the...
target-mips: Fix signedness of loads in MIPS16 RESTOREs
Make RESTORE use sign-extending rather than zero-extending loads.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: implement DSP (d)append sub-class with TCG
DSP instruction from the (d)append sub-class can be implemented withTCG. Use a different function for these instructions are they are quitedifferent from compare-pick sub-class.
Fix BALIGN instruction for negative value, where the value should be...
target-mips: generate a reserved instruction exception on CPU without DSP
On CPU without DSP ASE support, a reserved instruction exception (instead ofa DSP ASE sate disabled) should be generated.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: copy insn_flags in DisasContext
Copy insn_flags in DisasContext to avoid passing a CPUMIPSState pointerto subroutines, as suggested by Richard Henderson. Change subroutines touse this new field and remove the first argument.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-mips: fix DSP loads with rd = 0
When rd is 0, which still need to do the actually load to possiblygenerate a TLB exception.
Reviewed-by: Eric Johnson <ericj@mips.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-mips: Make repl_ph to sign extend to target-long
The immediate value is 9bits, should sign-extend to 16bits. The return value toregister should sign-extend to target_long, as Richard says, removing anunnecessary cast works fun.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>...
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: kill libdis, move disassemblers to disas/
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
target-mips: remove POOL48A from the microMIPS decoding
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add comments on POOL32Axf encoding
Current QEMU MIPS POOL32AXF encoding comes from microMIPS32and microMIPS32 DSP. Add comment here to help reading.
Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>Reviewed-by: Eric Johnson <ericj@mips.com>...
target-mips: Clean up microMIPS32 major opcode
I check MIPS microMIPS manual [1], and found the major opcode mightbe wrong. I add a comment to explicitly indicate what manual I am referingto, and according that manual I remove microMIPS32 major opcodes 0x1f....
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
target-mips: fix wrong microMIPS opcode encoding
While reading microMIPS decoding, I found a possible wrong opcodeencoding. According to [1] page 166, the bits 13..12 for MULTU is0x01 rather than 0x00. Please review, thanks.
[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP...
target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.
The call to gen_logic_imm for OPC_LUI passes -1 for rs. Thiscauses the MIPS_DEBUG statement to seg fault due to the deferenceof regnames[rs]. This patch fixes that.
Signed-off-by: Eric Johnson <ericj@mips.com>...
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
target-mips: don't use local temps for store conditional
Store conditional operations only need local temps in user mode. Fixthe code to use temp local only in user mode, this spares two memorystores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,...
target-mips: implement movn/movz using movcond
Avoid the branches in movn/movz implementation and replace them withmovcond. Also update a wrong command.
target-mips: optimize ddiv/ddivu/div/divu with movcond
The result of a division by 0, or a division of INT_MIN by -1 in thesigned case, is unpredictable. Just replace 0 by 1 in that case so thatit doesn't trigger a floating point exception on the host....
target-mips: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. Itallows the host to emit the corresponding instruction if available.
At the same time remove the (lsb > msb) test. The MIPS64R2 instruction...
target-mips: cleanup load/store operations
Load/store operations use macros for historical reasons. Now that thereis no point in keeping them, replace them by direct calls to qemu_ld/st.
target-mips: optimize load operations
Only allocate t1 when needed.
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quiteinefficient. Rewrite unaligned loads instructions using TCG andaligned loads. The number of actual loads operations to implementan unaligned load instruction is reduced from up to 8 to 1....
target-mips: correctly restore btarget upon exception
When the CPU state is restored through retranslation after an exception,btarget should also be restored.
target-mips: do not save CPU state when using retranslation
When the CPU state after a possible retranslation is going to be handledthrough code retranslation, we don't need to save the CPU state before.
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,msub, nmadd and nmsub instructions. At the same time replace the name ofthe helpers by the name of the instruction, as the only reason for the...
target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
All switch() decoding instruction have a default entry, so it is possibleto have unused enum entries. Remove conditional definitions of MIPS64opcode enums, as it only makes the code less readable....
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.
target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.
target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.
target-mips: Add ASE DSP load instructions
Add MIPS ASE DSP Load instructions.
target-mips: Add ASE DSP branch instructions
Add MIPS ASE DSP Branch instructions.
Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.
target-mips: Use TCG registers for the FPU.
With normal FP, this doesn't have much affect on the generated code,because most of the FP operations are not CONST/PURE, and so we spillregisters in about the same frequency as the explicit load/stores.
But with Loongson multimedia instructions, which are all integral and...
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-mips: Implement Loongson Multimedia Instructions
Implements all of the COP2 instructions except for the S<cond>family of comparisons. The documentation is unclear for those.
target-mips: Set opn in gen_ldst_multiple.
Used by MIPS_DEBUG, when enabled.
Signed-off-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix MIPS_DEBUG.
The macro uses the DisasContext. Pass it around as needed.
target-mips: Always evaluate debugging macro arguments
this will prevent some of the compilation errors with debuggingenabled from creeping back in.
target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Aurelien Jarno <aurelien@aurel32.net>
MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of codethat figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1Xnot being set where applicable that causes floating-point MADD family...
target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs. So theirbehavior is well defined when RD equals BASE. The MIPS ArchitectureVerification Programs (AVPs) check that they work as expected. This...
target-mips: add privilege level check to several Cop0 instructions
The MIPS Architecture Verification Programs (AVPs) check privilegedinstructions for the required privilege level. These changes are neededto pass the AVP suite.
mips-linux-user: Always support rdhwr.
The kernel will emulate this instruction if it's not supportednatively. This insn is used for TLS, among other things, andso is required by modern glibc.
Signed-off-by: Richard Henderson <rth@twiddle.net>Cc: Riku Voipio <riku.voipio@iki.fi>...
target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.
Fix order of CVT.PS.S operands
The FS input to CVT.PS.S is the high half and FT is the low half.tcg_gen_concat_i32_i64 takes the low half first, so the operandswere in the wrong order.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix operands of RECIP2.S and RECIP2.PS
Read the second input operand of RECIP2.S and RECIP2.PS from FT ratherthan FD. RECIP2.D is already correct.
target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required*MIPS32r2 RDHWR hardware registers should be accessible (theLinux kernel enables access to these same registers). Notethat these registers are still enabled when the MIPS ISA is...
MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps onfloating-point MADD group instructions with SIGILL, at least whileemulating MIPS32r2 processors. These instructions use the COP1X majoropcode and include ones like:...
target-mips: Use cpu_reset() in cpu_mips_init()
Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ifyCPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping theintroduction of subclasses for 1.1, due to mips_def_t the reset code...
target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSStatefor backwards compatibility.
mips: Fix BC1ANY24F instructions
There's some dodgy application of De Morgan's law in the emulationof the MIPS BC1ANY24F instructions: they end up branching onlyif all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests....
target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-mips: Start QOM'ifying CPU init
Move code not dependent on mips_def_t from cpu_mips_init() into aQOM initfn, as a start.
target-mips: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-mips: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs andTCs start in sleep.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
mips: Hook in more reg accesses via mttr/mftr
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-mips: fix save_cpu_state() calls
The rule is:- don't save PC if the exception is only triggered by softmmu.- save PC if the exception can be triggered by an helper.
Fix a 64-bit kernel crash when loading modules.
mips: Break TBs after mfc0_count
Break the TB after reading the count register. This makes itpossible to take timer interrupts immediately after a read ofa possibly expired timer.
target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:
int x; ... /* no initialization of x */ x = f (x);
which confused later bits of TCG rather badly, leading to crashes.
Fix the helpers to only return results (those instructions have no...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
mips: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:/src/qemu/target-mips/translate.c: In function 'gen_ld':/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]...
Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
mips: more fixes to the MIPS interrupt glue logic
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of theinterrupt logic to cpu-exec.c. Remove the remaining useless codeand fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-mips: add loongson 2E & 2F integer instructions
This patch adds support for loongson 2E & 2F instructions. They are thesame instructions, but differ by the opcode encoding.
target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.Emulate it as a NOP.
target-mips: split load and store
target-mips: fix DINSU instruction
target-mips: enable movn/movz on loongson 2E & 2F
target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.
Cc: Nathan Froyd <froydnj@codesourcery.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numberinginto the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral specialopcodes. Since there are several places where the delay slotrequirements for microMIPS branches differ from mips16 branches, usingopcodes is easier than checking hflags, then checking mips16...
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.