History | View | Annotate | Download (87 kB)
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-user
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPUrelated -- they are specific to the TLS ABI for a a particular OS.Move them into the linux-user/ tree where they belong....
target-ppc: Introduce unrealizefn for PowerPCCPU
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Add MMU type for 2.06 with AMR but no TB pages
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TBMMU capability from the MMU type mask, but not the AMR bit.
This leads to us having a new MMU type that we don't check for in ourMMU management functions....
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and anextra control register (MMCRA). This patch adds stub support for them to...
PPC: Remove env->hreset_excp_prefix
This value is not needed if we use correctly the MSR[IP] bit.
excp_prefix is always 0x00000000, except when the MSR[IP] bit isimplemented and set to 1, in that case excp_prefix is 0xfff00000.
The handling of MSR[IP] was already implemented but not used at reset...
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional pageprotection mechanism. Each virtual page has a "class" (0-31) recorded inthe PTE. The AMR register contains bits which can prohibit reads and/or...
target-ppc: Split user only code out of mmu_helper.c
mmu_helper.c is, for obvious reasons, almost entirely concerned withsoftmmu builds of qemu. However, it does contain one stub function whichis used when CONFIG_USER_ONLY=y - the user only versoin of...
target-ppc: Move ppc tlb_fill implementation into mmu_helper.c
For softmmu builds the interface from the generic code to the targetspecific MMU implementation is through the tlb_fill() function. For ppcthis is currently in mem_helper.c, whereas it would make more sense in...
target-ppc: Disentangle hash mmu helper functions
The newly separated paths for hash mmus rely on several helper functionswhich are still shared with 32-bit hash mmus: pp_check(), check_prot() andpte_update_flags(). While these don't have ugly ifdefs on the mmu type,...
target-ppc: Don't share get_pteg_offset() between 32 and 64-bit
The get_pteg_offset() helper function is currently shared between 32-bitand 64-bit hash mmus, taking a parameter for the hash pte size. In the64-bit paths, it's only called in one place, and it's a trivial...
target-ppc: Disentangle BAT code for 32-bit hash MMUs
The functions for looking up BATs (Block Address Translation - essentiallya level 0 TLB) are shared between the classic 32-bit hash MMUs and the6xx style software loaded TLB implementations.
This patch splits out a copy for the 32-bit hash MMUs, to facilitate...
target-ppc: mmu_ctx_t should not be a global type
mmu_ctx_t is currently defined in cpu.h. However it is used for temporaryinformation relating to mmu translation, and is only used in mmu_helper.cand (now) mmu-hash{32,64}.c. Furthermore it contains information which...
mmu-hash*: Add header file for definitions
Currently cpu.h contains a number of definitions relating to the 64-bithash MMU. Some are used in the MMU emulation code, but some are only usedin the spapr MMU management hcall implementations.
This patch moves these definitions (except for a few that are needed...
target-ppc: Disentangle pte_check()
Currently support for both 32-bit and 64-bit hash MMUs share animplementation of pte_check. But there are enough differences that thismeans the shared function has several very ugly conditionals on "is_64b".
This patch cleans things up by separating out the 64-bit version...
target-ppc: Disentangle find_pte()
32-bit and 64-bit hash MMU implementations currently share a find_ptefunction. This results in a whole bunch of ugly conditionals in the sharedfunction, and not all that much actually shared code.
This patch separates out the 32-bit and 64-bit versions, putting then...
target-ppc: Disentangle get_physical_address() paths
Depending on the MSR state, for 64-bit hash MMUs, get_physical_addresscan either call check_physical (which has further tests for mmu type)or get_segment64. Similarly for 32-bit hash MMUs we can either call...
PPC/GDB: handle read and write of fpscr
Although the support of this register may be uncomplete, there are noreason to prevent the debugger from reading or writing it.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Remove vestigial PowerPC 620 support
The PowerPC 620 was the very first 64-bit PowerPC implementation, buthardly anyone ever actually used the chips. qemu notionally supports the620, but since we don't actually have code to implement the segment table,...
target-ppc: Trivial cleanups in mmu_helper.c
This removes the never-used pte64_invalidate() function, and makesppcmas_tlb_check() static, since it's only used within that file.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Move SLB handling into a mmu-hash64.c
As a first step to disentangling the handling for 64-bit hash MMUs fromthe rest, we move the code handling the Segment Lookaside Buffer (SLB)(which only exists on 64-bit hash MMUs) into a new mmu-hash64.c file....
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-ppc: Add mechanism for synchronizing SPRs with KVM
Currently when runing under KVM on ppc, we synchronize a certain number ofvital SPRs to KVM through the SET_SREGS call. This leaves out quite a lotof important SPRs which are maintained in KVM. It would be helpful to...
target-ppc: Convert CPU definitions
Turn the array of model definitions into a set of self-registering QOMtypes with their own class_init. Unique identifiers are obtained fromthe combination of PVR, SVR and family identifiers; this requires allalias #defines to be removed from the list. Possibly there are some more...
target-ppc: Split out SO, OV, CA fields from XER
In preparation for more efficient setting of these fields.
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: Unify dcbzl code path
The bit that makes a dcbz instruction a dcbzl instruction was declared asreserved in ppc32 ISAs. However, hardware simply ignores the bit, makingcode valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.
Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,but only implemented it halfway correctly.
This patch adds support for
target-ppc: Slim conversion of model definitions to QOM subclasses
Since the model list is highly macrofied, keep ppc_def_t for now andsave a pointer to it in PowerPCCPUClass. This results in a flat list ofsubclasses including aliases, to be refined later....
fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
target-ppc: Don't use hwaddr to represent hardware state
The hwaddr type is somewhat vaguely defined as being able to contain busaddresses on the widest possible bus in the system. For that reason it'sdiscouraged for representing specific pieces of persistent hardware state,...
Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
ppc: add missing static
Add missing 'static' qualifiers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
target-ppc: make some functions static
Merge remote-tracking branch 'afaerber/qom-cpu' into staging
target-ppc: Rework storage of VPA registration state
We change the storage of the VPA information to explicitly use fixedsize integer types which will make life easier for syncing this data withKVM, which we will need in future.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
target-ppc: Extend FPU state for newer POWER CPUs
This patch adds some extra FPU state to CPUPPCState. Specifically,fpscr is extended to a target_ulong bits, since some recent (64 bit)CPUs now have more status bits than fit inside 32 bits. Also, we add...
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall
Adapt emulate_spapr_hypercall() accordingly.
Needed for changing spapr_hypercall() argument type to PowerPCCPU.
With PAPR guests, hypercalls allow registration of the Virtual ProcessorArea (VPA), SLB shadow and dispatch trace log (DTL), each of which allowfor certain communication between the guest and hypervisor. Currently, we...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-ppc: Remove unused power_mode field from cpu state
CPUPPCState includes a variable 'power_mode' which is used nowhere. Thispatch removes it. This includes saving a dummy zero in its place duringvmsave, to avoid breaking the save format.
PPC: BookE: Implement EPR SPR
On the e500 series, accessing SPR_EPR magically turns into an access atthat CPU's IACK register on the MPIC. Implement that logic to get kernelsthat make use of that feature work.
Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: BookE206: Bump MAS2 to 64bit
On 64bit capable systems, MAS2 can actually hold a 64bit virtual pageaddress. So increase the mask for its EPN.
PPC: Add some booke SPR defines
The number of SPRs avaiable in different PowerPC chip is still increasing. Adddefinitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
PPC: Add support for MSR_CM
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG tosupport running 64bit code with MSR_CM set.
ppc64: Rudimentary Support for extra page sizes on server CPUs
More recent Power server chips (i.e. based on the 64 bit hash MMU)support more than just the traditional 4k and 16M page sizes. Thiscan get quite complicated, because which page sizes are supported,...
ppc: Cleanup MMU merge
Remove useless wrappers. In some cases 'int' parameters arechanged to uint32_t.
Make internal functions static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>[agraf: fix kvm compilation]Signed-off-by: Alexander Graf <agraf@suse.de>...
ppc: Move exception helpers from helper.c to excp_helper.c
Move exception helpers from helper.c to excp_helper.c andmake cpu_dump_rfi() static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Let cpu_ppc_init() return PowerPCCPU
Adapt e500 mpc8544ds machine accordingly.
Turn cpu_init() into a static inline function returning CPUPPCState forbackwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>
target-ppc: QOM'ify CPU
Embed CPUPPCState as first member of PowerPCCPU.Distinguish between "powerpc-cpu", "powerpc64-cpu" and"embedded-powerpc-cpu".
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Drop cpu_ppc_close()
It is unused, so avoid QOM'ifying it unneededly.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: David Gibson <david@gibson.dropbear.id.au>
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC64: Add support for ldbrx and stdbrx instructions
These instructions for loading and storing byte-swapped 64-bit values havebeen introduced in PowerISA 2.06.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-ppc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
PPC: 405: Use proper CPU reset
On ppc405ep there is a register that allows for software to reset thecore, but not the whole system. Implement this reset using a resetinterrupt.
This gets rid of a bunch of #if 0'ed code.
Reported-by: Andreas Färber <afaerber@suse.de>...
PPC: E500: Add doorbell defines
We're going to introduce doorbell instructions (called processorcontrol in the spec) soon. Add some defines for easier patchreadability later.
PPC: Add CPU feature for processor control
We're soon going to implement processor control features. Add thefeature flag, so we're well prepared.
PPC: booke: add tlbnps handling
When using MAV 2.0 TLB registers, we have another range of TLB registersavailable to read the supported page sizes from.
Add SPR definitions for those and add a helper function that we can useto receive such a bitmap even when using MAV 1.0....
PPC: booke206: Check for TLB overrun
Our internal helpers to fetch TLB entries were not able to tell usthat an entry doesn't even exist. Pass an error out if we hit sucha case to not accidently pass beyond the TLB array.
PPC: E500: Add some more excp vectors
Our EXCP list is getting outdated. By now, 3 new exception vectors havebeen introduced. Update the list so we have everything at one place.
PPC: Add IVOR 38-42
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06from 38 - 42.
Signed-off-by: Alexander Graf <agraf@suse.de>Reviewed-by: Andreas Färber <afaerber@suse.de>
fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Alexander Graf <agraf@suse.de>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Blue Swirl <blauwirbel@gmail.com>...
ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate
The CPU state contains two bitmaps, initialized from the CPU specwhich describes which instructions are implemented on the CPU. Acouple of bits are defined which cover instructions (VSX and DFP)...
pseries: Correct vmx/dfp handling in both KVM and TCG cases
Currently, when KVM is enabled, the pseries machine checks if the hostCPU supports VMX, VSX and/or DFP instructions and advertisesaccordingly in the guest device tree. It does this regardless of what...
PPC: Bump qemu-system-ppc to 64-bit physical address space
Some 32-bit PPC CPUs can use up to 36 bit of physical address space.Treat them accordingly in the qemu-system-ppc binary type.
ppc: First cut implementation of -cpu host
For convenience with kvm, x86 allows the user to specify -cpu host on theqemu command line, which means make the guest cpu the same as the hostcpu. This patch implements the same option for ppc targets.
For now, this just read the host PVR (Processor Version Register) and...
PPC: booke timers
While working on the emulation of the freescale p2010 (e500v2) I realized thatthere's no implementation of booke's timers features. Currently mpc8544 usesppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (forexample booke uses different SPR)....
kvm: ppc: booke206: use MMU API
Share the TLB array with KVM. This allows us to set the initial TLBboth on initial boot and reset, is useful for debugging, and couldeventually be used to support migration.
Signed-off-by: Scott Wood <scottwood@freescale.com>...
ppc: booke206: add "info tlb" support
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages
This definition is backward compatible with MAV=1.0 as long asthe guest does not set reserved bits in MAS1/MAS4.
Also, fix the shift in booke206_tlb_to_page_size -- it's the basethat should be able to hold a 4G page size, not the shift count....
Implement POWER7's CFAR in TCG
This patch implements support for the CFAR SPR on POWER7 (Come FromAddress Register), which snapshots the PC value at the time of a branch oran rfid. The latest powerpc-next kernel also catches it and can show it inxmon or in the signal frames....
PPC: E500: Add ESR bit definitions
The BookE spec specifies a number of ESR bits. Add defines for themso we can use them later on.
Reported-by: Jason Wessel <jason.wessel@windriver.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
target-alpha, target-ppc: Remove unnecessary setjmp.h include
Remove the include of setjmp.h from the cpu.h of target-alphaand target-ppc. This is unnecessary because cpu-defs.h alreadyincludes this header; this change brings these two targetsinto line with all the rest....
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types andallocated that union. While it's a waste of memory (and cache) to allocateTLB information for a TLB type with much information when you only needlittle, it also inflicts another issue....
PPC: E500: Use MAS registers instead of internal TLB representation
The natural format for e500 cores to do TLB manipulation with are the MASregisters. Instead of converting them into some internal representationand back again when the guest reads them, we can just keep the data...
w32: Fix compilation and replace non-portable usage of ulong
ulong is undefined for w32 (and maybe other) compilations.Replace it by uintptr_t (which also fixes compilation for w64and is a better choice for pointer to integer conversions).
Cc: Aurelien Jarno <aurelien@aurel32.net>...
PPC: Add GS MSR definition
The BookE specification defines MSR bit 28 as Guest State. Add itto the list of MSR macros.
PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currentlyselected CPU emulation, we have a feature mask of what exactly the respectiveinstruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64...
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
monitor: add PPC BookE SPRs
Read them via KVM_GET_SREGS in kvm_arch_get_registers(),and display them in "info registers".
Also get CR and PID from the existing KVM_GET_REGS.
Fix typo in comment (embeded -> embedded)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Implement PAPR VPA functions for pSeries shared processor partitions
Shared-processor partitions are those where a CPU is time-sliced betweenpartitions, rather than being permanently dedicated to a singlepartition. qemu emulated partitions, since they are just scheduled with...
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't(quite) get the hash value for the ppc hashed page table. Instead itgets the hash shifted - effectively the offset of the hash bucket within...
Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()has a mix of common and 32 or 64 bit specific code. However thedivision is not done terribly well which results in a lot of messy codeflipping between common and divided paths....
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used onpowerpc MMUs were 256MB in size. This was the only option on all hashpage table based 32-bit powerpc cpus, and on the earlier 64-bit hash pagetable based cpus. However, newer 64-bit cpus also permit 1TB segments...
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's farfrom perfect - it's missing a number of POWER7 features so far, includingany support for VSX or decimal floating point instructions. However, it'sclose enough to boot a kernel with the POWER7 PVR....
Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full systempartitions, the guest does not have direct access to the hardware pagetable. Instead, the pagetable exists in hypervisor memory, and the guest...
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 isstoreed in a structure with the unhelpfully named fields 'tmp'and 'tmp64'. While the layout in these fields does match thedescription of the SLB in the architecture document, it is not...
Add a hook to allow hypercalls to be emulated on PowerPC
PowerPC and POWER chips since the POWER4 and 970 have a specialhypervisor mode, and a corresponding form of the system callinstruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. That...
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translationthrough the segment lookaside buffer. Likewise it supports theslbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions...
Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introducedin POWER5 (although it doesn't actually allow you to choose POWER5).
However, the logic is slightly incorrect: it will generate results...