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target-ppc: add support for extended mtfsf/mtfsfi forms
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a newW field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with...
powerpc: correctly handle fpu exceptions.
Raise the exception on the first occurence, do not wait for the nextfloating point operation.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: optimize fabs, fnabs, fneg
fabs, fnabs and fneg are just flipping the bit sign of an FP register,this can be implemented in TCG instead of using softfloat.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC/GDB: handle read and write of fpscr
Although the support of this register may be uncomplete, there are noreason to prevent the debugger from reading or writing it.
ppc: Add missing break
Add obviously missing 'break' statement.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Split FPU and SPE ops
Move FPU and SPE helpers from op_helper.c to fpu_helper.c.
ppc: Avoid AREG0 for FPU and SPE helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.