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cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
gdbstub: Change gdb_register_coprocessor() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
e600 core for MPC86xx processors
MPC86xx processors are based on the e600 core, which is not the casein qemu where it is based on the 7400 processor.
This patch creates the e600 core and instantiates the MPC86xxprocessors based on it. Therefore, adding the high BATs, the SPRG...
target-ppc: Add POWER8 v1.0 CPU model
This patch adds CPU PVR definition for POWER8,and enables QEMU to launch guests on POWER8 hardware.
Signed-off-by: Prerna Saxena
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org>...
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable inCPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Reviewed-by: Richard Henderson <rth@twiddle.net>...
PPC: Introduce an alias cache for faster lookups
When running QEMU with "-cpu ?" we walk through every alias for everytarget CPU we know about. This takes several seconds on my very fasthost system.
Let's introduce a class object cache in the alias table. Using that we...
PPC: Ignore writes to L2CR
The L2CR register contains a number of bits that either impose configurationwhich we can't deal with or mean "something is in progress until the bit is0 again".
Since we don't model the former and we do want to accomodate guests using the...
target-ppc: Introduce unrealizefn for PowerPCCPU
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Drop redundant flags assignments from CPU families
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in someplaces for macrofied assignment to insns_flags2 field.
PPC_NONE is defined as zero though and QOM classes are zero-initialized,...
ppc: do not register IABR SPR twice for 603e
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E().
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
target-ppc: Add read and write of PPR SPR
Recent Linux kernels save and restore the PPR across exceptionsso we need to handle it.
Signed-off-by: Anton Blanchard <anton@au1.ibm.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several propertieswith information about the L1 cache. We already create two of theseproperties, but with incorrect names - "[id]cache-block-size" instead...
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and anextra control register (MMCRA). This patch adds stub support for them to...
PPC: Remove env->hreset_excp_prefix
This value is not needed if we use correctly the MSR[IP] bit.
excp_prefix is always 0x00000000, except when the MSR[IP] bit isimplemented and set to 1, in that case excp_prefix is 0xfff00000.
The handling of MSR[IP] was already implemented but not used at reset...
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for systemreset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start...
PPC: Add breakpoint registers for 603 and e300
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Enable ISEL on POWER7
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7.Given this is trapped and emulated by the Linux kernel, I guess it wentunnoticed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
mmu-hash64: Implement Virtual Page Class Key Protection
Version 2.06 of the Power architecture describes an additional pageprotection mechanism. Each virtual page has a "class" (0-31) recorded inthe PTE. The AMR register contains bits which can prohibit reads and/or...
target-ppc: Use QOM method dispatch for MMU fault handling
After previous cleanups, the many scattered checks of env->mmu_model inthe ppc MMU implementation have, at least for "classic" hash MMUs beenreduced (almost) to a single switch at the top ofcpu_ppc_handle_mmu_fault()....
PPC/GDB: handle read and write of fpscr
Although the support of this register may be uncomplete, there are noreason to prevent the debugger from reading or writing it.
target-ppc: Remove vestigial PowerPC 620 support
The PowerPC 620 was the very first 64-bit PowerPC implementation, buthardly anyone ever actually used the chips. qemu notionally supports the620, but since we don't actually have code to implement the segment table,...
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-ppc: Fix PPC_DUMP_SPR_ACCESS build
A victim of the d523dd00a7d73b28f2e99acf45a4b3f92e56e40a AREG0conversion, insert the missing cpu_env arguments.
target-ppc: Make host CPU a subclass of the host's CPU model
This avoids assigning individual class fields and contributorsforgetting to add field assignments in KVM-only code.
ppc_cpu_class_find_by_pvr() requires the CPU model classes to beregistered, so defer host CPU type registration to kvm_arch_init()....
target-ppc: List alias names alongside CPU models
Revert adding a separate -cpu ? output section for aliases and list themper CPU subclass.
Requested-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Report CPU aliases for QMP
The QMP query-cpu-definitions implementation iterated over CPU classesonly, which were getting less and less as aliases were extracted.
Keep them in QMP as valid -cpu arguments even if not guaranteed stable.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Move CPU aliases out of translate_init.c
Move array of CPU aliases to cpu-models.c, alongside model definitions.This requires to zero-terminate the aliases array since ARRAY_SIZE() canno longer be used in translate_init.c then.
Suggested-by: Alexander Graf <agraf@suse.de>...
target-ppc: Turn descriptive CPU model comments into device descriptions
Fix microcontroller typo while at it.
target-ppc: Update Coding Style for CPU models
Drop the space in #if defined (TODO).
target-ppc: Split model definitions out of translate_init.c
Now that model definitions only reference their parent type, modeldefinitions are independent of the family definitions and can becompiled independently of TCG translation.
Keep all #if defined(TODO) code local to cpu-models.c....
target-ppc: Change "POWER7" CPU alias
Let it resolve to v2.3 rather than v2.0.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add mechanism for synchronizing SPRs with KVM
Currently when runing under KVM on ppc, we synchronize a certain number ofvital SPRs to KVM through the SET_SREGS call. This leaves out quite a lotof important SPRs which are maintained in KVM. It would be helpful to...
target-ppc: Convert CPU definitions
Turn the array of model definitions into a set of self-registering QOMtypes with their own class_init. Unique identifiers are obtained fromthe combination of PVR, SVR and family identifiers; this requires allalias #defines to be removed from the list. Possibly there are some more...
target-ppc: Introduce abstract CPU family types
Instead of assigning *_<family> constants, set .parent to a family type.
Introduce a POWERPC_FAMILY() macro to keep type registration close toits implementation. This macro will need tweaking later.
target-ppc: Set instruction flags on CPU family classes
target-ppc: Register all types for TARGET_PPCEMB
Don't attempt to suppress registration of CPU types, since the criteriais actually a property of the class and should thus become a field.Since we can't check a field set in a class_init function beforeregistering the type that leads to execution of that function, guard the...
target-ppc: Set remaining fields on CPU family classes
Now POWERPC_DEF_SVR() no longer sets family-specific fields itself.
target-ppc: Turn descriptive CPU family comments into device descriptions
This gets rid of some more overly long comments that have lost most oftheir purpose now that in most cases there's only two functions left perCPU family.
The class field is inherited by the actual CPU models, so override it....
target-ppc: Extract 970 aliases
target-ppc: Extract POWER7 alias
target-ppc: Get model name from type name
We are about to drop the redundant name field along with ppc_def_t.
target-ppc: Extract MPC82xx_HiP{3, 4} aliases
target-ppc: Extract MPC52xx alias
target-ppc: Extract MPC5200/MPC5200B aliases
target-ppc: Extract MPC8240 alias
target-ppc: Extract 405GPe alias
target-ppc: Extract 604e alias
target-ppc: Extract MPC85xx aliases
target-ppc: Extract e500v1/e500v2 aliases
target-ppc: Extract MPC83xx aliases
target-ppc: Extract e300 alias
target-ppc: Extract e200 alias
target-ppc: Extract MPC82xx alias
target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliases
This depends on the fix for "G2leGP3" PVR.
target-ppc: Extract MPC82xx aliases to *_HiP4
target-ppc: Extract 7410 alias
target-ppc: Extract 7400 alias
target-ppc: Extract 7x5 aliases
target-ppc: Extract 750 aliases
target-ppc: Extract 740/750 aliases
target-ppc: Extract 603e alias
target-ppc: Extract 603r alias
target-ppc: Extract 601/601v aliases
target-ppc: Extract MGT823/MPC8xx as aliases
They used different PVRs but were defined to MPC8xx.
target-ppc: Extract 40x aliases
target-ppc: Extract 440 aliases
target-ppc: Turn "ppc32" and "ppc64" CPUs into aliases
target-ppc: Extract 74x7[A] aliases
target-ppc: Extract 74x5 as aliases
target-ppc: Extract 74x1 aliases
target-ppc: Extract 7450 alias
target-ppc: Extract 7448 alias
target-ppc: Update error handling in ppc_cpu_realize()
Commit fe828a4d4b7a5617cda7b24e95e327bfb71d790e added a new fatal errormessage while QOM realize'ification was in flight.
Convert it to return an Error instead of exit()ing.
target-ppc: Drop nested TARGET_PPC64 guard for POWER7
It is within a large TARGET_PPC64 section from 970 to 620,so an #endif /* TARGET_PPC64 */ is confusing. Clean this up.
target-ppc: Inline comma into POWERPC_DEF_SVR() macro
To repurpose the POWERPC_DEF_SVR() macro outside of an array,move the comma into the macro. No functional change.
target-ppc: Extract aliases from definitions list
Move definitions that were 100% identical except for the name into alist of aliases so that we don't register duplicate CPU types.Drop the accompanying comments since they don't really add value.
We need to support recursive lookup due to code names referencing a...
target-ppc: Make -cpu "ppc" an alias to "ppc32"
Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64.If we ever want to change it, we can more easily do so now.
target-ppc: Extract MPC5xx aliases
Their PVR differed but was defined to MPC5xx.
target-ppc: Fix CPU_POWERPC_MPC8547E
It was defined to ..._MPC8545E_v21 rather than ..._MPC8547E_v21.Due to both resolving to CPU_POWERPC_e500v2_v21 this did not show.
Fixing this nontheless helps with QOM'ifying CPU aliases.
target-ppc: Fix "G2leGP3" PVR
Unlike derived PVR constants mapped to CPU_POWERPC_G2LEgp3, the"G2leGP3" model definition itself used the CPU_POWERPC_G2LEgp1 PVR.
Fixing this will allow to alias CPU_POWERPC_G2LEgp3-using types to"G2leGP3".
target-ppc: Split out SO, OV, CA fields from XER
In preparation for more efficient setting of these fields.
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-ppc: Move TCG initialization to PowerPCCPU initfn
Ensures that a QOM-created PowerPCCPU is usable.
target-ppc: Update PowerPCCPU to QOM realizefn
Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and setrealized = true in cpu_ppc_init().
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
error: Strip trailing '\n' from error string arguments (again)
Commit 6daf194d and be62a2eb got rid of a bunch, but they keep comingback. Tracked down with this Coccinelle semantic patch:
r expression err, eno, cls, fmt; position p; @@ (...
r
cpu: do not use object_delete
CPUs are never added to the composition tree, so delete is achievedsimply by removing the last references to them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
PPC: Unify dcbzl code path
The bit that makes a dcbz instruction a dcbzl instruction was declared asreserved in ppc32 ISAs. However, hardware simply ignores the bit, makingcode valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.
Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
cpu: Add model resolution support to CPUClass
Introduce CPUClass::class_by_name and add a default implementation.Hook up the alpha and ppc implementations.
Introduce a wrapper function cpu_class_by_name().
target-ppc: Give a meaningful error if too many threads are specified
Currently the target-ppc tcg code only supports a single thread. You canspecify more, but they're treated identically to multiple cores. On KVMwe obviously can't support more threads than the hardware; if more are...
PPC: Provide zero SVR for -cpu e500mc and e5500
Even though our -cpu types for e500mc and e5500 are no real CPUs thatactually have version registers, a guest might still want to accesssaid version register and that has to succeed for a guest to be happy....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,but only implemented it halfway correctly.
This patch adds support for
target-ppc: Slim conversion of model definitions to QOM subclasses
Since the model list is highly macrofied, keep ppc_def_t for now andsave a pointer to it in PowerPCCPUClass. This results in a flat list ofsubclasses including aliases, to be refined later....