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/*
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 * QEMU MicroBlaze CPU
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 *
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 * Copyright (c) 2009 Edgar E. Iglesias
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 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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 * Copyright (c) 2012 SUSE LINUX Products GmbH
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2.1 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see
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 * <http://www.gnu.org/licenses/lgpl-2.1.html>
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 */
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#include "cpu.h"
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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static void mb_cpu_set_pc(CPUState *cs, vaddr value)
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{
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    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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    cpu->env.sregs[SR_PC] = value;
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}
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/* CPUClass::reset() */
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static void mb_cpu_reset(CPUState *s)
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{
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    MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
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    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
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    CPUMBState *env = &cpu->env;
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    mcc->parent_reset(s);
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    memset(env, 0, offsetof(CPUMBState, breakpoints));
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    env->res_addr = RES_ADDR_NONE;
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    tlb_flush(env, 1);
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    /* Disable stack protector.  */
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    env->shr = ~0;
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    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
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                       | PVR0_USE_BARREL_MASK \
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                       | PVR0_USE_DIV_MASK \
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                       | PVR0_USE_HW_MUL_MASK \
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                       | PVR0_USE_EXC_MASK \
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                       | PVR0_USE_ICACHE_MASK \
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                       | PVR0_USE_DCACHE_MASK \
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                       | PVR0_USE_MMU \
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                       | (0xb << 8);
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    env->pvr.regs[2] = PVR2_D_OPB_MASK \
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                        | PVR2_D_LMB_MASK \
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                        | PVR2_I_OPB_MASK \
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                        | PVR2_I_LMB_MASK \
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                        | PVR2_USE_MSR_INSTR \
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                        | PVR2_USE_PCMP_INSTR \
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                        | PVR2_USE_BARREL_MASK \
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                        | PVR2_USE_DIV_MASK \
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                        | PVR2_USE_HW_MUL_MASK \
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                        | PVR2_USE_MUL64_MASK \
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                        | PVR2_USE_FPU_MASK \
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                        | PVR2_USE_FPU2_MASK \
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                        | PVR2_FPU_EXC_MASK \
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                        | 0;
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    env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
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    env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
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#if defined(CONFIG_USER_ONLY)
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    /* start in user mode with interrupts enabled.  */
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    env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
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    env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
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#else
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    env->sregs[SR_MSR] = 0;
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    mmu_init(&env->mmu);
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    env->mmu.c_mmu = 3;
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    env->mmu.c_mmu_tlb_access = 3;
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    env->mmu.c_mmu_zones = 16;
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#endif
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}
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static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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    MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
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    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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    cpu_reset(CPU(cpu));
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    mcc->parent_realize(dev, errp);
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}
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static void mb_cpu_initfn(Object *obj)
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{
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    CPUState *cs = CPU(obj);
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    MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
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    CPUMBState *env = &cpu->env;
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    static bool tcg_initialized;
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    cs->env_ptr = env;
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    cpu_exec_init(env);
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    set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
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    if (tcg_enabled() && !tcg_initialized) {
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        tcg_initialized = true;
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        mb_tcg_init();
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    }
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}
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static const VMStateDescription vmstate_mb_cpu = {
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    .name = "cpu",
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    .unmigratable = 1,
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};
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static Property mb_properties[] = {
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    DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void mb_cpu_class_init(ObjectClass *oc, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(oc);
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    CPUClass *cc = CPU_CLASS(oc);
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    MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
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    mcc->parent_realize = dc->realize;
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    dc->realize = mb_cpu_realizefn;
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    mcc->parent_reset = cc->reset;
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    cc->reset = mb_cpu_reset;
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    cc->do_interrupt = mb_cpu_do_interrupt;
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    cc->dump_state = mb_cpu_dump_state;
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    cc->set_pc = mb_cpu_set_pc;
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    cc->gdb_read_register = mb_cpu_gdb_read_register;
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    cc->gdb_write_register = mb_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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    cc->do_unassigned_access = mb_cpu_unassigned_access;
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    cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
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#endif
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    dc->vmsd = &vmstate_mb_cpu;
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    dc->props = mb_properties;
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    cc->gdb_num_core_regs = 32 + 5;
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}
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static const TypeInfo mb_cpu_type_info = {
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    .name = TYPE_MICROBLAZE_CPU,
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    .parent = TYPE_CPU,
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    .instance_size = sizeof(MicroBlazeCPU),
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    .instance_init = mb_cpu_initfn,
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    .class_size = sizeof(MicroBlazeCPUClass),
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    .class_init = mb_cpu_class_init,
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};
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static void mb_cpu_register_types(void)
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{
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    type_register_static(&mb_cpu_type_info);
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}
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type_init(mb_cpu_register_types)