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/*
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 *  PowerPC CPU initialization for qemu.
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 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *  Copyright 2011 Freescale Semiconductor, Inc.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "disas/bfd.h"
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#include "exec/gdbstub.h"
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#include <sysemu/kvm.h>
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#include "kvm_ppc.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/cpus.h"
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#include "cpu-models.h"
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#include "mmu-hash32.h"
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#include "mmu-hash64.h"
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//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DUMP_SPR_ACCESSES
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35
/* For user-mode emulation, we don't emulate any IRQ controller */
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#if defined(CONFIG_USER_ONLY)
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#define PPC_IRQ_INIT_FN(name)                                                 \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
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{                                                                             \
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}
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#else
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#define PPC_IRQ_INIT_FN(name)                                                 \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
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PPC_IRQ_INIT_FN(40x);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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PPC_IRQ_INIT_FN(POWER7);
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PPC_IRQ_INIT_FN(e500);
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/* Generic callbacks:
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 * do nothing but store/retrieve spr value
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 */
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static void spr_load_dump_spr(int sprn)
56
{
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#ifdef PPC_DUMP_SPR_ACCESSES
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    TCGv_i32 t0 = tcg_const_i32(sprn);
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    gen_helper_load_dump_spr(cpu_env, t0);
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    tcg_temp_free_i32(t0);
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#endif
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}
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static void spr_read_generic (void *opaque, int gprn, int sprn)
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{
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    gen_load_spr(cpu_gpr[gprn], sprn);
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    spr_load_dump_spr(sprn);
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}
69

    
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static void spr_store_dump_spr(int sprn)
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{
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#ifdef PPC_DUMP_SPR_ACCESSES
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    TCGv_i32 t0 = tcg_const_i32(sprn);
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    gen_helper_store_dump_spr(cpu_env, t0);
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    tcg_temp_free_i32(t0);
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#endif
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}
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static void spr_write_generic (void *opaque, int sprn, int gprn)
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{
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    gen_store_spr(sprn, cpu_gpr[gprn]);
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    spr_store_dump_spr(sprn);
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}
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85
#if !defined(CONFIG_USER_ONLY)
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static void spr_write_generic32(void *opaque, int sprn, int gprn)
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{
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#ifdef TARGET_PPC64
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    TCGv t0 = tcg_temp_new();
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    tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
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    gen_store_spr(sprn, t0);
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    tcg_temp_free(t0);
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    spr_store_dump_spr(sprn);
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#else
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    spr_write_generic(opaque, sprn, gprn);
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#endif
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}
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99
static void spr_write_clear (void *opaque, int sprn, int gprn)
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{
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    TCGv t0 = tcg_temp_new();
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    TCGv t1 = tcg_temp_new();
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    gen_load_spr(t0, sprn);
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    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
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    tcg_gen_and_tl(t0, t0, t1);
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    gen_store_spr(sprn, t0);
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    tcg_temp_free(t0);
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    tcg_temp_free(t1);
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}
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#endif
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/* SPR common to all PowerPC */
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/* XER */
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static void spr_read_xer (void *opaque, int gprn, int sprn)
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{
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    gen_read_xer(cpu_gpr[gprn]);
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}
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119
static void spr_write_xer (void *opaque, int sprn, int gprn)
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{
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    gen_write_xer(cpu_gpr[gprn]);
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}
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124
/* LR */
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static void spr_read_lr (void *opaque, int gprn, int sprn)
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{
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    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
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}
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130
static void spr_write_lr (void *opaque, int sprn, int gprn)
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{
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    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
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}
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/* CFAR */
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static void spr_read_cfar (void *opaque, int gprn, int sprn)
138
{
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    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
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}
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static void spr_write_cfar (void *opaque, int sprn, int gprn)
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{
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    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
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}
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#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
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148
/* CTR */
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static void spr_read_ctr (void *opaque, int gprn, int sprn)
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{
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    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
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}
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static void spr_write_ctr (void *opaque, int sprn, int gprn)
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{
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    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
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}
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/* User read access to SPR */
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/* USPRx */
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/* UMMCRx */
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/* UPMCx */
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/* USIA */
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/* UDECR */
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static void spr_read_ureg (void *opaque, int gprn, int sprn)
166
{
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    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
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}
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/* SPR common to all non-embedded PowerPC */
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/* DECR */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_decr (void *opaque, int gprn, int sprn)
174
{
175
    if (use_icount) {
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        gen_io_start();
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    }
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    gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
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    if (use_icount) {
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        gen_io_end();
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        gen_stop_exception(opaque);
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    }
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}
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static void spr_write_decr (void *opaque, int sprn, int gprn)
186
{
187
    if (use_icount) {
188
        gen_io_start();
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    }
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    gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
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    if (use_icount) {
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        gen_io_end();
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        gen_stop_exception(opaque);
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    }
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}
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#endif
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/* SPR common to all non-embedded PowerPC, except 601 */
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/* Time base */
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static void spr_read_tbl (void *opaque, int gprn, int sprn)
201
{
202
    if (use_icount) {
203
        gen_io_start();
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    }
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    gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
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    if (use_icount) {
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        gen_io_end();
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        gen_stop_exception(opaque);
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    }
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}
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static void spr_read_tbu (void *opaque, int gprn, int sprn)
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{
214
    if (use_icount) {
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        gen_io_start();
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    }
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    gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
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    if (use_icount) {
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        gen_io_end();
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        gen_stop_exception(opaque);
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    }
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}
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__attribute__ (( unused ))
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static void spr_read_atbl (void *opaque, int gprn, int sprn)
226
{
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    gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
228
}
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__attribute__ (( unused ))
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static void spr_read_atbu (void *opaque, int gprn, int sprn)
232
{
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    gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
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}
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_tbl (void *opaque, int sprn, int gprn)
238
{
239
    if (use_icount) {
240
        gen_io_start();
241
    }
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    gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
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    if (use_icount) {
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        gen_io_end();
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        gen_stop_exception(opaque);
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    }
247
}
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static void spr_write_tbu (void *opaque, int sprn, int gprn)
250
{
251
    if (use_icount) {
252
        gen_io_start();
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    }
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    gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
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    if (use_icount) {
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        gen_io_end();
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        gen_stop_exception(opaque);
258
    }
259
}
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__attribute__ (( unused ))
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static void spr_write_atbl (void *opaque, int sprn, int gprn)
263
{
264
    gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
265
}
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267
__attribute__ (( unused ))
268
static void spr_write_atbu (void *opaque, int sprn, int gprn)
269
{
270
    gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
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}
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273
#if defined(TARGET_PPC64)
274
__attribute__ (( unused ))
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static void spr_read_purr (void *opaque, int gprn, int sprn)
276
{
277
    gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
278
}
279
#endif
280
#endif
281

    
282
#if !defined(CONFIG_USER_ONLY)
283
/* IBAT0U...IBAT0U */
284
/* IBAT0L...IBAT7L */
285
static void spr_read_ibat (void *opaque, int gprn, int sprn)
286
{
287
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
288
}
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290
static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
291
{
292
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
293
}
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295
static void spr_write_ibatu (void *opaque, int sprn, int gprn)
296
{
297
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
298
    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
299
    tcg_temp_free_i32(t0);
300
}
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302
static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
303
{
304
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
305
    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
306
    tcg_temp_free_i32(t0);
307
}
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309
static void spr_write_ibatl (void *opaque, int sprn, int gprn)
310
{
311
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
312
    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
313
    tcg_temp_free_i32(t0);
314
}
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316
static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
317
{
318
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
319
    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
320
    tcg_temp_free_i32(t0);
321
}
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323
/* DBAT0U...DBAT7U */
324
/* DBAT0L...DBAT7L */
325
static void spr_read_dbat (void *opaque, int gprn, int sprn)
326
{
327
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
328
}
329

    
330
static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
331
{
332
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
333
}
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335
static void spr_write_dbatu (void *opaque, int sprn, int gprn)
336
{
337
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
338
    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
339
    tcg_temp_free_i32(t0);
340
}
341

    
342
static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
343
{
344
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
345
    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
346
    tcg_temp_free_i32(t0);
347
}
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349
static void spr_write_dbatl (void *opaque, int sprn, int gprn)
350
{
351
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
352
    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
353
    tcg_temp_free_i32(t0);
354
}
355

    
356
static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
357
{
358
    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
359
    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
360
    tcg_temp_free_i32(t0);
361
}
362

    
363
/* SDR1 */
364
static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
365
{
366
    gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
367
}
368

    
369
/* 64 bits PowerPC specific SPRs */
370
#if defined(TARGET_PPC64)
371
static void spr_read_hior (void *opaque, int gprn, int sprn)
372
{
373
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
374
}
375

    
376
static void spr_write_hior (void *opaque, int sprn, int gprn)
377
{
378
    TCGv t0 = tcg_temp_new();
379
    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
380
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
381
    tcg_temp_free(t0);
382
}
383
#endif
384
#endif
385

    
386
/* PowerPC 601 specific registers */
387
/* RTC */
388
static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
389
{
390
    gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
391
}
392

    
393
static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
394
{
395
    gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
396
}
397

    
398
#if !defined(CONFIG_USER_ONLY)
399
static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
400
{
401
    gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
402
}
403

    
404
static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
405
{
406
    gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
407
}
408

    
409
static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
410
{
411
    DisasContext *ctx = opaque;
412

    
413
    gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
414
    /* Must stop the translation as endianness may have changed */
415
    gen_stop_exception(ctx);
416
}
417
#endif
418

    
419
/* Unified bats */
420
#if !defined(CONFIG_USER_ONLY)
421
static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
422
{
423
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
424
}
425

    
426
static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
427
{
428
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
429
    gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
430
    tcg_temp_free_i32(t0);
431
}
432

    
433
static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
434
{
435
    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
436
    gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
437
    tcg_temp_free_i32(t0);
438
}
439
#endif
440

    
441
/* PowerPC 40x specific registers */
442
#if !defined(CONFIG_USER_ONLY)
443
static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
444
{
445
    gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
446
}
447

    
448
static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
449
{
450
    gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
451
}
452

    
453
static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
454
{
455
    DisasContext *ctx = opaque;
456

    
457
    gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
458
    /* We must stop translation as we may have rebooted */
459
    gen_stop_exception(ctx);
460
}
461

    
462
static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
463
{
464
    gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
465
}
466

    
467
static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
468
{
469
    gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
470
}
471

    
472
static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
473
{
474
    gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
475
}
476
#endif
477

    
478
/* PowerPC 403 specific registers */
479
/* PBL1 / PBU1 / PBL2 / PBU2 */
480
#if !defined(CONFIG_USER_ONLY)
481
static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
482
{
483
    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
484
}
485

    
486
static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
487
{
488
    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
489
    gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
490
    tcg_temp_free_i32(t0);
491
}
492

    
493
static void spr_write_pir (void *opaque, int sprn, int gprn)
494
{
495
    TCGv t0 = tcg_temp_new();
496
    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
497
    gen_store_spr(SPR_PIR, t0);
498
    tcg_temp_free(t0);
499
}
500
#endif
501

    
502
/* SPE specific registers */
503
static void spr_read_spefscr (void *opaque, int gprn, int sprn)
504
{
505
    TCGv_i32 t0 = tcg_temp_new_i32();
506
    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
507
    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
508
    tcg_temp_free_i32(t0);
509
}
510

    
511
static void spr_write_spefscr (void *opaque, int sprn, int gprn)
512
{
513
    TCGv_i32 t0 = tcg_temp_new_i32();
514
    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515
    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
516
    tcg_temp_free_i32(t0);
517
}
518

    
519
#if !defined(CONFIG_USER_ONLY)
520
/* Callback used to write the exception vector base */
521
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
522
{
523
    TCGv t0 = tcg_temp_new();
524
    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
525
    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
526
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
527
    gen_store_spr(sprn, t0);
528
    tcg_temp_free(t0);
529
}
530

    
531
static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
532
{
533
    DisasContext *ctx = opaque;
534
    int sprn_offs;
535

    
536
    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
537
        sprn_offs = sprn - SPR_BOOKE_IVOR0;
538
    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
539
        sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
540
    } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
541
        sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
542
    } else {
543
        printf("Trying to write an unknown exception vector %d %03x\n",
544
               sprn, sprn);
545
        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
546
        return;
547
    }
548

    
549
    TCGv t0 = tcg_temp_new();
550
    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
551
    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
552
    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
553
    gen_store_spr(sprn, t0);
554
    tcg_temp_free(t0);
555
}
556
#endif
557

    
558
static inline void vscr_init (CPUPPCState *env, uint32_t val)
559
{
560
    env->vscr = val;
561
    /* Altivec always uses round-to-nearest */
562
    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
563
    set_flush_to_zero(vscr_nj, &env->vec_status);
564
}
565

    
566
#ifdef CONFIG_USER_ONLY
567
#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
568
                         oea_read, oea_write, one_reg_id, initial_value)       \
569
    _spr_register(env, num, name, uea_read, uea_write, initial_value)
570
#else
571
#if !defined(CONFIG_KVM)
572
#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
573
                         oea_read, oea_write, one_reg_id, initial_value) \
574
    _spr_register(env, num, name, uea_read, uea_write,                         \
575
                  oea_read, oea_write, initial_value)
576
#else
577
#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
578
                         oea_read, oea_write, one_reg_id, initial_value) \
579
    _spr_register(env, num, name, uea_read, uea_write,                         \
580
                  oea_read, oea_write, one_reg_id, initial_value)
581
#endif
582
#endif
583

    
584
#define spr_register(env, num, name, uea_read, uea_write,                      \
585
                     oea_read, oea_write, initial_value)                       \
586
    spr_register_kvm(env, num, name, uea_read, uea_write,                      \
587
                     oea_read, oea_write, 0, initial_value)
588

    
589
static inline void _spr_register(CPUPPCState *env, int num,
590
                                 const char *name,
591
                                 void (*uea_read)(void *opaque, int gprn, int sprn),
592
                                 void (*uea_write)(void *opaque, int sprn, int gprn),
593
#if !defined(CONFIG_USER_ONLY)
594

    
595
                                 void (*oea_read)(void *opaque, int gprn, int sprn),
596
                                 void (*oea_write)(void *opaque, int sprn, int gprn),
597
#endif
598
#if defined(CONFIG_KVM)
599
                                 uint64_t one_reg_id,
600
#endif
601
                                 target_ulong initial_value)
602
{
603
    ppc_spr_t *spr;
604

    
605
    spr = &env->spr_cb[num];
606
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
607
#if !defined(CONFIG_USER_ONLY)
608
        spr->oea_read != NULL || spr->oea_write != NULL ||
609
#endif
610
        spr->uea_read != NULL || spr->uea_write != NULL) {
611
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612
        exit(1);
613
    }
614
#if defined(PPC_DEBUG_SPR)
615
    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616
           name, initial_value);
617
#endif
618
    spr->name = name;
619
    spr->uea_read = uea_read;
620
    spr->uea_write = uea_write;
621
#if !defined(CONFIG_USER_ONLY)
622
    spr->oea_read = oea_read;
623
    spr->oea_write = oea_write;
624
#endif
625
    env->spr[num] = initial_value;
626
}
627

    
628
/* Generic PowerPC SPRs */
629
static void gen_spr_generic (CPUPPCState *env)
630
{
631
    /* Integer processing */
632
    spr_register(env, SPR_XER, "XER",
633
                 &spr_read_xer, &spr_write_xer,
634
                 &spr_read_xer, &spr_write_xer,
635
                 0x00000000);
636
    /* Branch contol */
637
    spr_register(env, SPR_LR, "LR",
638
                 &spr_read_lr, &spr_write_lr,
639
                 &spr_read_lr, &spr_write_lr,
640
                 0x00000000);
641
    spr_register(env, SPR_CTR, "CTR",
642
                 &spr_read_ctr, &spr_write_ctr,
643
                 &spr_read_ctr, &spr_write_ctr,
644
                 0x00000000);
645
    /* Interrupt processing */
646
    spr_register(env, SPR_SRR0, "SRR0",
647
                 SPR_NOACCESS, SPR_NOACCESS,
648
                 &spr_read_generic, &spr_write_generic,
649
                 0x00000000);
650
    spr_register(env, SPR_SRR1, "SRR1",
651
                 SPR_NOACCESS, SPR_NOACCESS,
652
                 &spr_read_generic, &spr_write_generic,
653
                 0x00000000);
654
    /* Processor control */
655
    spr_register(env, SPR_SPRG0, "SPRG0",
656
                 SPR_NOACCESS, SPR_NOACCESS,
657
                 &spr_read_generic, &spr_write_generic,
658
                 0x00000000);
659
    spr_register(env, SPR_SPRG1, "SPRG1",
660
                 SPR_NOACCESS, SPR_NOACCESS,
661
                 &spr_read_generic, &spr_write_generic,
662
                 0x00000000);
663
    spr_register(env, SPR_SPRG2, "SPRG2",
664
                 SPR_NOACCESS, SPR_NOACCESS,
665
                 &spr_read_generic, &spr_write_generic,
666
                 0x00000000);
667
    spr_register(env, SPR_SPRG3, "SPRG3",
668
                 SPR_NOACCESS, SPR_NOACCESS,
669
                 &spr_read_generic, &spr_write_generic,
670
                 0x00000000);
671
}
672

    
673
/* SPR common to all non-embedded PowerPC, including 601 */
674
static void gen_spr_ne_601 (CPUPPCState *env)
675
{
676
    /* Exception processing */
677
    spr_register_kvm(env, SPR_DSISR, "DSISR",
678
                     SPR_NOACCESS, SPR_NOACCESS,
679
                     &spr_read_generic, &spr_write_generic,
680
                     KVM_REG_PPC_DSISR, 0x00000000);
681
    spr_register_kvm(env, SPR_DAR, "DAR",
682
                     SPR_NOACCESS, SPR_NOACCESS,
683
                     &spr_read_generic, &spr_write_generic,
684
                     KVM_REG_PPC_DAR, 0x00000000);
685
    /* Timer */
686
    spr_register(env, SPR_DECR, "DECR",
687
                 SPR_NOACCESS, SPR_NOACCESS,
688
                 &spr_read_decr, &spr_write_decr,
689
                 0x00000000);
690
    /* Memory management */
691
    spr_register(env, SPR_SDR1, "SDR1",
692
                 SPR_NOACCESS, SPR_NOACCESS,
693
                 &spr_read_generic, &spr_write_sdr1,
694
                 0x00000000);
695
}
696

    
697
/* BATs 0-3 */
698
static void gen_low_BATs (CPUPPCState *env)
699
{
700
#if !defined(CONFIG_USER_ONLY)
701
    spr_register(env, SPR_IBAT0U, "IBAT0U",
702
                 SPR_NOACCESS, SPR_NOACCESS,
703
                 &spr_read_ibat, &spr_write_ibatu,
704
                 0x00000000);
705
    spr_register(env, SPR_IBAT0L, "IBAT0L",
706
                 SPR_NOACCESS, SPR_NOACCESS,
707
                 &spr_read_ibat, &spr_write_ibatl,
708
                 0x00000000);
709
    spr_register(env, SPR_IBAT1U, "IBAT1U",
710
                 SPR_NOACCESS, SPR_NOACCESS,
711
                 &spr_read_ibat, &spr_write_ibatu,
712
                 0x00000000);
713
    spr_register(env, SPR_IBAT1L, "IBAT1L",
714
                 SPR_NOACCESS, SPR_NOACCESS,
715
                 &spr_read_ibat, &spr_write_ibatl,
716
                 0x00000000);
717
    spr_register(env, SPR_IBAT2U, "IBAT2U",
718
                 SPR_NOACCESS, SPR_NOACCESS,
719
                 &spr_read_ibat, &spr_write_ibatu,
720
                 0x00000000);
721
    spr_register(env, SPR_IBAT2L, "IBAT2L",
722
                 SPR_NOACCESS, SPR_NOACCESS,
723
                 &spr_read_ibat, &spr_write_ibatl,
724
                 0x00000000);
725
    spr_register(env, SPR_IBAT3U, "IBAT3U",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_ibat, &spr_write_ibatu,
728
                 0x00000000);
729
    spr_register(env, SPR_IBAT3L, "IBAT3L",
730
                 SPR_NOACCESS, SPR_NOACCESS,
731
                 &spr_read_ibat, &spr_write_ibatl,
732
                 0x00000000);
733
    spr_register(env, SPR_DBAT0U, "DBAT0U",
734
                 SPR_NOACCESS, SPR_NOACCESS,
735
                 &spr_read_dbat, &spr_write_dbatu,
736
                 0x00000000);
737
    spr_register(env, SPR_DBAT0L, "DBAT0L",
738
                 SPR_NOACCESS, SPR_NOACCESS,
739
                 &spr_read_dbat, &spr_write_dbatl,
740
                 0x00000000);
741
    spr_register(env, SPR_DBAT1U, "DBAT1U",
742
                 SPR_NOACCESS, SPR_NOACCESS,
743
                 &spr_read_dbat, &spr_write_dbatu,
744
                 0x00000000);
745
    spr_register(env, SPR_DBAT1L, "DBAT1L",
746
                 SPR_NOACCESS, SPR_NOACCESS,
747
                 &spr_read_dbat, &spr_write_dbatl,
748
                 0x00000000);
749
    spr_register(env, SPR_DBAT2U, "DBAT2U",
750
                 SPR_NOACCESS, SPR_NOACCESS,
751
                 &spr_read_dbat, &spr_write_dbatu,
752
                 0x00000000);
753
    spr_register(env, SPR_DBAT2L, "DBAT2L",
754
                 SPR_NOACCESS, SPR_NOACCESS,
755
                 &spr_read_dbat, &spr_write_dbatl,
756
                 0x00000000);
757
    spr_register(env, SPR_DBAT3U, "DBAT3U",
758
                 SPR_NOACCESS, SPR_NOACCESS,
759
                 &spr_read_dbat, &spr_write_dbatu,
760
                 0x00000000);
761
    spr_register(env, SPR_DBAT3L, "DBAT3L",
762
                 SPR_NOACCESS, SPR_NOACCESS,
763
                 &spr_read_dbat, &spr_write_dbatl,
764
                 0x00000000);
765
    env->nb_BATs += 4;
766
#endif
767
}
768

    
769
/* BATs 4-7 */
770
static void gen_high_BATs (CPUPPCState *env)
771
{
772
#if !defined(CONFIG_USER_ONLY)
773
    spr_register(env, SPR_IBAT4U, "IBAT4U",
774
                 SPR_NOACCESS, SPR_NOACCESS,
775
                 &spr_read_ibat_h, &spr_write_ibatu_h,
776
                 0x00000000);
777
    spr_register(env, SPR_IBAT4L, "IBAT4L",
778
                 SPR_NOACCESS, SPR_NOACCESS,
779
                 &spr_read_ibat_h, &spr_write_ibatl_h,
780
                 0x00000000);
781
    spr_register(env, SPR_IBAT5U, "IBAT5U",
782
                 SPR_NOACCESS, SPR_NOACCESS,
783
                 &spr_read_ibat_h, &spr_write_ibatu_h,
784
                 0x00000000);
785
    spr_register(env, SPR_IBAT5L, "IBAT5L",
786
                 SPR_NOACCESS, SPR_NOACCESS,
787
                 &spr_read_ibat_h, &spr_write_ibatl_h,
788
                 0x00000000);
789
    spr_register(env, SPR_IBAT6U, "IBAT6U",
790
                 SPR_NOACCESS, SPR_NOACCESS,
791
                 &spr_read_ibat_h, &spr_write_ibatu_h,
792
                 0x00000000);
793
    spr_register(env, SPR_IBAT6L, "IBAT6L",
794
                 SPR_NOACCESS, SPR_NOACCESS,
795
                 &spr_read_ibat_h, &spr_write_ibatl_h,
796
                 0x00000000);
797
    spr_register(env, SPR_IBAT7U, "IBAT7U",
798
                 SPR_NOACCESS, SPR_NOACCESS,
799
                 &spr_read_ibat_h, &spr_write_ibatu_h,
800
                 0x00000000);
801
    spr_register(env, SPR_IBAT7L, "IBAT7L",
802
                 SPR_NOACCESS, SPR_NOACCESS,
803
                 &spr_read_ibat_h, &spr_write_ibatl_h,
804
                 0x00000000);
805
    spr_register(env, SPR_DBAT4U, "DBAT4U",
806
                 SPR_NOACCESS, SPR_NOACCESS,
807
                 &spr_read_dbat_h, &spr_write_dbatu_h,
808
                 0x00000000);
809
    spr_register(env, SPR_DBAT4L, "DBAT4L",
810
                 SPR_NOACCESS, SPR_NOACCESS,
811
                 &spr_read_dbat_h, &spr_write_dbatl_h,
812
                 0x00000000);
813
    spr_register(env, SPR_DBAT5U, "DBAT5U",
814
                 SPR_NOACCESS, SPR_NOACCESS,
815
                 &spr_read_dbat_h, &spr_write_dbatu_h,
816
                 0x00000000);
817
    spr_register(env, SPR_DBAT5L, "DBAT5L",
818
                 SPR_NOACCESS, SPR_NOACCESS,
819
                 &spr_read_dbat_h, &spr_write_dbatl_h,
820
                 0x00000000);
821
    spr_register(env, SPR_DBAT6U, "DBAT6U",
822
                 SPR_NOACCESS, SPR_NOACCESS,
823
                 &spr_read_dbat_h, &spr_write_dbatu_h,
824
                 0x00000000);
825
    spr_register(env, SPR_DBAT6L, "DBAT6L",
826
                 SPR_NOACCESS, SPR_NOACCESS,
827
                 &spr_read_dbat_h, &spr_write_dbatl_h,
828
                 0x00000000);
829
    spr_register(env, SPR_DBAT7U, "DBAT7U",
830
                 SPR_NOACCESS, SPR_NOACCESS,
831
                 &spr_read_dbat_h, &spr_write_dbatu_h,
832
                 0x00000000);
833
    spr_register(env, SPR_DBAT7L, "DBAT7L",
834
                 SPR_NOACCESS, SPR_NOACCESS,
835
                 &spr_read_dbat_h, &spr_write_dbatl_h,
836
                 0x00000000);
837
    env->nb_BATs += 4;
838
#endif
839
}
840

    
841
/* Generic PowerPC time base */
842
static void gen_tbl (CPUPPCState *env)
843
{
844
    spr_register(env, SPR_VTBL,  "TBL",
845
                 &spr_read_tbl, SPR_NOACCESS,
846
                 &spr_read_tbl, SPR_NOACCESS,
847
                 0x00000000);
848
    spr_register(env, SPR_TBL,   "TBL",
849
                 &spr_read_tbl, SPR_NOACCESS,
850
                 &spr_read_tbl, &spr_write_tbl,
851
                 0x00000000);
852
    spr_register(env, SPR_VTBU,  "TBU",
853
                 &spr_read_tbu, SPR_NOACCESS,
854
                 &spr_read_tbu, SPR_NOACCESS,
855
                 0x00000000);
856
    spr_register(env, SPR_TBU,   "TBU",
857
                 &spr_read_tbu, SPR_NOACCESS,
858
                 &spr_read_tbu, &spr_write_tbu,
859
                 0x00000000);
860
}
861

    
862
/* Softare table search registers */
863
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864
{
865
#if !defined(CONFIG_USER_ONLY)
866
    env->nb_tlb = nb_tlbs;
867
    env->nb_ways = nb_ways;
868
    env->id_tlbs = 1;
869
    env->tlb_type = TLB_6XX;
870
    spr_register(env, SPR_DMISS, "DMISS",
871
                 SPR_NOACCESS, SPR_NOACCESS,
872
                 &spr_read_generic, SPR_NOACCESS,
873
                 0x00000000);
874
    spr_register(env, SPR_DCMP, "DCMP",
875
                 SPR_NOACCESS, SPR_NOACCESS,
876
                 &spr_read_generic, SPR_NOACCESS,
877
                 0x00000000);
878
    spr_register(env, SPR_HASH1, "HASH1",
879
                 SPR_NOACCESS, SPR_NOACCESS,
880
                 &spr_read_generic, SPR_NOACCESS,
881
                 0x00000000);
882
    spr_register(env, SPR_HASH2, "HASH2",
883
                 SPR_NOACCESS, SPR_NOACCESS,
884
                 &spr_read_generic, SPR_NOACCESS,
885
                 0x00000000);
886
    spr_register(env, SPR_IMISS, "IMISS",
887
                 SPR_NOACCESS, SPR_NOACCESS,
888
                 &spr_read_generic, SPR_NOACCESS,
889
                 0x00000000);
890
    spr_register(env, SPR_ICMP, "ICMP",
891
                 SPR_NOACCESS, SPR_NOACCESS,
892
                 &spr_read_generic, SPR_NOACCESS,
893
                 0x00000000);
894
    spr_register(env, SPR_RPA, "RPA",
895
                 SPR_NOACCESS, SPR_NOACCESS,
896
                 &spr_read_generic, &spr_write_generic,
897
                 0x00000000);
898
#endif
899
}
900

    
901
/* SPR common to MPC755 and G2 */
902
static void gen_spr_G2_755 (CPUPPCState *env)
903
{
904
    /* SGPRs */
905
    spr_register(env, SPR_SPRG4, "SPRG4",
906
                 SPR_NOACCESS, SPR_NOACCESS,
907
                 &spr_read_generic, &spr_write_generic,
908
                 0x00000000);
909
    spr_register(env, SPR_SPRG5, "SPRG5",
910
                 SPR_NOACCESS, SPR_NOACCESS,
911
                 &spr_read_generic, &spr_write_generic,
912
                 0x00000000);
913
    spr_register(env, SPR_SPRG6, "SPRG6",
914
                 SPR_NOACCESS, SPR_NOACCESS,
915
                 &spr_read_generic, &spr_write_generic,
916
                 0x00000000);
917
    spr_register(env, SPR_SPRG7, "SPRG7",
918
                 SPR_NOACCESS, SPR_NOACCESS,
919
                 &spr_read_generic, &spr_write_generic,
920
                 0x00000000);
921
}
922

    
923
/* SPR common to all 7xx PowerPC implementations */
924
static void gen_spr_7xx (CPUPPCState *env)
925
{
926
    /* Breakpoints */
927
    /* XXX : not implemented */
928
    spr_register_kvm(env, SPR_DABR, "DABR",
929
                     SPR_NOACCESS, SPR_NOACCESS,
930
                     &spr_read_generic, &spr_write_generic,
931
                     KVM_REG_PPC_DABR, 0x00000000);
932
    /* XXX : not implemented */
933
    spr_register(env, SPR_IABR, "IABR",
934
                 SPR_NOACCESS, SPR_NOACCESS,
935
                 &spr_read_generic, &spr_write_generic,
936
                 0x00000000);
937
    /* Cache management */
938
    /* XXX : not implemented */
939
    spr_register(env, SPR_ICTC, "ICTC",
940
                 SPR_NOACCESS, SPR_NOACCESS,
941
                 &spr_read_generic, &spr_write_generic,
942
                 0x00000000);
943
    /* Performance monitors */
944
    /* XXX : not implemented */
945
    spr_register(env, SPR_MMCR0, "MMCR0",
946
                 SPR_NOACCESS, SPR_NOACCESS,
947
                 &spr_read_generic, &spr_write_generic,
948
                 0x00000000);
949
    /* XXX : not implemented */
950
    spr_register(env, SPR_MMCR1, "MMCR1",
951
                 SPR_NOACCESS, SPR_NOACCESS,
952
                 &spr_read_generic, &spr_write_generic,
953
                 0x00000000);
954
    /* XXX : not implemented */
955
    spr_register(env, SPR_PMC1, "PMC1",
956
                 SPR_NOACCESS, SPR_NOACCESS,
957
                 &spr_read_generic, &spr_write_generic,
958
                 0x00000000);
959
    /* XXX : not implemented */
960
    spr_register(env, SPR_PMC2, "PMC2",
961
                 SPR_NOACCESS, SPR_NOACCESS,
962
                 &spr_read_generic, &spr_write_generic,
963
                 0x00000000);
964
    /* XXX : not implemented */
965
    spr_register(env, SPR_PMC3, "PMC3",
966
                 SPR_NOACCESS, SPR_NOACCESS,
967
                 &spr_read_generic, &spr_write_generic,
968
                 0x00000000);
969
    /* XXX : not implemented */
970
    spr_register(env, SPR_PMC4, "PMC4",
971
                 SPR_NOACCESS, SPR_NOACCESS,
972
                 &spr_read_generic, &spr_write_generic,
973
                 0x00000000);
974
    /* XXX : not implemented */
975
    spr_register(env, SPR_SIAR, "SIAR",
976
                 SPR_NOACCESS, SPR_NOACCESS,
977
                 &spr_read_generic, SPR_NOACCESS,
978
                 0x00000000);
979
    /* XXX : not implemented */
980
    spr_register(env, SPR_UMMCR0, "UMMCR0",
981
                 &spr_read_ureg, SPR_NOACCESS,
982
                 &spr_read_ureg, SPR_NOACCESS,
983
                 0x00000000);
984
    /* XXX : not implemented */
985
    spr_register(env, SPR_UMMCR1, "UMMCR1",
986
                 &spr_read_ureg, SPR_NOACCESS,
987
                 &spr_read_ureg, SPR_NOACCESS,
988
                 0x00000000);
989
    /* XXX : not implemented */
990
    spr_register(env, SPR_UPMC1, "UPMC1",
991
                 &spr_read_ureg, SPR_NOACCESS,
992
                 &spr_read_ureg, SPR_NOACCESS,
993
                 0x00000000);
994
    /* XXX : not implemented */
995
    spr_register(env, SPR_UPMC2, "UPMC2",
996
                 &spr_read_ureg, SPR_NOACCESS,
997
                 &spr_read_ureg, SPR_NOACCESS,
998
                 0x00000000);
999
    /* XXX : not implemented */
1000
    spr_register(env, SPR_UPMC3, "UPMC3",
1001
                 &spr_read_ureg, SPR_NOACCESS,
1002
                 &spr_read_ureg, SPR_NOACCESS,
1003
                 0x00000000);
1004
    /* XXX : not implemented */
1005
    spr_register(env, SPR_UPMC4, "UPMC4",
1006
                 &spr_read_ureg, SPR_NOACCESS,
1007
                 &spr_read_ureg, SPR_NOACCESS,
1008
                 0x00000000);
1009
    /* XXX : not implemented */
1010
    spr_register(env, SPR_USIAR, "USIAR",
1011
                 &spr_read_ureg, SPR_NOACCESS,
1012
                 &spr_read_ureg, SPR_NOACCESS,
1013
                 0x00000000);
1014
    /* External access control */
1015
    /* XXX : not implemented */
1016
    spr_register(env, SPR_EAR, "EAR",
1017
                 SPR_NOACCESS, SPR_NOACCESS,
1018
                 &spr_read_generic, &spr_write_generic,
1019
                 0x00000000);
1020
}
1021

    
1022
#ifdef TARGET_PPC64
1023
#ifndef CONFIG_USER_ONLY
1024
static void spr_read_uamr (void *opaque, int gprn, int sprn)
1025
{
1026
    gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1027
    spr_load_dump_spr(SPR_AMR);
1028
}
1029

    
1030
static void spr_write_uamr (void *opaque, int sprn, int gprn)
1031
{
1032
    gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1033
    spr_store_dump_spr(SPR_AMR);
1034
}
1035

    
1036
static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1037
{
1038
    TCGv t0 = tcg_temp_new();
1039

    
1040
    gen_load_spr(t0, SPR_UAMOR);
1041
    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1042
    gen_store_spr(SPR_AMR, t0);
1043
    spr_store_dump_spr(SPR_AMR);
1044
}
1045
#endif /* CONFIG_USER_ONLY */
1046

    
1047
static void gen_spr_amr (CPUPPCState *env)
1048
{
1049
#ifndef CONFIG_USER_ONLY
1050
    /* Virtual Page Class Key protection */
1051
    /* The AMR is accessible either via SPR 13 or SPR 29.  13 is
1052
     * userspace accessible, 29 is privileged.  So we only need to set
1053
     * the kvm ONE_REG id on one of them, we use 29 */
1054
    spr_register(env, SPR_UAMR, "UAMR",
1055
                 &spr_read_uamr, &spr_write_uamr_pr,
1056
                 &spr_read_uamr, &spr_write_uamr,
1057
                 0);
1058
    spr_register_kvm(env, SPR_AMR, "AMR",
1059
                     SPR_NOACCESS, SPR_NOACCESS,
1060
                     &spr_read_generic, &spr_write_generic,
1061
                     KVM_REG_PPC_AMR, 0xffffffffffffffffULL);
1062
    spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1063
                     SPR_NOACCESS, SPR_NOACCESS,
1064
                     &spr_read_generic, &spr_write_generic,
1065
                     KVM_REG_PPC_UAMOR, 0);
1066
#endif /* !CONFIG_USER_ONLY */
1067
}
1068
#endif /* TARGET_PPC64 */
1069

    
1070
static void gen_spr_thrm (CPUPPCState *env)
1071
{
1072
    /* Thermal management */
1073
    /* XXX : not implemented */
1074
    spr_register(env, SPR_THRM1, "THRM1",
1075
                 SPR_NOACCESS, SPR_NOACCESS,
1076
                 &spr_read_generic, &spr_write_generic,
1077
                 0x00000000);
1078
    /* XXX : not implemented */
1079
    spr_register(env, SPR_THRM2, "THRM2",
1080
                 SPR_NOACCESS, SPR_NOACCESS,
1081
                 &spr_read_generic, &spr_write_generic,
1082
                 0x00000000);
1083
    /* XXX : not implemented */
1084
    spr_register(env, SPR_THRM3, "THRM3",
1085
                 SPR_NOACCESS, SPR_NOACCESS,
1086
                 &spr_read_generic, &spr_write_generic,
1087
                 0x00000000);
1088
}
1089

    
1090
/* SPR specific to PowerPC 604 implementation */
1091
static void gen_spr_604 (CPUPPCState *env)
1092
{
1093
    /* Processor identification */
1094
    spr_register(env, SPR_PIR, "PIR",
1095
                 SPR_NOACCESS, SPR_NOACCESS,
1096
                 &spr_read_generic, &spr_write_pir,
1097
                 0x00000000);
1098
    /* Breakpoints */
1099
    /* XXX : not implemented */
1100
    spr_register(env, SPR_IABR, "IABR",
1101
                 SPR_NOACCESS, SPR_NOACCESS,
1102
                 &spr_read_generic, &spr_write_generic,
1103
                 0x00000000);
1104
    /* XXX : not implemented */
1105
    spr_register_kvm(env, SPR_DABR, "DABR",
1106
                     SPR_NOACCESS, SPR_NOACCESS,
1107
                     &spr_read_generic, &spr_write_generic,
1108
                     KVM_REG_PPC_DABR, 0x00000000);
1109
    /* Performance counters */
1110
    /* XXX : not implemented */
1111
    spr_register(env, SPR_MMCR0, "MMCR0",
1112
                 SPR_NOACCESS, SPR_NOACCESS,
1113
                 &spr_read_generic, &spr_write_generic,
1114
                 0x00000000);
1115
    /* XXX : not implemented */
1116
    spr_register(env, SPR_PMC1, "PMC1",
1117
                 SPR_NOACCESS, SPR_NOACCESS,
1118
                 &spr_read_generic, &spr_write_generic,
1119
                 0x00000000);
1120
    /* XXX : not implemented */
1121
    spr_register(env, SPR_PMC2, "PMC2",
1122
                 SPR_NOACCESS, SPR_NOACCESS,
1123
                 &spr_read_generic, &spr_write_generic,
1124
                 0x00000000);
1125
    /* XXX : not implemented */
1126
    spr_register(env, SPR_SIAR, "SIAR",
1127
                 SPR_NOACCESS, SPR_NOACCESS,
1128
                 &spr_read_generic, SPR_NOACCESS,
1129
                 0x00000000);
1130
    /* XXX : not implemented */
1131
    spr_register(env, SPR_SDA, "SDA",
1132
                 SPR_NOACCESS, SPR_NOACCESS,
1133
                 &spr_read_generic, SPR_NOACCESS,
1134
                 0x00000000);
1135
    /* External access control */
1136
    /* XXX : not implemented */
1137
    spr_register(env, SPR_EAR, "EAR",
1138
                 SPR_NOACCESS, SPR_NOACCESS,
1139
                 &spr_read_generic, &spr_write_generic,
1140
                 0x00000000);
1141
}
1142

    
1143
/* SPR specific to PowerPC 603 implementation */
1144
static void gen_spr_603 (CPUPPCState *env)
1145
{
1146
    /* External access control */
1147
    /* XXX : not implemented */
1148
    spr_register(env, SPR_EAR, "EAR",
1149
                 SPR_NOACCESS, SPR_NOACCESS,
1150
                 &spr_read_generic, &spr_write_generic,
1151
                 0x00000000);
1152
    /* Breakpoints */
1153
    /* XXX : not implemented */
1154
    spr_register(env, SPR_IABR, "IABR",
1155
                 SPR_NOACCESS, SPR_NOACCESS,
1156
                 &spr_read_generic, &spr_write_generic,
1157
                 0x00000000);
1158

    
1159
}
1160

    
1161
/* SPR specific to PowerPC G2 implementation */
1162
static void gen_spr_G2 (CPUPPCState *env)
1163
{
1164
    /* Memory base address */
1165
    /* MBAR */
1166
    /* XXX : not implemented */
1167
    spr_register(env, SPR_MBAR, "MBAR",
1168
                 SPR_NOACCESS, SPR_NOACCESS,
1169
                 &spr_read_generic, &spr_write_generic,
1170
                 0x00000000);
1171
    /* Exception processing */
1172
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1173
                 SPR_NOACCESS, SPR_NOACCESS,
1174
                 &spr_read_generic, &spr_write_generic,
1175
                 0x00000000);
1176
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1177
                 SPR_NOACCESS, SPR_NOACCESS,
1178
                 &spr_read_generic, &spr_write_generic,
1179
                 0x00000000);
1180
    /* Breakpoints */
1181
    /* XXX : not implemented */
1182
    spr_register(env, SPR_DABR, "DABR",
1183
                 SPR_NOACCESS, SPR_NOACCESS,
1184
                 &spr_read_generic, &spr_write_generic,
1185
                 0x00000000);
1186
    /* XXX : not implemented */
1187
    spr_register(env, SPR_DABR2, "DABR2",
1188
                 SPR_NOACCESS, SPR_NOACCESS,
1189
                 &spr_read_generic, &spr_write_generic,
1190
                 0x00000000);
1191
    /* XXX : not implemented */
1192
    spr_register(env, SPR_IABR, "IABR",
1193
                 SPR_NOACCESS, SPR_NOACCESS,
1194
                 &spr_read_generic, &spr_write_generic,
1195
                 0x00000000);
1196
    /* XXX : not implemented */
1197
    spr_register(env, SPR_IABR2, "IABR2",
1198
                 SPR_NOACCESS, SPR_NOACCESS,
1199
                 &spr_read_generic, &spr_write_generic,
1200
                 0x00000000);
1201
    /* XXX : not implemented */
1202
    spr_register(env, SPR_IBCR, "IBCR",
1203
                 SPR_NOACCESS, SPR_NOACCESS,
1204
                 &spr_read_generic, &spr_write_generic,
1205
                 0x00000000);
1206
    /* XXX : not implemented */
1207
    spr_register(env, SPR_DBCR, "DBCR",
1208
                 SPR_NOACCESS, SPR_NOACCESS,
1209
                 &spr_read_generic, &spr_write_generic,
1210
                 0x00000000);
1211
}
1212

    
1213
/* SPR specific to PowerPC 602 implementation */
1214
static void gen_spr_602 (CPUPPCState *env)
1215
{
1216
    /* ESA registers */
1217
    /* XXX : not implemented */
1218
    spr_register(env, SPR_SER, "SER",
1219
                 SPR_NOACCESS, SPR_NOACCESS,
1220
                 &spr_read_generic, &spr_write_generic,
1221
                 0x00000000);
1222
    /* XXX : not implemented */
1223
    spr_register(env, SPR_SEBR, "SEBR",
1224
                 SPR_NOACCESS, SPR_NOACCESS,
1225
                 &spr_read_generic, &spr_write_generic,
1226
                 0x00000000);
1227
    /* XXX : not implemented */
1228
    spr_register(env, SPR_ESASRR, "ESASRR",
1229
                 SPR_NOACCESS, SPR_NOACCESS,
1230
                 &spr_read_generic, &spr_write_generic,
1231
                 0x00000000);
1232
    /* Floating point status */
1233
    /* XXX : not implemented */
1234
    spr_register(env, SPR_SP, "SP",
1235
                 SPR_NOACCESS, SPR_NOACCESS,
1236
                 &spr_read_generic, &spr_write_generic,
1237
                 0x00000000);
1238
    /* XXX : not implemented */
1239
    spr_register(env, SPR_LT, "LT",
1240
                 SPR_NOACCESS, SPR_NOACCESS,
1241
                 &spr_read_generic, &spr_write_generic,
1242
                 0x00000000);
1243
    /* Watchdog timer */
1244
    /* XXX : not implemented */
1245
    spr_register(env, SPR_TCR, "TCR",
1246
                 SPR_NOACCESS, SPR_NOACCESS,
1247
                 &spr_read_generic, &spr_write_generic,
1248
                 0x00000000);
1249
    /* Interrupt base */
1250
    spr_register(env, SPR_IBR, "IBR",
1251
                 SPR_NOACCESS, SPR_NOACCESS,
1252
                 &spr_read_generic, &spr_write_generic,
1253
                 0x00000000);
1254
    /* XXX : not implemented */
1255
    spr_register(env, SPR_IABR, "IABR",
1256
                 SPR_NOACCESS, SPR_NOACCESS,
1257
                 &spr_read_generic, &spr_write_generic,
1258
                 0x00000000);
1259
}
1260

    
1261
/* SPR specific to PowerPC 601 implementation */
1262
static void gen_spr_601 (CPUPPCState *env)
1263
{
1264
    /* Multiplication/division register */
1265
    /* MQ */
1266
    spr_register(env, SPR_MQ, "MQ",
1267
                 &spr_read_generic, &spr_write_generic,
1268
                 &spr_read_generic, &spr_write_generic,
1269
                 0x00000000);
1270
    /* RTC registers */
1271
    spr_register(env, SPR_601_RTCU, "RTCU",
1272
                 SPR_NOACCESS, SPR_NOACCESS,
1273
                 SPR_NOACCESS, &spr_write_601_rtcu,
1274
                 0x00000000);
1275
    spr_register(env, SPR_601_VRTCU, "RTCU",
1276
                 &spr_read_601_rtcu, SPR_NOACCESS,
1277
                 &spr_read_601_rtcu, SPR_NOACCESS,
1278
                 0x00000000);
1279
    spr_register(env, SPR_601_RTCL, "RTCL",
1280
                 SPR_NOACCESS, SPR_NOACCESS,
1281
                 SPR_NOACCESS, &spr_write_601_rtcl,
1282
                 0x00000000);
1283
    spr_register(env, SPR_601_VRTCL, "RTCL",
1284
                 &spr_read_601_rtcl, SPR_NOACCESS,
1285
                 &spr_read_601_rtcl, SPR_NOACCESS,
1286
                 0x00000000);
1287
    /* Timer */
1288
#if 0 /* ? */
1289
    spr_register(env, SPR_601_UDECR, "UDECR",
1290
                 &spr_read_decr, SPR_NOACCESS,
1291
                 &spr_read_decr, SPR_NOACCESS,
1292
                 0x00000000);
1293
#endif
1294
    /* External access control */
1295
    /* XXX : not implemented */
1296
    spr_register(env, SPR_EAR, "EAR",
1297
                 SPR_NOACCESS, SPR_NOACCESS,
1298
                 &spr_read_generic, &spr_write_generic,
1299
                 0x00000000);
1300
    /* Memory management */
1301
#if !defined(CONFIG_USER_ONLY)
1302
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1303
                 SPR_NOACCESS, SPR_NOACCESS,
1304
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1305
                 0x00000000);
1306
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1307
                 SPR_NOACCESS, SPR_NOACCESS,
1308
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1309
                 0x00000000);
1310
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1311
                 SPR_NOACCESS, SPR_NOACCESS,
1312
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1313
                 0x00000000);
1314
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1315
                 SPR_NOACCESS, SPR_NOACCESS,
1316
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1317
                 0x00000000);
1318
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1319
                 SPR_NOACCESS, SPR_NOACCESS,
1320
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1321
                 0x00000000);
1322
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1323
                 SPR_NOACCESS, SPR_NOACCESS,
1324
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1325
                 0x00000000);
1326
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1327
                 SPR_NOACCESS, SPR_NOACCESS,
1328
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1329
                 0x00000000);
1330
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1331
                 SPR_NOACCESS, SPR_NOACCESS,
1332
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1333
                 0x00000000);
1334
    env->nb_BATs = 4;
1335
#endif
1336
}
1337

    
1338
static void gen_spr_74xx (CPUPPCState *env)
1339
{
1340
    /* Processor identification */
1341
    spr_register(env, SPR_PIR, "PIR",
1342
                 SPR_NOACCESS, SPR_NOACCESS,
1343
                 &spr_read_generic, &spr_write_pir,
1344
                 0x00000000);
1345
    /* XXX : not implemented */
1346
    spr_register(env, SPR_MMCR2, "MMCR2",
1347
                 SPR_NOACCESS, SPR_NOACCESS,
1348
                 &spr_read_generic, &spr_write_generic,
1349
                 0x00000000);
1350
    /* XXX : not implemented */
1351
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1352
                 &spr_read_ureg, SPR_NOACCESS,
1353
                 &spr_read_ureg, SPR_NOACCESS,
1354
                 0x00000000);
1355
    /* XXX: not implemented */
1356
    spr_register(env, SPR_BAMR, "BAMR",
1357
                 SPR_NOACCESS, SPR_NOACCESS,
1358
                 &spr_read_generic, &spr_write_generic,
1359
                 0x00000000);
1360
    /* XXX : not implemented */
1361
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1362
                 SPR_NOACCESS, SPR_NOACCESS,
1363
                 &spr_read_generic, &spr_write_generic,
1364
                 0x00000000);
1365
    /* Hardware implementation registers */
1366
    /* XXX : not implemented */
1367
    spr_register(env, SPR_HID0, "HID0",
1368
                 SPR_NOACCESS, SPR_NOACCESS,
1369
                 &spr_read_generic, &spr_write_generic,
1370
                 0x00000000);
1371
    /* XXX : not implemented */
1372
    spr_register(env, SPR_HID1, "HID1",
1373
                 SPR_NOACCESS, SPR_NOACCESS,
1374
                 &spr_read_generic, &spr_write_generic,
1375
                 0x00000000);
1376
    /* Altivec */
1377
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1378
                 &spr_read_generic, &spr_write_generic,
1379
                 &spr_read_generic, &spr_write_generic,
1380
                 0x00000000);
1381
    /* XXX : not implemented */
1382
    spr_register(env, SPR_L2CR, "L2CR",
1383
                 SPR_NOACCESS, SPR_NOACCESS,
1384
                 &spr_read_generic, NULL,
1385
                 0x00000000);
1386
    /* Not strictly an SPR */
1387
    vscr_init(env, 0x00010000);
1388
}
1389

    
1390
static void gen_l3_ctrl (CPUPPCState *env)
1391
{
1392
    /* L3CR */
1393
    /* XXX : not implemented */
1394
    spr_register(env, SPR_L3CR, "L3CR",
1395
                 SPR_NOACCESS, SPR_NOACCESS,
1396
                 &spr_read_generic, &spr_write_generic,
1397
                 0x00000000);
1398
    /* L3ITCR0 */
1399
    /* XXX : not implemented */
1400
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1401
                 SPR_NOACCESS, SPR_NOACCESS,
1402
                 &spr_read_generic, &spr_write_generic,
1403
                 0x00000000);
1404
    /* L3PM */
1405
    /* XXX : not implemented */
1406
    spr_register(env, SPR_L3PM, "L3PM",
1407
                 SPR_NOACCESS, SPR_NOACCESS,
1408
                 &spr_read_generic, &spr_write_generic,
1409
                 0x00000000);
1410
}
1411

    
1412
static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1413
{
1414
#if !defined(CONFIG_USER_ONLY)
1415
    env->nb_tlb = nb_tlbs;
1416
    env->nb_ways = nb_ways;
1417
    env->id_tlbs = 1;
1418
    env->tlb_type = TLB_6XX;
1419
    /* XXX : not implemented */
1420
    spr_register(env, SPR_PTEHI, "PTEHI",
1421
                 SPR_NOACCESS, SPR_NOACCESS,
1422
                 &spr_read_generic, &spr_write_generic,
1423
                 0x00000000);
1424
    /* XXX : not implemented */
1425
    spr_register(env, SPR_PTELO, "PTELO",
1426
                 SPR_NOACCESS, SPR_NOACCESS,
1427
                 &spr_read_generic, &spr_write_generic,
1428
                 0x00000000);
1429
    /* XXX : not implemented */
1430
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1431
                 SPR_NOACCESS, SPR_NOACCESS,
1432
                 &spr_read_generic, &spr_write_generic,
1433
                 0x00000000);
1434
#endif
1435
}
1436

    
1437
#if !defined(CONFIG_USER_ONLY)
1438
static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1439
{
1440
    TCGv t0 = tcg_temp_new();
1441

    
1442
    tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1443
    gen_store_spr(sprn, t0);
1444
    tcg_temp_free(t0);
1445
}
1446

    
1447
static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1448
{
1449
    TCGv_i32 t0 = tcg_const_i32(sprn);
1450
    gen_helper_booke206_tlbflush(cpu_env, t0);
1451
    tcg_temp_free_i32(t0);
1452
}
1453

    
1454
static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1455
{
1456
    TCGv_i32 t0 = tcg_const_i32(sprn);
1457
    gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1458
    tcg_temp_free_i32(t0);
1459
}
1460
#endif
1461

    
1462
static void gen_spr_usprgh (CPUPPCState *env)
1463
{
1464
    spr_register(env, SPR_USPRG4, "USPRG4",
1465
                 &spr_read_ureg, SPR_NOACCESS,
1466
                 &spr_read_ureg, SPR_NOACCESS,
1467
                 0x00000000);
1468
    spr_register(env, SPR_USPRG5, "USPRG5",
1469
                 &spr_read_ureg, SPR_NOACCESS,
1470
                 &spr_read_ureg, SPR_NOACCESS,
1471
                 0x00000000);
1472
    spr_register(env, SPR_USPRG6, "USPRG6",
1473
                 &spr_read_ureg, SPR_NOACCESS,
1474
                 &spr_read_ureg, SPR_NOACCESS,
1475
                 0x00000000);
1476
    spr_register(env, SPR_USPRG7, "USPRG7",
1477
                 &spr_read_ureg, SPR_NOACCESS,
1478
                 &spr_read_ureg, SPR_NOACCESS,
1479
                 0x00000000);
1480
}
1481

    
1482
/* PowerPC BookE SPR */
1483
static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1484
{
1485
    const char *ivor_names[64] = {
1486
        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1487
        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1488
        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1489
        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1490
        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1491
        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1492
        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1493
        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1494
        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1495
        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1496
        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1497
        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1498
        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1499
        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1500
        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1501
        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1502
    };
1503
#define SPR_BOOKE_IVORxx (-1)
1504
    int ivor_sprn[64] = {
1505
        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1506
        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1507
        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1508
        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1509
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1510
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1511
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1512
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1513
        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1514
        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1515
        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1516
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1517
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1518
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1519
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1520
        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1521
    };
1522
    int i;
1523

    
1524
    /* Interrupt processing */
1525
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1526
                 SPR_NOACCESS, SPR_NOACCESS,
1527
                 &spr_read_generic, &spr_write_generic,
1528
                 0x00000000);
1529
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1530
                 SPR_NOACCESS, SPR_NOACCESS,
1531
                 &spr_read_generic, &spr_write_generic,
1532
                 0x00000000);
1533
    /* Debug */
1534
    /* XXX : not implemented */
1535
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1536
                 SPR_NOACCESS, SPR_NOACCESS,
1537
                 &spr_read_generic, &spr_write_generic,
1538
                 0x00000000);
1539
    /* XXX : not implemented */
1540
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1541
                 SPR_NOACCESS, SPR_NOACCESS,
1542
                 &spr_read_generic, &spr_write_generic,
1543
                 0x00000000);
1544
    /* XXX : not implemented */
1545
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1546
                 SPR_NOACCESS, SPR_NOACCESS,
1547
                 &spr_read_generic, &spr_write_generic,
1548
                 0x00000000);
1549
    /* XXX : not implemented */
1550
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1551
                 SPR_NOACCESS, SPR_NOACCESS,
1552
                 &spr_read_generic, &spr_write_generic,
1553
                 0x00000000);
1554
    /* XXX : not implemented */
1555
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1556
                 SPR_NOACCESS, SPR_NOACCESS,
1557
                 &spr_read_generic, &spr_write_40x_dbcr0,
1558
                 0x00000000);
1559
    /* XXX : not implemented */
1560
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1561
                 SPR_NOACCESS, SPR_NOACCESS,
1562
                 &spr_read_generic, &spr_write_generic,
1563
                 0x00000000);
1564
    /* XXX : not implemented */
1565
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1566
                 SPR_NOACCESS, SPR_NOACCESS,
1567
                 &spr_read_generic, &spr_write_generic,
1568
                 0x00000000);
1569
    /* XXX : not implemented */
1570
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1571
                 SPR_NOACCESS, SPR_NOACCESS,
1572
                 &spr_read_generic, &spr_write_clear,
1573
                 0x00000000);
1574
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1575
                 SPR_NOACCESS, SPR_NOACCESS,
1576
                 &spr_read_generic, &spr_write_generic,
1577
                 0x00000000);
1578
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1579
                 SPR_NOACCESS, SPR_NOACCESS,
1580
                 &spr_read_generic, &spr_write_generic,
1581
                 0x00000000);
1582
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1583
                 SPR_NOACCESS, SPR_NOACCESS,
1584
                 &spr_read_generic, &spr_write_excp_prefix,
1585
                 0x00000000);
1586
    /* Exception vectors */
1587
    for (i = 0; i < 64; i++) {
1588
        if (ivor_mask & (1ULL << i)) {
1589
            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1590
                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1591
                exit(1);
1592
            }
1593
            spr_register(env, ivor_sprn[i], ivor_names[i],
1594
                         SPR_NOACCESS, SPR_NOACCESS,
1595
                         &spr_read_generic, &spr_write_excp_vector,
1596
                         0x00000000);
1597
        }
1598
    }
1599
    spr_register(env, SPR_BOOKE_PID, "PID",
1600
                 SPR_NOACCESS, SPR_NOACCESS,
1601
                 &spr_read_generic, &spr_write_booke_pid,
1602
                 0x00000000);
1603
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1604
                 SPR_NOACCESS, SPR_NOACCESS,
1605
                 &spr_read_generic, &spr_write_booke_tcr,
1606
                 0x00000000);
1607
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1608
                 SPR_NOACCESS, SPR_NOACCESS,
1609
                 &spr_read_generic, &spr_write_booke_tsr,
1610
                 0x00000000);
1611
    /* Timer */
1612
    spr_register(env, SPR_DECR, "DECR",
1613
                 SPR_NOACCESS, SPR_NOACCESS,
1614
                 &spr_read_decr, &spr_write_decr,
1615
                 0x00000000);
1616
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1617
                 SPR_NOACCESS, SPR_NOACCESS,
1618
                 SPR_NOACCESS, &spr_write_generic,
1619
                 0x00000000);
1620
    /* SPRGs */
1621
    spr_register(env, SPR_USPRG0, "USPRG0",
1622
                 &spr_read_generic, &spr_write_generic,
1623
                 &spr_read_generic, &spr_write_generic,
1624
                 0x00000000);
1625
    spr_register(env, SPR_SPRG4, "SPRG4",
1626
                 SPR_NOACCESS, SPR_NOACCESS,
1627
                 &spr_read_generic, &spr_write_generic,
1628
                 0x00000000);
1629
    spr_register(env, SPR_SPRG5, "SPRG5",
1630
                 SPR_NOACCESS, SPR_NOACCESS,
1631
                 &spr_read_generic, &spr_write_generic,
1632
                 0x00000000);
1633
    spr_register(env, SPR_SPRG6, "SPRG6",
1634
                 SPR_NOACCESS, SPR_NOACCESS,
1635
                 &spr_read_generic, &spr_write_generic,
1636
                 0x00000000);
1637
    spr_register(env, SPR_SPRG7, "SPRG7",
1638
                 SPR_NOACCESS, SPR_NOACCESS,
1639
                 &spr_read_generic, &spr_write_generic,
1640
                 0x00000000);
1641
}
1642

    
1643
static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1644
                                   uint32_t maxsize, uint32_t flags,
1645
                                   uint32_t nentries)
1646
{
1647
    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1648
           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1649
           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1650
           flags | nentries;
1651
}
1652

    
1653
/* BookE 2.06 storage control registers */
1654
static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1655
                              uint32_t *tlbncfg)
1656
{
1657
#if !defined(CONFIG_USER_ONLY)
1658
    const char *mas_names[8] = {
1659
        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1660
    };
1661
    int mas_sprn[8] = {
1662
        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1663
        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1664
    };
1665
    int i;
1666

    
1667
    /* TLB assist registers */
1668
    /* XXX : not implemented */
1669
    for (i = 0; i < 8; i++) {
1670
        void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1671
        if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1672
            uea_write = &spr_write_generic;
1673
        }
1674
        if (mas_mask & (1 << i)) {
1675
            spr_register(env, mas_sprn[i], mas_names[i],
1676
                         SPR_NOACCESS, SPR_NOACCESS,
1677
                         &spr_read_generic, uea_write,
1678
                         0x00000000);
1679
        }
1680
    }
1681
    if (env->nb_pids > 1) {
1682
        /* XXX : not implemented */
1683
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1684
                     SPR_NOACCESS, SPR_NOACCESS,
1685
                     &spr_read_generic, &spr_write_booke_pid,
1686
                     0x00000000);
1687
    }
1688
    if (env->nb_pids > 2) {
1689
        /* XXX : not implemented */
1690
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1691
                     SPR_NOACCESS, SPR_NOACCESS,
1692
                     &spr_read_generic, &spr_write_booke_pid,
1693
                     0x00000000);
1694
    }
1695
    /* XXX : not implemented */
1696
    spr_register(env, SPR_MMUCFG, "MMUCFG",
1697
                 SPR_NOACCESS, SPR_NOACCESS,
1698
                 &spr_read_generic, SPR_NOACCESS,
1699
                 0x00000000); /* TOFIX */
1700
    switch (env->nb_ways) {
1701
    case 4:
1702
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1703
                     SPR_NOACCESS, SPR_NOACCESS,
1704
                     &spr_read_generic, SPR_NOACCESS,
1705
                     tlbncfg[3]);
1706
        /* Fallthru */
1707
    case 3:
1708
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1709
                     SPR_NOACCESS, SPR_NOACCESS,
1710
                     &spr_read_generic, SPR_NOACCESS,
1711
                     tlbncfg[2]);
1712
        /* Fallthru */
1713
    case 2:
1714
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1715
                     SPR_NOACCESS, SPR_NOACCESS,
1716
                     &spr_read_generic, SPR_NOACCESS,
1717
                     tlbncfg[1]);
1718
        /* Fallthru */
1719
    case 1:
1720
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1721
                     SPR_NOACCESS, SPR_NOACCESS,
1722
                     &spr_read_generic, SPR_NOACCESS,
1723
                     tlbncfg[0]);
1724
        /* Fallthru */
1725
    case 0:
1726
    default:
1727
        break;
1728
    }
1729
#endif
1730

    
1731
    gen_spr_usprgh(env);
1732
}
1733

    
1734
/* SPR specific to PowerPC 440 implementation */
1735
static void gen_spr_440 (CPUPPCState *env)
1736
{
1737
    /* Cache control */
1738
    /* XXX : not implemented */
1739
    spr_register(env, SPR_440_DNV0, "DNV0",
1740
                 SPR_NOACCESS, SPR_NOACCESS,
1741
                 &spr_read_generic, &spr_write_generic,
1742
                 0x00000000);
1743
    /* XXX : not implemented */
1744
    spr_register(env, SPR_440_DNV1, "DNV1",
1745
                 SPR_NOACCESS, SPR_NOACCESS,
1746
                 &spr_read_generic, &spr_write_generic,
1747
                 0x00000000);
1748
    /* XXX : not implemented */
1749
    spr_register(env, SPR_440_DNV2, "DNV2",
1750
                 SPR_NOACCESS, SPR_NOACCESS,
1751
                 &spr_read_generic, &spr_write_generic,
1752
                 0x00000000);
1753
    /* XXX : not implemented */
1754
    spr_register(env, SPR_440_DNV3, "DNV3",
1755
                 SPR_NOACCESS, SPR_NOACCESS,
1756
                 &spr_read_generic, &spr_write_generic,
1757
                 0x00000000);
1758
    /* XXX : not implemented */
1759
    spr_register(env, SPR_440_DTV0, "DTV0",
1760
                 SPR_NOACCESS, SPR_NOACCESS,
1761
                 &spr_read_generic, &spr_write_generic,
1762
                 0x00000000);
1763
    /* XXX : not implemented */
1764
    spr_register(env, SPR_440_DTV1, "DTV1",
1765
                 SPR_NOACCESS, SPR_NOACCESS,
1766
                 &spr_read_generic, &spr_write_generic,
1767
                 0x00000000);
1768
    /* XXX : not implemented */
1769
    spr_register(env, SPR_440_DTV2, "DTV2",
1770
                 SPR_NOACCESS, SPR_NOACCESS,
1771
                 &spr_read_generic, &spr_write_generic,
1772
                 0x00000000);
1773
    /* XXX : not implemented */
1774
    spr_register(env, SPR_440_DTV3, "DTV3",
1775
                 SPR_NOACCESS, SPR_NOACCESS,
1776
                 &spr_read_generic, &spr_write_generic,
1777
                 0x00000000);
1778
    /* XXX : not implemented */
1779
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1780
                 SPR_NOACCESS, SPR_NOACCESS,
1781
                 &spr_read_generic, &spr_write_generic,
1782
                 0x00000000);
1783
    /* XXX : not implemented */
1784
    spr_register(env, SPR_440_INV0, "INV0",
1785
                 SPR_NOACCESS, SPR_NOACCESS,
1786
                 &spr_read_generic, &spr_write_generic,
1787
                 0x00000000);
1788
    /* XXX : not implemented */
1789
    spr_register(env, SPR_440_INV1, "INV1",
1790
                 SPR_NOACCESS, SPR_NOACCESS,
1791
                 &spr_read_generic, &spr_write_generic,
1792
                 0x00000000);
1793
    /* XXX : not implemented */
1794
    spr_register(env, SPR_440_INV2, "INV2",
1795
                 SPR_NOACCESS, SPR_NOACCESS,
1796
                 &spr_read_generic, &spr_write_generic,
1797
                 0x00000000);
1798
    /* XXX : not implemented */
1799
    spr_register(env, SPR_440_INV3, "INV3",
1800
                 SPR_NOACCESS, SPR_NOACCESS,
1801
                 &spr_read_generic, &spr_write_generic,
1802
                 0x00000000);
1803
    /* XXX : not implemented */
1804
    spr_register(env, SPR_440_ITV0, "ITV0",
1805
                 SPR_NOACCESS, SPR_NOACCESS,
1806
                 &spr_read_generic, &spr_write_generic,
1807
                 0x00000000);
1808
    /* XXX : not implemented */
1809
    spr_register(env, SPR_440_ITV1, "ITV1",
1810
                 SPR_NOACCESS, SPR_NOACCESS,
1811
                 &spr_read_generic, &spr_write_generic,
1812
                 0x00000000);
1813
    /* XXX : not implemented */
1814
    spr_register(env, SPR_440_ITV2, "ITV2",
1815
                 SPR_NOACCESS, SPR_NOACCESS,
1816
                 &spr_read_generic, &spr_write_generic,
1817
                 0x00000000);
1818
    /* XXX : not implemented */
1819
    spr_register(env, SPR_440_ITV3, "ITV3",
1820
                 SPR_NOACCESS, SPR_NOACCESS,
1821
                 &spr_read_generic, &spr_write_generic,
1822
                 0x00000000);
1823
    /* XXX : not implemented */
1824
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1825
                 SPR_NOACCESS, SPR_NOACCESS,
1826
                 &spr_read_generic, &spr_write_generic,
1827
                 0x00000000);
1828
    /* Cache debug */
1829
    /* XXX : not implemented */
1830
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1831
                 SPR_NOACCESS, SPR_NOACCESS,
1832
                 &spr_read_generic, SPR_NOACCESS,
1833
                 0x00000000);
1834
    /* XXX : not implemented */
1835
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1836
                 SPR_NOACCESS, SPR_NOACCESS,
1837
                 &spr_read_generic, SPR_NOACCESS,
1838
                 0x00000000);
1839
    /* XXX : not implemented */
1840
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1841
                 SPR_NOACCESS, SPR_NOACCESS,
1842
                 &spr_read_generic, SPR_NOACCESS,
1843
                 0x00000000);
1844
    /* XXX : not implemented */
1845
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1846
                 SPR_NOACCESS, SPR_NOACCESS,
1847
                 &spr_read_generic, SPR_NOACCESS,
1848
                 0x00000000);
1849
    /* XXX : not implemented */
1850
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1851
                 SPR_NOACCESS, SPR_NOACCESS,
1852
                 &spr_read_generic, SPR_NOACCESS,
1853
                 0x00000000);
1854
    /* XXX : not implemented */
1855
    spr_register(env, SPR_440_DBDR, "DBDR",
1856
                 SPR_NOACCESS, SPR_NOACCESS,
1857
                 &spr_read_generic, &spr_write_generic,
1858
                 0x00000000);
1859
    /* Processor control */
1860
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1861
                 SPR_NOACCESS, SPR_NOACCESS,
1862
                 &spr_read_generic, &spr_write_generic,
1863
                 0x00000000);
1864
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1865
                 SPR_NOACCESS, SPR_NOACCESS,
1866
                 &spr_read_generic, SPR_NOACCESS,
1867
                 0x00000000);
1868
    /* Storage control */
1869
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1870
                 SPR_NOACCESS, SPR_NOACCESS,
1871
                 &spr_read_generic, &spr_write_generic,
1872
                 0x00000000);
1873
}
1874

    
1875
/* SPR shared between PowerPC 40x implementations */
1876
static void gen_spr_40x (CPUPPCState *env)
1877
{
1878
    /* Cache */
1879
    /* not emulated, as QEMU do not emulate caches */
1880
    spr_register(env, SPR_40x_DCCR, "DCCR",
1881
                 SPR_NOACCESS, SPR_NOACCESS,
1882
                 &spr_read_generic, &spr_write_generic,
1883
                 0x00000000);
1884
    /* not emulated, as QEMU do not emulate caches */
1885
    spr_register(env, SPR_40x_ICCR, "ICCR",
1886
                 SPR_NOACCESS, SPR_NOACCESS,
1887
                 &spr_read_generic, &spr_write_generic,
1888
                 0x00000000);
1889
    /* not emulated, as QEMU do not emulate caches */
1890
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1891
                 SPR_NOACCESS, SPR_NOACCESS,
1892
                 &spr_read_generic, SPR_NOACCESS,
1893
                 0x00000000);
1894
    /* Exception */
1895
    spr_register(env, SPR_40x_DEAR, "DEAR",
1896
                 SPR_NOACCESS, SPR_NOACCESS,
1897
                 &spr_read_generic, &spr_write_generic,
1898
                 0x00000000);
1899
    spr_register(env, SPR_40x_ESR, "ESR",
1900
                 SPR_NOACCESS, SPR_NOACCESS,
1901
                 &spr_read_generic, &spr_write_generic,
1902
                 0x00000000);
1903
    spr_register(env, SPR_40x_EVPR, "EVPR",
1904
                 SPR_NOACCESS, SPR_NOACCESS,
1905
                 &spr_read_generic, &spr_write_excp_prefix,
1906
                 0x00000000);
1907
    spr_register(env, SPR_40x_SRR2, "SRR2",
1908
                 &spr_read_generic, &spr_write_generic,
1909
                 &spr_read_generic, &spr_write_generic,
1910
                 0x00000000);
1911
    spr_register(env, SPR_40x_SRR3, "SRR3",
1912
                 &spr_read_generic, &spr_write_generic,
1913
                 &spr_read_generic, &spr_write_generic,
1914
                 0x00000000);
1915
    /* Timers */
1916
    spr_register(env, SPR_40x_PIT, "PIT",
1917
                 SPR_NOACCESS, SPR_NOACCESS,
1918
                 &spr_read_40x_pit, &spr_write_40x_pit,
1919
                 0x00000000);
1920
    spr_register(env, SPR_40x_TCR, "TCR",
1921
                 SPR_NOACCESS, SPR_NOACCESS,
1922
                 &spr_read_generic, &spr_write_booke_tcr,
1923
                 0x00000000);
1924
    spr_register(env, SPR_40x_TSR, "TSR",
1925
                 SPR_NOACCESS, SPR_NOACCESS,
1926
                 &spr_read_generic, &spr_write_booke_tsr,
1927
                 0x00000000);
1928
}
1929

    
1930
/* SPR specific to PowerPC 405 implementation */
1931
static void gen_spr_405 (CPUPPCState *env)
1932
{
1933
    /* MMU */
1934
    spr_register(env, SPR_40x_PID, "PID",
1935
                 SPR_NOACCESS, SPR_NOACCESS,
1936
                 &spr_read_generic, &spr_write_generic,
1937
                 0x00000000);
1938
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1939
                 SPR_NOACCESS, SPR_NOACCESS,
1940
                 &spr_read_generic, &spr_write_generic,
1941
                 0x00700000);
1942
    /* Debug interface */
1943
    /* XXX : not implemented */
1944
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1945
                 SPR_NOACCESS, SPR_NOACCESS,
1946
                 &spr_read_generic, &spr_write_40x_dbcr0,
1947
                 0x00000000);
1948
    /* XXX : not implemented */
1949
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1950
                 SPR_NOACCESS, SPR_NOACCESS,
1951
                 &spr_read_generic, &spr_write_generic,
1952
                 0x00000000);
1953
    /* XXX : not implemented */
1954
    spr_register(env, SPR_40x_DBSR, "DBSR",
1955
                 SPR_NOACCESS, SPR_NOACCESS,
1956
                 &spr_read_generic, &spr_write_clear,
1957
                 /* Last reset was system reset */
1958
                 0x00000300);
1959
    /* XXX : not implemented */
1960
    spr_register(env, SPR_40x_DAC1, "DAC1",
1961
                 SPR_NOACCESS, SPR_NOACCESS,
1962
                 &spr_read_generic, &spr_write_generic,
1963
                 0x00000000);
1964
    spr_register(env, SPR_40x_DAC2, "DAC2",
1965
                 SPR_NOACCESS, SPR_NOACCESS,
1966
                 &spr_read_generic, &spr_write_generic,
1967
                 0x00000000);
1968
    /* XXX : not implemented */
1969
    spr_register(env, SPR_405_DVC1, "DVC1",
1970
                 SPR_NOACCESS, SPR_NOACCESS,
1971
                 &spr_read_generic, &spr_write_generic,
1972
                 0x00000000);
1973
    /* XXX : not implemented */
1974
    spr_register(env, SPR_405_DVC2, "DVC2",
1975
                 SPR_NOACCESS, SPR_NOACCESS,
1976
                 &spr_read_generic, &spr_write_generic,
1977
                 0x00000000);
1978
    /* XXX : not implemented */
1979
    spr_register(env, SPR_40x_IAC1, "IAC1",
1980
                 SPR_NOACCESS, SPR_NOACCESS,
1981
                 &spr_read_generic, &spr_write_generic,
1982
                 0x00000000);
1983
    spr_register(env, SPR_40x_IAC2, "IAC2",
1984
                 SPR_NOACCESS, SPR_NOACCESS,
1985
                 &spr_read_generic, &spr_write_generic,
1986
                 0x00000000);
1987
    /* XXX : not implemented */
1988
    spr_register(env, SPR_405_IAC3, "IAC3",
1989
                 SPR_NOACCESS, SPR_NOACCESS,
1990
                 &spr_read_generic, &spr_write_generic,
1991
                 0x00000000);
1992
    /* XXX : not implemented */
1993
    spr_register(env, SPR_405_IAC4, "IAC4",
1994
                 SPR_NOACCESS, SPR_NOACCESS,
1995
                 &spr_read_generic, &spr_write_generic,
1996
                 0x00000000);
1997
    /* Storage control */
1998
    /* XXX: TODO: not implemented */
1999
    spr_register(env, SPR_405_SLER, "SLER",
2000
                 SPR_NOACCESS, SPR_NOACCESS,
2001
                 &spr_read_generic, &spr_write_40x_sler,
2002
                 0x00000000);
2003
    spr_register(env, SPR_40x_ZPR, "ZPR",
2004
                 SPR_NOACCESS, SPR_NOACCESS,
2005
                 &spr_read_generic, &spr_write_generic,
2006
                 0x00000000);
2007
    /* XXX : not implemented */
2008
    spr_register(env, SPR_405_SU0R, "SU0R",
2009
                 SPR_NOACCESS, SPR_NOACCESS,
2010
                 &spr_read_generic, &spr_write_generic,
2011
                 0x00000000);
2012
    /* SPRG */
2013
    spr_register(env, SPR_USPRG0, "USPRG0",
2014
                 &spr_read_ureg, SPR_NOACCESS,
2015
                 &spr_read_ureg, SPR_NOACCESS,
2016
                 0x00000000);
2017
    spr_register(env, SPR_SPRG4, "SPRG4",
2018
                 SPR_NOACCESS, SPR_NOACCESS,
2019
                 &spr_read_generic, &spr_write_generic,
2020
                 0x00000000);
2021
    spr_register(env, SPR_SPRG5, "SPRG5",
2022
                 SPR_NOACCESS, SPR_NOACCESS,
2023
                 spr_read_generic, &spr_write_generic,
2024
                 0x00000000);
2025
    spr_register(env, SPR_SPRG6, "SPRG6",
2026
                 SPR_NOACCESS, SPR_NOACCESS,
2027
                 spr_read_generic, &spr_write_generic,
2028
                 0x00000000);
2029
    spr_register(env, SPR_SPRG7, "SPRG7",
2030
                 SPR_NOACCESS, SPR_NOACCESS,
2031
                 spr_read_generic, &spr_write_generic,
2032
                 0x00000000);
2033
    gen_spr_usprgh(env);
2034
}
2035

    
2036
/* SPR shared between PowerPC 401 & 403 implementations */
2037
static void gen_spr_401_403 (CPUPPCState *env)
2038
{
2039
    /* Time base */
2040
    spr_register(env, SPR_403_VTBL,  "TBL",
2041
                 &spr_read_tbl, SPR_NOACCESS,
2042
                 &spr_read_tbl, SPR_NOACCESS,
2043
                 0x00000000);
2044
    spr_register(env, SPR_403_TBL,   "TBL",
2045
                 SPR_NOACCESS, SPR_NOACCESS,
2046
                 SPR_NOACCESS, &spr_write_tbl,
2047
                 0x00000000);
2048
    spr_register(env, SPR_403_VTBU,  "TBU",
2049
                 &spr_read_tbu, SPR_NOACCESS,
2050
                 &spr_read_tbu, SPR_NOACCESS,
2051
                 0x00000000);
2052
    spr_register(env, SPR_403_TBU,   "TBU",
2053
                 SPR_NOACCESS, SPR_NOACCESS,
2054
                 SPR_NOACCESS, &spr_write_tbu,
2055
                 0x00000000);
2056
    /* Debug */
2057
    /* not emulated, as QEMU do not emulate caches */
2058
    spr_register(env, SPR_403_CDBCR, "CDBCR",
2059
                 SPR_NOACCESS, SPR_NOACCESS,
2060
                 &spr_read_generic, &spr_write_generic,
2061
                 0x00000000);
2062
}
2063

    
2064
/* SPR specific to PowerPC 401 implementation */
2065
static void gen_spr_401 (CPUPPCState *env)
2066
{
2067
    /* Debug interface */
2068
    /* XXX : not implemented */
2069
    spr_register(env, SPR_40x_DBCR0, "DBCR",
2070
                 SPR_NOACCESS, SPR_NOACCESS,
2071
                 &spr_read_generic, &spr_write_40x_dbcr0,
2072
                 0x00000000);
2073
    /* XXX : not implemented */
2074
    spr_register(env, SPR_40x_DBSR, "DBSR",
2075
                 SPR_NOACCESS, SPR_NOACCESS,
2076
                 &spr_read_generic, &spr_write_clear,
2077
                 /* Last reset was system reset */
2078
                 0x00000300);
2079
    /* XXX : not implemented */
2080
    spr_register(env, SPR_40x_DAC1, "DAC",
2081
                 SPR_NOACCESS, SPR_NOACCESS,
2082
                 &spr_read_generic, &spr_write_generic,
2083
                 0x00000000);
2084
    /* XXX : not implemented */
2085
    spr_register(env, SPR_40x_IAC1, "IAC",
2086
                 SPR_NOACCESS, SPR_NOACCESS,
2087
                 &spr_read_generic, &spr_write_generic,
2088
                 0x00000000);
2089
    /* Storage control */
2090
    /* XXX: TODO: not implemented */
2091
    spr_register(env, SPR_405_SLER, "SLER",
2092
                 SPR_NOACCESS, SPR_NOACCESS,
2093
                 &spr_read_generic, &spr_write_40x_sler,
2094
                 0x00000000);
2095
    /* not emulated, as QEMU never does speculative access */
2096
    spr_register(env, SPR_40x_SGR, "SGR",
2097
                 SPR_NOACCESS, SPR_NOACCESS,
2098
                 &spr_read_generic, &spr_write_generic,
2099
                 0xFFFFFFFF);
2100
    /* not emulated, as QEMU do not emulate caches */
2101
    spr_register(env, SPR_40x_DCWR, "DCWR",
2102
                 SPR_NOACCESS, SPR_NOACCESS,
2103
                 &spr_read_generic, &spr_write_generic,
2104
                 0x00000000);
2105
}
2106

    
2107
static void gen_spr_401x2 (CPUPPCState *env)
2108
{
2109
    gen_spr_401(env);
2110
    spr_register(env, SPR_40x_PID, "PID",
2111
                 SPR_NOACCESS, SPR_NOACCESS,
2112
                 &spr_read_generic, &spr_write_generic,
2113
                 0x00000000);
2114
    spr_register(env, SPR_40x_ZPR, "ZPR",
2115
                 SPR_NOACCESS, SPR_NOACCESS,
2116
                 &spr_read_generic, &spr_write_generic,
2117
                 0x00000000);
2118
}
2119

    
2120
/* SPR specific to PowerPC 403 implementation */
2121
static void gen_spr_403 (CPUPPCState *env)
2122
{
2123
    /* Debug interface */
2124
    /* XXX : not implemented */
2125
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2126
                 SPR_NOACCESS, SPR_NOACCESS,
2127
                 &spr_read_generic, &spr_write_40x_dbcr0,
2128
                 0x00000000);
2129
    /* XXX : not implemented */
2130
    spr_register(env, SPR_40x_DBSR, "DBSR",
2131
                 SPR_NOACCESS, SPR_NOACCESS,
2132
                 &spr_read_generic, &spr_write_clear,
2133
                 /* Last reset was system reset */
2134
                 0x00000300);
2135
    /* XXX : not implemented */
2136
    spr_register(env, SPR_40x_DAC1, "DAC1",
2137
                 SPR_NOACCESS, SPR_NOACCESS,
2138
                 &spr_read_generic, &spr_write_generic,
2139
                 0x00000000);
2140
    /* XXX : not implemented */
2141
    spr_register(env, SPR_40x_DAC2, "DAC2",
2142
                 SPR_NOACCESS, SPR_NOACCESS,
2143
                 &spr_read_generic, &spr_write_generic,
2144
                 0x00000000);
2145
    /* XXX : not implemented */
2146
    spr_register(env, SPR_40x_IAC1, "IAC1",
2147
                 SPR_NOACCESS, SPR_NOACCESS,
2148
                 &spr_read_generic, &spr_write_generic,
2149
                 0x00000000);
2150
    /* XXX : not implemented */
2151
    spr_register(env, SPR_40x_IAC2, "IAC2",
2152
                 SPR_NOACCESS, SPR_NOACCESS,
2153
                 &spr_read_generic, &spr_write_generic,
2154
                 0x00000000);
2155
}
2156

    
2157
static void gen_spr_403_real (CPUPPCState *env)
2158
{
2159
    spr_register(env, SPR_403_PBL1,  "PBL1",
2160
                 SPR_NOACCESS, SPR_NOACCESS,
2161
                 &spr_read_403_pbr, &spr_write_403_pbr,
2162
                 0x00000000);
2163
    spr_register(env, SPR_403_PBU1,  "PBU1",
2164
                 SPR_NOACCESS, SPR_NOACCESS,
2165
                 &spr_read_403_pbr, &spr_write_403_pbr,
2166
                 0x00000000);
2167
    spr_register(env, SPR_403_PBL2,  "PBL2",
2168
                 SPR_NOACCESS, SPR_NOACCESS,
2169
                 &spr_read_403_pbr, &spr_write_403_pbr,
2170
                 0x00000000);
2171
    spr_register(env, SPR_403_PBU2,  "PBU2",
2172
                 SPR_NOACCESS, SPR_NOACCESS,
2173
                 &spr_read_403_pbr, &spr_write_403_pbr,
2174
                 0x00000000);
2175
}
2176

    
2177
static void gen_spr_403_mmu (CPUPPCState *env)
2178
{
2179
    /* MMU */
2180
    spr_register(env, SPR_40x_PID, "PID",
2181
                 SPR_NOACCESS, SPR_NOACCESS,
2182
                 &spr_read_generic, &spr_write_generic,
2183
                 0x00000000);
2184
    spr_register(env, SPR_40x_ZPR, "ZPR",
2185
                 SPR_NOACCESS, SPR_NOACCESS,
2186
                 &spr_read_generic, &spr_write_generic,
2187
                 0x00000000);
2188
}
2189

    
2190
/* SPR specific to PowerPC compression coprocessor extension */
2191
static void gen_spr_compress (CPUPPCState *env)
2192
{
2193
    /* XXX : not implemented */
2194
    spr_register(env, SPR_401_SKR, "SKR",
2195
                 SPR_NOACCESS, SPR_NOACCESS,
2196
                 &spr_read_generic, &spr_write_generic,
2197
                 0x00000000);
2198
}
2199

    
2200
static void gen_spr_5xx_8xx (CPUPPCState *env)
2201
{
2202
    /* Exception processing */
2203
    spr_register_kvm(env, SPR_DSISR, "DSISR",
2204
                     SPR_NOACCESS, SPR_NOACCESS,
2205
                     &spr_read_generic, &spr_write_generic,
2206
                     KVM_REG_PPC_DSISR, 0x00000000);
2207
    spr_register_kvm(env, SPR_DAR, "DAR",
2208
                     SPR_NOACCESS, SPR_NOACCESS,
2209
                     &spr_read_generic, &spr_write_generic,
2210
                     KVM_REG_PPC_DAR, 0x00000000);
2211
    /* Timer */
2212
    spr_register(env, SPR_DECR, "DECR",
2213
                 SPR_NOACCESS, SPR_NOACCESS,
2214
                 &spr_read_decr, &spr_write_decr,
2215
                 0x00000000);
2216
    /* XXX : not implemented */
2217
    spr_register(env, SPR_MPC_EIE, "EIE",
2218
                 SPR_NOACCESS, SPR_NOACCESS,
2219
                 &spr_read_generic, &spr_write_generic,
2220
                 0x00000000);
2221
    /* XXX : not implemented */
2222
    spr_register(env, SPR_MPC_EID, "EID",
2223
                 SPR_NOACCESS, SPR_NOACCESS,
2224
                 &spr_read_generic, &spr_write_generic,
2225
                 0x00000000);
2226
    /* XXX : not implemented */
2227
    spr_register(env, SPR_MPC_NRI, "NRI",
2228
                 SPR_NOACCESS, SPR_NOACCESS,
2229
                 &spr_read_generic, &spr_write_generic,
2230
                 0x00000000);
2231
    /* XXX : not implemented */
2232
    spr_register(env, SPR_MPC_CMPA, "CMPA",
2233
                 SPR_NOACCESS, SPR_NOACCESS,
2234
                 &spr_read_generic, &spr_write_generic,
2235
                 0x00000000);
2236
    /* XXX : not implemented */
2237
    spr_register(env, SPR_MPC_CMPB, "CMPB",
2238
                 SPR_NOACCESS, SPR_NOACCESS,
2239
                 &spr_read_generic, &spr_write_generic,
2240
                 0x00000000);
2241
    /* XXX : not implemented */
2242
    spr_register(env, SPR_MPC_CMPC, "CMPC",
2243
                 SPR_NOACCESS, SPR_NOACCESS,
2244
                 &spr_read_generic, &spr_write_generic,
2245
                 0x00000000);
2246
    /* XXX : not implemented */
2247
    spr_register(env, SPR_MPC_CMPD, "CMPD",
2248
                 SPR_NOACCESS, SPR_NOACCESS,
2249
                 &spr_read_generic, &spr_write_generic,
2250
                 0x00000000);
2251
    /* XXX : not implemented */
2252
    spr_register(env, SPR_MPC_ECR, "ECR",
2253
                 SPR_NOACCESS, SPR_NOACCESS,
2254
                 &spr_read_generic, &spr_write_generic,
2255
                 0x00000000);
2256
    /* XXX : not implemented */
2257
    spr_register(env, SPR_MPC_DER, "DER",
2258
                 SPR_NOACCESS, SPR_NOACCESS,
2259
                 &spr_read_generic, &spr_write_generic,
2260
                 0x00000000);
2261
    /* XXX : not implemented */
2262
    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2263
                 SPR_NOACCESS, SPR_NOACCESS,
2264
                 &spr_read_generic, &spr_write_generic,
2265
                 0x00000000);
2266
    /* XXX : not implemented */
2267
    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2268
                 SPR_NOACCESS, SPR_NOACCESS,
2269
                 &spr_read_generic, &spr_write_generic,
2270
                 0x00000000);
2271
    /* XXX : not implemented */
2272
    spr_register(env, SPR_MPC_CMPE, "CMPE",
2273
                 SPR_NOACCESS, SPR_NOACCESS,
2274
                 &spr_read_generic, &spr_write_generic,
2275
                 0x00000000);
2276
    /* XXX : not implemented */
2277
    spr_register(env, SPR_MPC_CMPF, "CMPF",
2278
                 SPR_NOACCESS, SPR_NOACCESS,
2279
                 &spr_read_generic, &spr_write_generic,
2280
                 0x00000000);
2281
    /* XXX : not implemented */
2282
    spr_register(env, SPR_MPC_CMPG, "CMPG",
2283
                 SPR_NOACCESS, SPR_NOACCESS,
2284
                 &spr_read_generic, &spr_write_generic,
2285
                 0x00000000);
2286
    /* XXX : not implemented */
2287
    spr_register(env, SPR_MPC_CMPH, "CMPH",
2288
                 SPR_NOACCESS, SPR_NOACCESS,
2289
                 &spr_read_generic, &spr_write_generic,
2290
                 0x00000000);
2291
    /* XXX : not implemented */
2292
    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2293
                 SPR_NOACCESS, SPR_NOACCESS,
2294
                 &spr_read_generic, &spr_write_generic,
2295
                 0x00000000);
2296
    /* XXX : not implemented */
2297
    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2298
                 SPR_NOACCESS, SPR_NOACCESS,
2299
                 &spr_read_generic, &spr_write_generic,
2300
                 0x00000000);
2301
    /* XXX : not implemented */
2302
    spr_register(env, SPR_MPC_BAR, "BAR",
2303
                 SPR_NOACCESS, SPR_NOACCESS,
2304
                 &spr_read_generic, &spr_write_generic,
2305
                 0x00000000);
2306
    /* XXX : not implemented */
2307
    spr_register(env, SPR_MPC_DPDR, "DPDR",
2308
                 SPR_NOACCESS, SPR_NOACCESS,
2309
                 &spr_read_generic, &spr_write_generic,
2310
                 0x00000000);
2311
    /* XXX : not implemented */
2312
    spr_register(env, SPR_MPC_IMMR, "IMMR",
2313
                 SPR_NOACCESS, SPR_NOACCESS,
2314
                 &spr_read_generic, &spr_write_generic,
2315
                 0x00000000);
2316
}
2317

    
2318
static void gen_spr_5xx (CPUPPCState *env)
2319
{
2320
    /* XXX : not implemented */
2321
    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2322
                 SPR_NOACCESS, SPR_NOACCESS,
2323
                 &spr_read_generic, &spr_write_generic,
2324
                 0x00000000);
2325
    /* XXX : not implemented */
2326
    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2327
                 SPR_NOACCESS, SPR_NOACCESS,
2328
                 &spr_read_generic, &spr_write_generic,
2329
                 0x00000000);
2330
    /* XXX : not implemented */
2331
    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2332
                 SPR_NOACCESS, SPR_NOACCESS,
2333
                 &spr_read_generic, &spr_write_generic,
2334
                 0x00000000);
2335
    /* XXX : not implemented */
2336
    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2337
                 SPR_NOACCESS, SPR_NOACCESS,
2338
                 &spr_read_generic, &spr_write_generic,
2339
                 0x00000000);
2340
    /* XXX : not implemented */
2341
    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2342
                 SPR_NOACCESS, SPR_NOACCESS,
2343
                 &spr_read_generic, &spr_write_generic,
2344
                 0x00000000);
2345
    /* XXX : not implemented */
2346
    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2347
                 SPR_NOACCESS, SPR_NOACCESS,
2348
                 &spr_read_generic, &spr_write_generic,
2349
                 0x00000000);
2350
    /* XXX : not implemented */
2351
    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2352
                 SPR_NOACCESS, SPR_NOACCESS,
2353
                 &spr_read_generic, &spr_write_generic,
2354
                 0x00000000);
2355
    /* XXX : not implemented */
2356
    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2357
                 SPR_NOACCESS, SPR_NOACCESS,
2358
                 &spr_read_generic, &spr_write_generic,
2359
                 0x00000000);
2360
    /* XXX : not implemented */
2361
    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2362
                 SPR_NOACCESS, SPR_NOACCESS,
2363
                 &spr_read_generic, &spr_write_generic,
2364
                 0x00000000);
2365
    /* XXX : not implemented */
2366
    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2367
                 SPR_NOACCESS, SPR_NOACCESS,
2368
                 &spr_read_generic, &spr_write_generic,
2369
                 0x00000000);
2370
    /* XXX : not implemented */
2371
    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2372
                 SPR_NOACCESS, SPR_NOACCESS,
2373
                 &spr_read_generic, &spr_write_generic,
2374
                 0x00000000);
2375
    /* XXX : not implemented */
2376
    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2377
                 SPR_NOACCESS, SPR_NOACCESS,
2378
                 &spr_read_generic, &spr_write_generic,
2379
                 0x00000000);
2380
    /* XXX : not implemented */
2381
    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2382
                 SPR_NOACCESS, SPR_NOACCESS,
2383
                 &spr_read_generic, &spr_write_generic,
2384
                 0x00000000);
2385
    /* XXX : not implemented */
2386
    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2387
                 SPR_NOACCESS, SPR_NOACCESS,
2388
                 &spr_read_generic, &spr_write_generic,
2389
                 0x00000000);
2390
    /* XXX : not implemented */
2391
    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2392
                 SPR_NOACCESS, SPR_NOACCESS,
2393
                 &spr_read_generic, &spr_write_generic,
2394
                 0x00000000);
2395
    /* XXX : not implemented */
2396
    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2397
                 SPR_NOACCESS, SPR_NOACCESS,
2398
                 &spr_read_generic, &spr_write_generic,
2399
                 0x00000000);
2400
    /* XXX : not implemented */
2401
    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2402
                 SPR_NOACCESS, SPR_NOACCESS,
2403
                 &spr_read_generic, &spr_write_generic,
2404
                 0x00000000);
2405
    /* XXX : not implemented */
2406
    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2407
                 SPR_NOACCESS, SPR_NOACCESS,
2408
                 &spr_read_generic, &spr_write_generic,
2409
                 0x00000000);
2410
    /* XXX : not implemented */
2411
    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2412
                 SPR_NOACCESS, SPR_NOACCESS,
2413
                 &spr_read_generic, &spr_write_generic,
2414
                 0x00000000);
2415
    /* XXX : not implemented */
2416
    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2417
                 SPR_NOACCESS, SPR_NOACCESS,
2418
                 &spr_read_generic, &spr_write_generic,
2419
                 0x00000000);
2420
    /* XXX : not implemented */
2421
    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2422
                 SPR_NOACCESS, SPR_NOACCESS,
2423
                 &spr_read_generic, &spr_write_generic,
2424
                 0x00000000);
2425
}
2426

    
2427
static void gen_spr_8xx (CPUPPCState *env)
2428
{
2429
    /* XXX : not implemented */
2430
    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2431
                 SPR_NOACCESS, SPR_NOACCESS,
2432
                 &spr_read_generic, &spr_write_generic,
2433
                 0x00000000);
2434
    /* XXX : not implemented */
2435
    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2436
                 SPR_NOACCESS, SPR_NOACCESS,
2437
                 &spr_read_generic, &spr_write_generic,
2438
                 0x00000000);
2439
    /* XXX : not implemented */
2440
    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2441
                 SPR_NOACCESS, SPR_NOACCESS,
2442
                 &spr_read_generic, &spr_write_generic,
2443
                 0x00000000);
2444
    /* XXX : not implemented */
2445
    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2446
                 SPR_NOACCESS, SPR_NOACCESS,
2447
                 &spr_read_generic, &spr_write_generic,
2448
                 0x00000000);
2449
    /* XXX : not implemented */
2450
    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2451
                 SPR_NOACCESS, SPR_NOACCESS,
2452
                 &spr_read_generic, &spr_write_generic,
2453
                 0x00000000);
2454
    /* XXX : not implemented */
2455
    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2456
                 SPR_NOACCESS, SPR_NOACCESS,
2457
                 &spr_read_generic, &spr_write_generic,
2458
                 0x00000000);
2459
    /* XXX : not implemented */
2460
    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2461
                 SPR_NOACCESS, SPR_NOACCESS,
2462
                 &spr_read_generic, &spr_write_generic,
2463
                 0x00000000);
2464
    /* XXX : not implemented */
2465
    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2466
                 SPR_NOACCESS, SPR_NOACCESS,
2467
                 &spr_read_generic, &spr_write_generic,
2468
                 0x00000000);
2469
    /* XXX : not implemented */
2470
    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2471
                 SPR_NOACCESS, SPR_NOACCESS,
2472
                 &spr_read_generic, &spr_write_generic,
2473
                 0x00000000);
2474
    /* XXX : not implemented */
2475
    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2476
                 SPR_NOACCESS, SPR_NOACCESS,
2477
                 &spr_read_generic, &spr_write_generic,
2478
                 0x00000000);
2479
    /* XXX : not implemented */
2480
    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2481
                 SPR_NOACCESS, SPR_NOACCESS,
2482
                 &spr_read_generic, &spr_write_generic,
2483
                 0x00000000);
2484
    /* XXX : not implemented */
2485
    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2486
                 SPR_NOACCESS, SPR_NOACCESS,
2487
                 &spr_read_generic, &spr_write_generic,
2488
                 0x00000000);
2489
    /* XXX : not implemented */
2490
    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2491
                 SPR_NOACCESS, SPR_NOACCESS,
2492
                 &spr_read_generic, &spr_write_generic,
2493
                 0x00000000);
2494
    /* XXX : not implemented */
2495
    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2496
                 SPR_NOACCESS, SPR_NOACCESS,
2497
                 &spr_read_generic, &spr_write_generic,
2498
                 0x00000000);
2499
    /* XXX : not implemented */
2500
    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2501
                 SPR_NOACCESS, SPR_NOACCESS,
2502
                 &spr_read_generic, &spr_write_generic,
2503
                 0x00000000);
2504
    /* XXX : not implemented */
2505
    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2506
                 SPR_NOACCESS, SPR_NOACCESS,
2507
                 &spr_read_generic, &spr_write_generic,
2508
                 0x00000000);
2509
    /* XXX : not implemented */
2510
    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2511
                 SPR_NOACCESS, SPR_NOACCESS,
2512
                 &spr_read_generic, &spr_write_generic,
2513
                 0x00000000);
2514
    /* XXX : not implemented */
2515
    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2516
                 SPR_NOACCESS, SPR_NOACCESS,
2517
                 &spr_read_generic, &spr_write_generic,
2518
                 0x00000000);
2519
    /* XXX : not implemented */
2520
    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2521
                 SPR_NOACCESS, SPR_NOACCESS,
2522
                 &spr_read_generic, &spr_write_generic,
2523
                 0x00000000);
2524
    /* XXX : not implemented */
2525
    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2526
                 SPR_NOACCESS, SPR_NOACCESS,
2527
                 &spr_read_generic, &spr_write_generic,
2528
                 0x00000000);
2529
    /* XXX : not implemented */
2530
    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2531
                 SPR_NOACCESS, SPR_NOACCESS,
2532
                 &spr_read_generic, &spr_write_generic,
2533
                 0x00000000);
2534
    /* XXX : not implemented */
2535
    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2536
                 SPR_NOACCESS, SPR_NOACCESS,
2537
                 &spr_read_generic, &spr_write_generic,
2538
                 0x00000000);
2539
    /* XXX : not implemented */
2540
    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2541
                 SPR_NOACCESS, SPR_NOACCESS,
2542
                 &spr_read_generic, &spr_write_generic,
2543
                 0x00000000);
2544
    /* XXX : not implemented */
2545
    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2546
                 SPR_NOACCESS, SPR_NOACCESS,
2547
                 &spr_read_generic, &spr_write_generic,
2548
                 0x00000000);
2549
    /* XXX : not implemented */
2550
    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2551
                 SPR_NOACCESS, SPR_NOACCESS,
2552
                 &spr_read_generic, &spr_write_generic,
2553
                 0x00000000);
2554
}
2555

    
2556
// XXX: TODO
2557
/*
2558
 * AMR     => SPR 29 (Power 2.04)
2559
 * CTRL    => SPR 136 (Power 2.04)
2560
 * CTRL    => SPR 152 (Power 2.04)
2561
 * SCOMC   => SPR 276 (64 bits ?)
2562
 * SCOMD   => SPR 277 (64 bits ?)
2563
 * TBU40   => SPR 286 (Power 2.04 hypv)
2564
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2565
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2566
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2567
 * HDAR    => SPR 307 (Power 2.04 hypv)
2568
 * PURR    => SPR 309 (Power 2.04 hypv)
2569
 * HDEC    => SPR 310 (Power 2.04 hypv)
2570
 * HIOR    => SPR 311 (hypv)
2571
 * RMOR    => SPR 312 (970)
2572
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2573
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2574
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2575
 * LPCR    => SPR 316 (970)
2576
 * LPIDR   => SPR 317 (970)
2577
 * EPR     => SPR 702 (Power 2.04 emb)
2578
 * perf    => 768-783 (Power 2.04)
2579
 * perf    => 784-799 (Power 2.04)
2580
 * PPR     => SPR 896 (Power 2.04)
2581
 * EPLC    => SPR 947 (Power 2.04 emb)
2582
 * EPSC    => SPR 948 (Power 2.04 emb)
2583
 * DABRX   => 1015    (Power 2.04 hypv)
2584
 * FPECR   => SPR 1022 (?)
2585
 * ... and more (thermal management, performance counters, ...)
2586
 */
2587

    
2588
/*****************************************************************************/
2589
/* Exception vectors models                                                  */
2590
static void init_excp_4xx_real (CPUPPCState *env)
2591
{
2592
#if !defined(CONFIG_USER_ONLY)
2593
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2594
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2595
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2596
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2597
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2598
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2599
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2600
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2601
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2602
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2603
    env->ivor_mask = 0x0000FFF0UL;
2604
    env->ivpr_mask = 0xFFFF0000UL;
2605
    /* Hardware reset vector */
2606
    env->hreset_vector = 0xFFFFFFFCUL;
2607
#endif
2608
}
2609

    
2610
static void init_excp_4xx_softmmu (CPUPPCState *env)
2611
{
2612
#if !defined(CONFIG_USER_ONLY)
2613
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2614
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2615
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2616
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2617
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2618
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2619
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2620
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2621
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2622
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2623
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2624
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2625
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2626
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2627
    env->ivor_mask = 0x0000FFF0UL;
2628
    env->ivpr_mask = 0xFFFF0000UL;
2629
    /* Hardware reset vector */
2630
    env->hreset_vector = 0xFFFFFFFCUL;
2631
#endif
2632
}
2633

    
2634
static void init_excp_MPC5xx (CPUPPCState *env)
2635
{
2636
#if !defined(CONFIG_USER_ONLY)
2637
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2638
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2639
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2640
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2641
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2642
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2643
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2644
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2645
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2646
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2647
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2648
    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2649
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2650
    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2651
    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2652
    env->ivor_mask = 0x0000FFF0UL;
2653
    env->ivpr_mask = 0xFFFF0000UL;
2654
    /* Hardware reset vector */
2655
    env->hreset_vector = 0x00000100UL;
2656
#endif
2657
}
2658

    
2659
static void init_excp_MPC8xx (CPUPPCState *env)
2660
{
2661
#if !defined(CONFIG_USER_ONLY)
2662
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2663
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2664
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2665
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2666
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2667
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2668
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2669
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2670
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2671
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2672
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2673
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2674
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2675
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2676
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2677
    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2678
    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2679
    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2680
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2681
    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2682
    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2683
    env->ivor_mask = 0x0000FFF0UL;
2684
    env->ivpr_mask = 0xFFFF0000UL;
2685
    /* Hardware reset vector */
2686
    env->hreset_vector = 0x00000100UL;
2687
#endif
2688
}
2689

    
2690
static void init_excp_G2 (CPUPPCState *env)
2691
{
2692
#if !defined(CONFIG_USER_ONLY)
2693
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2694
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2695
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2696
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2697
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2698
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2699
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2700
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2701
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2702
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2703
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2704
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2705
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2706
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2707
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2708
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2709
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2710
    /* Hardware reset vector */
2711
    env->hreset_vector = 0x00000100UL;
2712
#endif
2713
}
2714

    
2715
static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2716
{
2717
#if !defined(CONFIG_USER_ONLY)
2718
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2719
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2720
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2721
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2722
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2723
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2724
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2725
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2726
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2727
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2728
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2729
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2730
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2731
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2732
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2733
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2734
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2735
    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2736
    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2737
    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2738
    env->ivor_mask = 0x0000FFF7UL;
2739
    env->ivpr_mask = ivpr_mask;
2740
    /* Hardware reset vector */
2741
    env->hreset_vector = 0xFFFFFFFCUL;
2742
#endif
2743
}
2744

    
2745
static void init_excp_BookE (CPUPPCState *env)
2746
{
2747
#if !defined(CONFIG_USER_ONLY)
2748
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2749
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2750
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2751
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2752
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2753
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2754
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2755
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2756
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2757
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2758
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2759
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2760
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2761
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2762
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2763
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2764
    env->ivor_mask = 0x0000FFE0UL;
2765
    env->ivpr_mask = 0xFFFF0000UL;
2766
    /* Hardware reset vector */
2767
    env->hreset_vector = 0xFFFFFFFCUL;
2768
#endif
2769
}
2770

    
2771
static void init_excp_601 (CPUPPCState *env)
2772
{
2773
#if !defined(CONFIG_USER_ONLY)
2774
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2775
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2776
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2777
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2778
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2779
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2780
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2781
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2782
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2783
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2784
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2785
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2786
    /* Hardware reset vector */
2787
    env->hreset_vector = 0x00000100UL;
2788
#endif
2789
}
2790

    
2791
static void init_excp_602 (CPUPPCState *env)
2792
{
2793
#if !defined(CONFIG_USER_ONLY)
2794
    /* XXX: exception prefix has a special behavior on 602 */
2795
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2796
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2797
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2798
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2799
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2800
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2801
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2802
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2803
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2804
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2805
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2806
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2807
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2808
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2809
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2810
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2811
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2812
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2813
    /* Hardware reset vector */
2814
    env->hreset_vector = 0x00000100UL;
2815
#endif
2816
}
2817

    
2818
static void init_excp_603 (CPUPPCState *env)
2819
{
2820
#if !defined(CONFIG_USER_ONLY)
2821
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2822
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2823
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2824
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2825
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2826
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2827
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2828
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2829
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2830
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2831
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2832
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2833
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2834
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2835
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2836
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2837
    /* Hardware reset vector */
2838
    env->hreset_vector = 0x00000100UL;
2839
#endif
2840
}
2841

    
2842
static void init_excp_604 (CPUPPCState *env)
2843
{
2844
#if !defined(CONFIG_USER_ONLY)
2845
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2846
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2847
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2848
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2849
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2850
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2851
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2852
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2853
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2854
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2855
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2856
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2857
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2858
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2859
    /* Hardware reset vector */
2860
    env->hreset_vector = 0x00000100UL;
2861
#endif
2862
}
2863

    
2864
static void init_excp_7x0 (CPUPPCState *env)
2865
{
2866
#if !defined(CONFIG_USER_ONLY)
2867
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2868
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2869
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2870
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2871
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2872
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2873
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2874
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2875
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2876
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2877
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2878
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2879
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2880
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2881
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2882
    /* Hardware reset vector */
2883
    env->hreset_vector = 0x00000100UL;
2884
#endif
2885
}
2886

    
2887
static void init_excp_750cl (CPUPPCState *env)
2888
{
2889
#if !defined(CONFIG_USER_ONLY)
2890
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2891
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2892
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2893
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2894
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2896
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2897
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2898
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2899
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2900
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2901
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2902
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2903
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2904
    /* Hardware reset vector */
2905
    env->hreset_vector = 0x00000100UL;
2906
#endif
2907
}
2908

    
2909
static void init_excp_750cx (CPUPPCState *env)
2910
{
2911
#if !defined(CONFIG_USER_ONLY)
2912
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2913
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2914
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2915
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2916
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2917
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2918
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2919
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2920
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2921
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2922
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2923
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2924
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2925
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2926
    /* Hardware reset vector */
2927
    env->hreset_vector = 0x00000100UL;
2928
#endif
2929
}
2930

    
2931
/* XXX: Check if this is correct */
2932
static void init_excp_7x5 (CPUPPCState *env)
2933
{
2934
#if !defined(CONFIG_USER_ONLY)
2935
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2936
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2937
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2938
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2939
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2940
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2941
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2942
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2943
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2944
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2945
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2946
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2947
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2948
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2949
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2950
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2951
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2952
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2953
    /* Hardware reset vector */
2954
    env->hreset_vector = 0x00000100UL;
2955
#endif
2956
}
2957

    
2958
static void init_excp_7400 (CPUPPCState *env)
2959
{
2960
#if !defined(CONFIG_USER_ONLY)
2961
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2962
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2963
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2964
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2965
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2967
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2968
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2969
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2970
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2971
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2972
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2973
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2974
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2975
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2976
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2977
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2978
    /* Hardware reset vector */
2979
    env->hreset_vector = 0x00000100UL;
2980
#endif
2981
}
2982

    
2983
static void init_excp_7450 (CPUPPCState *env)
2984
{
2985
#if !defined(CONFIG_USER_ONLY)
2986
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2987
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2988
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2989
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2990
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2991
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2992
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2993
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2994
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2995
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2996
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2997
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2998
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2999
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3000
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3001
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3002
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3003
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3004
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3005
    /* Hardware reset vector */
3006
    env->hreset_vector = 0x00000100UL;
3007
#endif
3008
}
3009

    
3010
#if defined (TARGET_PPC64)
3011
static void init_excp_970 (CPUPPCState *env)
3012
{
3013
#if !defined(CONFIG_USER_ONLY)
3014
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3015
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3016
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3017
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3018
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3019
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3020
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3021
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3022
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3023
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3024
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3025
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3026
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3027
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3028
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3029
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3030
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3031
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3032
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3033
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3034
    /* Hardware reset vector */
3035
    env->hreset_vector = 0x0000000000000100ULL;
3036
#endif
3037
}
3038

    
3039
static void init_excp_POWER7 (CPUPPCState *env)
3040
{
3041
#if !defined(CONFIG_USER_ONLY)
3042
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3043
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3044
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3045
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3046
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3047
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3048
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3049
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3050
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3051
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3052
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3053
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3054
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3055
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3056
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3057
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3058
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3059
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3060
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3061
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3062
    /* Hardware reset vector */
3063
    env->hreset_vector = 0x0000000000000100ULL;
3064
#endif
3065
}
3066
#endif
3067

    
3068
/*****************************************************************************/
3069
/* Power management enable checks                                            */
3070
static int check_pow_none (CPUPPCState *env)
3071
{
3072
    return 0;
3073
}
3074

    
3075
static int check_pow_nocheck (CPUPPCState *env)
3076
{
3077
    return 1;
3078
}
3079

    
3080
static int check_pow_hid0 (CPUPPCState *env)
3081
{
3082
    if (env->spr[SPR_HID0] & 0x00E00000)
3083
        return 1;
3084

    
3085
    return 0;
3086
}
3087

    
3088
static int check_pow_hid0_74xx (CPUPPCState *env)
3089
{
3090
    if (env->spr[SPR_HID0] & 0x00600000)
3091
        return 1;
3092

    
3093
    return 0;
3094
}
3095

    
3096
/*****************************************************************************/
3097
/* PowerPC implementations definitions                                       */
3098

    
3099
#define POWERPC_FAMILY(_name)                                               \
3100
    static void                                                             \
3101
    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3102
                                                                            \
3103
    static const TypeInfo                                                   \
3104
    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3105
        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3106
        .parent = TYPE_POWERPC_CPU,                                         \
3107
        .abstract = true,                                                   \
3108
        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3109
    };                                                                      \
3110
                                                                            \
3111
    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3112
    {                                                                       \
3113
        type_register_static(                                               \
3114
            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3115
    }                                                                       \
3116
                                                                            \
3117
    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3118
                                                                            \
3119
    static void glue(glue(ppc_, _name), _cpu_family_class_init)
3120

    
3121
static void init_proc_401 (CPUPPCState *env)
3122
{
3123
    gen_spr_40x(env);
3124
    gen_spr_401_403(env);
3125
    gen_spr_401(env);
3126
    init_excp_4xx_real(env);
3127
    env->dcache_line_size = 32;
3128
    env->icache_line_size = 32;
3129
    /* Allocate hardware IRQ controller */
3130
    ppc40x_irq_init(env);
3131

    
3132
    SET_FIT_PERIOD(12, 16, 20, 24);
3133
    SET_WDT_PERIOD(16, 20, 24, 28);
3134
}
3135

    
3136
POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3137
{
3138
    DeviceClass *dc = DEVICE_CLASS(oc);
3139
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3140

    
3141
    dc->desc = "PowerPC 401";
3142
    pcc->init_proc = init_proc_401;
3143
    pcc->check_pow = check_pow_nocheck;
3144
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3145
                       PPC_WRTEE | PPC_DCR |
3146
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3147
                       PPC_CACHE_DCBZ |
3148
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3149
                       PPC_4xx_COMMON | PPC_40x_EXCP;
3150
    pcc->msr_mask = 0x00000000000FD201ULL;
3151
    pcc->mmu_model = POWERPC_MMU_REAL;
3152
    pcc->excp_model = POWERPC_EXCP_40x;
3153
    pcc->bus_model = PPC_FLAGS_INPUT_401;
3154
    pcc->bfd_mach = bfd_mach_ppc_403;
3155
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3156
                 POWERPC_FLAG_BUS_CLK;
3157
}
3158

    
3159
static void init_proc_401x2 (CPUPPCState *env)
3160
{
3161
    gen_spr_40x(env);
3162
    gen_spr_401_403(env);
3163
    gen_spr_401x2(env);
3164
    gen_spr_compress(env);
3165
    /* Memory management */
3166
#if !defined(CONFIG_USER_ONLY)
3167
    env->nb_tlb = 64;
3168
    env->nb_ways = 1;
3169
    env->id_tlbs = 0;
3170
    env->tlb_type = TLB_EMB;
3171
#endif
3172
    init_excp_4xx_softmmu(env);
3173
    env->dcache_line_size = 32;
3174
    env->icache_line_size = 32;
3175
    /* Allocate hardware IRQ controller */
3176
    ppc40x_irq_init(env);
3177

    
3178
    SET_FIT_PERIOD(12, 16, 20, 24);
3179
    SET_WDT_PERIOD(16, 20, 24, 28);
3180
}
3181

    
3182
POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3183
{
3184
    DeviceClass *dc = DEVICE_CLASS(oc);
3185
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3186

    
3187
    dc->desc = "PowerPC 401x2";
3188
    pcc->init_proc = init_proc_401x2;
3189
    pcc->check_pow = check_pow_nocheck;
3190
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3191
                       PPC_DCR | PPC_WRTEE |
3192
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3193
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3194
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3195
                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3196
                       PPC_4xx_COMMON | PPC_40x_EXCP;
3197
    pcc->msr_mask = 0x00000000001FD231ULL;
3198
    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3199
    pcc->excp_model = POWERPC_EXCP_40x;
3200
    pcc->bus_model = PPC_FLAGS_INPUT_401;
3201
    pcc->bfd_mach = bfd_mach_ppc_403;
3202
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3203
                 POWERPC_FLAG_BUS_CLK;
3204
}
3205

    
3206
static void init_proc_401x3 (CPUPPCState *env)
3207
{
3208
    gen_spr_40x(env);
3209
    gen_spr_401_403(env);
3210
    gen_spr_401(env);
3211
    gen_spr_401x2(env);
3212
    gen_spr_compress(env);
3213
    init_excp_4xx_softmmu(env);
3214
    env->dcache_line_size = 32;
3215
    env->icache_line_size = 32;
3216
    /* Allocate hardware IRQ controller */
3217
    ppc40x_irq_init(env);
3218

    
3219
    SET_FIT_PERIOD(12, 16, 20, 24);
3220
    SET_WDT_PERIOD(16, 20, 24, 28);
3221
}
3222

    
3223
POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3224
{
3225
    DeviceClass *dc = DEVICE_CLASS(oc);
3226
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3227

    
3228
    dc->desc = "PowerPC 401x3";
3229
    pcc->init_proc = init_proc_401x3;
3230
    pcc->check_pow = check_pow_nocheck;
3231
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3232
                       PPC_DCR | PPC_WRTEE |
3233
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3234
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3235
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3236
                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3237
                       PPC_4xx_COMMON | PPC_40x_EXCP;
3238
    pcc->msr_mask = 0x00000000001FD631ULL;
3239
    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3240
    pcc->excp_model = POWERPC_EXCP_40x;
3241
    pcc->bus_model = PPC_FLAGS_INPUT_401;
3242
    pcc->bfd_mach = bfd_mach_ppc_403;
3243
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3244
                 POWERPC_FLAG_BUS_CLK;
3245
}
3246

    
3247
static void init_proc_IOP480 (CPUPPCState *env)
3248
{
3249
    gen_spr_40x(env);
3250
    gen_spr_401_403(env);
3251
    gen_spr_401x2(env);
3252
    gen_spr_compress(env);
3253
    /* Memory management */
3254
#if !defined(CONFIG_USER_ONLY)
3255
    env->nb_tlb = 64;
3256
    env->nb_ways = 1;
3257
    env->id_tlbs = 0;
3258
    env->tlb_type = TLB_EMB;
3259
#endif
3260
    init_excp_4xx_softmmu(env);
3261
    env->dcache_line_size = 32;
3262
    env->icache_line_size = 32;
3263
    /* Allocate hardware IRQ controller */
3264
    ppc40x_irq_init(env);
3265

    
3266
    SET_FIT_PERIOD(8, 12, 16, 20);
3267
    SET_WDT_PERIOD(16, 20, 24, 28);
3268
}
3269

    
3270
POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3271
{
3272
    DeviceClass *dc = DEVICE_CLASS(oc);
3273
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3274

    
3275
    dc->desc = "IOP480";
3276
    pcc->init_proc = init_proc_IOP480;
3277
    pcc->check_pow = check_pow_nocheck;
3278
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3279
                       PPC_DCR | PPC_WRTEE |
3280
                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
3281
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3282
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3283
                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3284
                       PPC_4xx_COMMON | PPC_40x_EXCP;
3285
    pcc->msr_mask = 0x00000000001FD231ULL;
3286
    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3287
    pcc->excp_model = POWERPC_EXCP_40x;
3288
    pcc->bus_model = PPC_FLAGS_INPUT_401;
3289
    pcc->bfd_mach = bfd_mach_ppc_403;
3290
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3291
                 POWERPC_FLAG_BUS_CLK;
3292
}
3293

    
3294
static void init_proc_403 (CPUPPCState *env)
3295
{
3296
    gen_spr_40x(env);
3297
    gen_spr_401_403(env);
3298
    gen_spr_403(env);
3299
    gen_spr_403_real(env);
3300
    init_excp_4xx_real(env);
3301
    env->dcache_line_size = 32;
3302
    env->icache_line_size = 32;
3303
    /* Allocate hardware IRQ controller */
3304
    ppc40x_irq_init(env);
3305

    
3306
    SET_FIT_PERIOD(8, 12, 16, 20);
3307
    SET_WDT_PERIOD(16, 20, 24, 28);
3308
}
3309

    
3310
POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3311
{
3312
    DeviceClass *dc = DEVICE_CLASS(oc);
3313
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3314

    
3315
    dc->desc = "PowerPC 403";
3316
    pcc->init_proc = init_proc_403;
3317
    pcc->check_pow = check_pow_nocheck;
3318
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3319
                       PPC_DCR | PPC_WRTEE |
3320
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3321
                       PPC_CACHE_DCBZ |
3322
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3323
                       PPC_4xx_COMMON | PPC_40x_EXCP;
3324
    pcc->msr_mask = 0x000000000007D00DULL;
3325
    pcc->mmu_model = POWERPC_MMU_REAL;
3326
    pcc->excp_model = POWERPC_EXCP_40x;
3327
    pcc->bus_model = PPC_FLAGS_INPUT_401;
3328
    pcc->bfd_mach = bfd_mach_ppc_403;
3329
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3330
                 POWERPC_FLAG_BUS_CLK;
3331
}
3332

    
3333
static void init_proc_403GCX (CPUPPCState *env)
3334
{
3335
    gen_spr_40x(env);
3336
    gen_spr_401_403(env);
3337
    gen_spr_403(env);
3338
    gen_spr_403_real(env);
3339
    gen_spr_403_mmu(env);
3340
    /* Bus access control */
3341
    /* not emulated, as QEMU never does speculative access */
3342
    spr_register(env, SPR_40x_SGR, "SGR",
3343
                 SPR_NOACCESS, SPR_NOACCESS,
3344
                 &spr_read_generic, &spr_write_generic,
3345
                 0xFFFFFFFF);
3346
    /* not emulated, as QEMU do not emulate caches */
3347
    spr_register(env, SPR_40x_DCWR, "DCWR",
3348
                 SPR_NOACCESS, SPR_NOACCESS,
3349
                 &spr_read_generic, &spr_write_generic,
3350
                 0x00000000);
3351
    /* Memory management */
3352
#if !defined(CONFIG_USER_ONLY)
3353
    env->nb_tlb = 64;
3354
    env->nb_ways = 1;
3355
    env->id_tlbs = 0;
3356
    env->tlb_type = TLB_EMB;
3357
#endif
3358
    init_excp_4xx_softmmu(env);
3359
    env->dcache_line_size = 32;
3360
    env->icache_line_size = 32;
3361
    /* Allocate hardware IRQ controller */
3362
    ppc40x_irq_init(env);
3363

    
3364
    SET_FIT_PERIOD(8, 12, 16, 20);
3365
    SET_WDT_PERIOD(16, 20, 24, 28);
3366
}
3367

    
3368
POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3369
{
3370
    DeviceClass *dc = DEVICE_CLASS(oc);
3371
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3372

    
3373
    dc->desc = "PowerPC 403 GCX";
3374
    pcc->init_proc = init_proc_403GCX;
3375
    pcc->check_pow = check_pow_nocheck;
3376
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3377
                       PPC_DCR | PPC_WRTEE |
3378
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3379
                       PPC_CACHE_DCBZ |
3380
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3381
                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3382
                       PPC_4xx_COMMON | PPC_40x_EXCP;
3383
    pcc->msr_mask = 0x000000000007D00DULL;
3384
    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3385
    pcc->excp_model = POWERPC_EXCP_40x;
3386
    pcc->bus_model = PPC_FLAGS_INPUT_401;
3387
    pcc->bfd_mach = bfd_mach_ppc_403;
3388
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3389
                 POWERPC_FLAG_BUS_CLK;
3390
}
3391

    
3392
static void init_proc_405 (CPUPPCState *env)
3393
{
3394
    /* Time base */
3395
    gen_tbl(env);
3396
    gen_spr_40x(env);
3397
    gen_spr_405(env);
3398
    /* Bus access control */
3399
    /* not emulated, as QEMU never does speculative access */
3400
    spr_register(env, SPR_40x_SGR, "SGR",
3401
                 SPR_NOACCESS, SPR_NOACCESS,
3402
                 &spr_read_generic, &spr_write_generic,
3403
                 0xFFFFFFFF);
3404
    /* not emulated, as QEMU do not emulate caches */
3405
    spr_register(env, SPR_40x_DCWR, "DCWR",
3406
                 SPR_NOACCESS, SPR_NOACCESS,
3407
                 &spr_read_generic, &spr_write_generic,
3408
                 0x00000000);
3409
    /* Memory management */
3410
#if !defined(CONFIG_USER_ONLY)
3411
    env->nb_tlb = 64;
3412
    env->nb_ways = 1;
3413
    env->id_tlbs = 0;
3414
    env->tlb_type = TLB_EMB;
3415
#endif
3416
    init_excp_4xx_softmmu(env);
3417
    env->dcache_line_size = 32;
3418
    env->icache_line_size = 32;
3419
    /* Allocate hardware IRQ controller */
3420
    ppc40x_irq_init(env);
3421

    
3422
    SET_FIT_PERIOD(8, 12, 16, 20);
3423
    SET_WDT_PERIOD(16, 20, 24, 28);
3424
}
3425

    
3426
POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3427
{
3428
    DeviceClass *dc = DEVICE_CLASS(oc);
3429
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3430

    
3431
    dc->desc = "PowerPC 405";
3432
    pcc->init_proc = init_proc_405;
3433
    pcc->check_pow = check_pow_nocheck;
3434
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3435
                       PPC_DCR | PPC_WRTEE |
3436
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3437
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3438
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3439
                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3440
                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3441
    pcc->msr_mask = 0x000000000006E630ULL;
3442
    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3443
    pcc->excp_model = POWERPC_EXCP_40x;
3444
    pcc->bus_model = PPC_FLAGS_INPUT_405;
3445
    pcc->bfd_mach = bfd_mach_ppc_403;
3446
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3447
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3448
}
3449

    
3450
static void init_proc_440EP (CPUPPCState *env)
3451
{
3452
    /* Time base */
3453
    gen_tbl(env);
3454
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3455
    gen_spr_440(env);
3456
    gen_spr_usprgh(env);
3457
    /* Processor identification */
3458
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3459
                 SPR_NOACCESS, SPR_NOACCESS,
3460
                 &spr_read_generic, &spr_write_pir,
3461
                 0x00000000);
3462
    /* XXX : not implemented */
3463
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3464
                 SPR_NOACCESS, SPR_NOACCESS,
3465
                 &spr_read_generic, &spr_write_generic,
3466
                 0x00000000);
3467
    /* XXX : not implemented */
3468
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3469
                 SPR_NOACCESS, SPR_NOACCESS,
3470
                 &spr_read_generic, &spr_write_generic,
3471
                 0x00000000);
3472
    /* XXX : not implemented */
3473
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3474
                 SPR_NOACCESS, SPR_NOACCESS,
3475
                 &spr_read_generic, &spr_write_generic,
3476
                 0x00000000);
3477
    /* XXX : not implemented */
3478
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3479
                 SPR_NOACCESS, SPR_NOACCESS,
3480
                 &spr_read_generic, &spr_write_generic,
3481
                 0x00000000);
3482
    /* XXX : not implemented */
3483
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3484
                 SPR_NOACCESS, SPR_NOACCESS,
3485
                 &spr_read_generic, &spr_write_generic,
3486
                 0x00000000);
3487
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3488
                 SPR_NOACCESS, SPR_NOACCESS,
3489
                 &spr_read_generic, &spr_write_generic,
3490
                 0x00000000);
3491
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3492
                 SPR_NOACCESS, SPR_NOACCESS,
3493
                 &spr_read_generic, &spr_write_generic,
3494
                 0x00000000);
3495
    /* XXX : not implemented */
3496
    spr_register(env, SPR_440_CCR1, "CCR1",
3497
                 SPR_NOACCESS, SPR_NOACCESS,
3498
                 &spr_read_generic, &spr_write_generic,
3499
                 0x00000000);
3500
    /* Memory management */
3501
#if !defined(CONFIG_USER_ONLY)
3502
    env->nb_tlb = 64;
3503
    env->nb_ways = 1;
3504
    env->id_tlbs = 0;
3505
    env->tlb_type = TLB_EMB;
3506
#endif
3507
    init_excp_BookE(env);
3508
    env->dcache_line_size = 32;
3509
    env->icache_line_size = 32;
3510
    ppc40x_irq_init(env);
3511

    
3512
    SET_FIT_PERIOD(12, 16, 20, 24);
3513
    SET_WDT_PERIOD(20, 24, 28, 32);
3514
}
3515

    
3516
POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3517
{
3518
    DeviceClass *dc = DEVICE_CLASS(oc);
3519
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3520

    
3521
    dc->desc = "PowerPC 440 EP";
3522
    pcc->init_proc = init_proc_440EP;
3523
    pcc->check_pow = check_pow_nocheck;
3524
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3525
                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3526
                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3527
                       PPC_FLOAT_STFIWX |
3528
                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3529
                       PPC_CACHE | PPC_CACHE_ICBI |
3530
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3531
                       PPC_MEM_TLBSYNC | PPC_MFTB |
3532
                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3533
                       PPC_440_SPEC;
3534
    pcc->msr_mask = 0x000000000006FF30ULL;
3535
    pcc->mmu_model = POWERPC_MMU_BOOKE;
3536
    pcc->excp_model = POWERPC_EXCP_BOOKE;
3537
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3538
    pcc->bfd_mach = bfd_mach_ppc_403;
3539
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3540
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3541
}
3542

    
3543
static void init_proc_440GP (CPUPPCState *env)
3544
{
3545
    /* Time base */
3546
    gen_tbl(env);
3547
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3548
    gen_spr_440(env);
3549
    gen_spr_usprgh(env);
3550
    /* Processor identification */
3551
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3552
                 SPR_NOACCESS, SPR_NOACCESS,
3553
                 &spr_read_generic, &spr_write_pir,
3554
                 0x00000000);
3555
    /* XXX : not implemented */
3556
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3557
                 SPR_NOACCESS, SPR_NOACCESS,
3558
                 &spr_read_generic, &spr_write_generic,
3559
                 0x00000000);
3560
    /* XXX : not implemented */
3561
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3562
                 SPR_NOACCESS, SPR_NOACCESS,
3563
                 &spr_read_generic, &spr_write_generic,
3564
                 0x00000000);
3565
    /* XXX : not implemented */
3566
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3567
                 SPR_NOACCESS, SPR_NOACCESS,
3568
                 &spr_read_generic, &spr_write_generic,
3569
                 0x00000000);
3570
    /* XXX : not implemented */
3571
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3572
                 SPR_NOACCESS, SPR_NOACCESS,
3573
                 &spr_read_generic, &spr_write_generic,
3574
                 0x00000000);
3575
    /* Memory management */
3576
#if !defined(CONFIG_USER_ONLY)
3577
    env->nb_tlb = 64;
3578
    env->nb_ways = 1;
3579
    env->id_tlbs = 0;
3580
    env->tlb_type = TLB_EMB;
3581
#endif
3582
    init_excp_BookE(env);
3583
    env->dcache_line_size = 32;
3584
    env->icache_line_size = 32;
3585
    /* XXX: TODO: allocate internal IRQ controller */
3586

    
3587
    SET_FIT_PERIOD(12, 16, 20, 24);
3588
    SET_WDT_PERIOD(20, 24, 28, 32);
3589
}
3590

    
3591
POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3592
{
3593
    DeviceClass *dc = DEVICE_CLASS(oc);
3594
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3595

    
3596
    dc->desc = "PowerPC 440 GP";
3597
    pcc->init_proc = init_proc_440GP;
3598
    pcc->check_pow = check_pow_nocheck;
3599
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3600
                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3601
                       PPC_CACHE | PPC_CACHE_ICBI |
3602
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3603
                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3604
                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3605
                       PPC_440_SPEC;
3606
    pcc->msr_mask = 0x000000000006FF30ULL;
3607
    pcc->mmu_model = POWERPC_MMU_BOOKE;
3608
    pcc->excp_model = POWERPC_EXCP_BOOKE;
3609
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3610
    pcc->bfd_mach = bfd_mach_ppc_403;
3611
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3612
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3613
}
3614

    
3615
static void init_proc_440x4 (CPUPPCState *env)
3616
{
3617
    /* Time base */
3618
    gen_tbl(env);
3619
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3620
    gen_spr_440(env);
3621
    gen_spr_usprgh(env);
3622
    /* Processor identification */
3623
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3624
                 SPR_NOACCESS, SPR_NOACCESS,
3625
                 &spr_read_generic, &spr_write_pir,
3626
                 0x00000000);
3627
    /* XXX : not implemented */
3628
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3629
                 SPR_NOACCESS, SPR_NOACCESS,
3630
                 &spr_read_generic, &spr_write_generic,
3631
                 0x00000000);
3632
    /* XXX : not implemented */
3633
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3634
                 SPR_NOACCESS, SPR_NOACCESS,
3635
                 &spr_read_generic, &spr_write_generic,
3636
                 0x00000000);
3637
    /* XXX : not implemented */
3638
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3639
                 SPR_NOACCESS, SPR_NOACCESS,
3640
                 &spr_read_generic, &spr_write_generic,
3641
                 0x00000000);
3642
    /* XXX : not implemented */
3643
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3644
                 SPR_NOACCESS, SPR_NOACCESS,
3645
                 &spr_read_generic, &spr_write_generic,
3646
                 0x00000000);
3647
    /* Memory management */
3648
#if !defined(CONFIG_USER_ONLY)
3649
    env->nb_tlb = 64;
3650
    env->nb_ways = 1;
3651
    env->id_tlbs = 0;
3652
    env->tlb_type = TLB_EMB;
3653
#endif
3654
    init_excp_BookE(env);
3655
    env->dcache_line_size = 32;
3656
    env->icache_line_size = 32;
3657
    /* XXX: TODO: allocate internal IRQ controller */
3658

    
3659
    SET_FIT_PERIOD(12, 16, 20, 24);
3660
    SET_WDT_PERIOD(20, 24, 28, 32);
3661
}
3662

    
3663
POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3664
{
3665
    DeviceClass *dc = DEVICE_CLASS(oc);
3666
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3667

    
3668
    dc->desc = "PowerPC 440x4";
3669
    pcc->init_proc = init_proc_440x4;
3670
    pcc->check_pow = check_pow_nocheck;
3671
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3672
                       PPC_DCR | PPC_WRTEE |
3673
                       PPC_CACHE | PPC_CACHE_ICBI |
3674
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3675
                       PPC_MEM_TLBSYNC | PPC_MFTB |
3676
                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3677
                       PPC_440_SPEC;
3678
    pcc->msr_mask = 0x000000000006FF30ULL;
3679
    pcc->mmu_model = POWERPC_MMU_BOOKE;
3680
    pcc->excp_model = POWERPC_EXCP_BOOKE;
3681
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3682
    pcc->bfd_mach = bfd_mach_ppc_403;
3683
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3684
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3685
}
3686

    
3687
static void init_proc_440x5 (CPUPPCState *env)
3688
{
3689
    /* Time base */
3690
    gen_tbl(env);
3691
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3692
    gen_spr_440(env);
3693
    gen_spr_usprgh(env);
3694
    /* Processor identification */
3695
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3696
                 SPR_NOACCESS, SPR_NOACCESS,
3697
                 &spr_read_generic, &spr_write_pir,
3698
                 0x00000000);
3699
    /* XXX : not implemented */
3700
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3701
                 SPR_NOACCESS, SPR_NOACCESS,
3702
                 &spr_read_generic, &spr_write_generic,
3703
                 0x00000000);
3704
    /* XXX : not implemented */
3705
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3706
                 SPR_NOACCESS, SPR_NOACCESS,
3707
                 &spr_read_generic, &spr_write_generic,
3708
                 0x00000000);
3709
    /* XXX : not implemented */
3710
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3711
                 SPR_NOACCESS, SPR_NOACCESS,
3712
                 &spr_read_generic, &spr_write_generic,
3713
                 0x00000000);
3714
    /* XXX : not implemented */
3715
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3716
                 SPR_NOACCESS, SPR_NOACCESS,
3717
                 &spr_read_generic, &spr_write_generic,
3718
                 0x00000000);
3719
    /* XXX : not implemented */
3720
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3721
                 SPR_NOACCESS, SPR_NOACCESS,
3722
                 &spr_read_generic, &spr_write_generic,
3723
                 0x00000000);
3724
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3725
                 SPR_NOACCESS, SPR_NOACCESS,
3726
                 &spr_read_generic, &spr_write_generic,
3727
                 0x00000000);
3728
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3729
                 SPR_NOACCESS, SPR_NOACCESS,
3730
                 &spr_read_generic, &spr_write_generic,
3731
                 0x00000000);
3732
    /* XXX : not implemented */
3733
    spr_register(env, SPR_440_CCR1, "CCR1",
3734
                 SPR_NOACCESS, SPR_NOACCESS,
3735
                 &spr_read_generic, &spr_write_generic,
3736
                 0x00000000);
3737
    /* Memory management */
3738
#if !defined(CONFIG_USER_ONLY)
3739
    env->nb_tlb = 64;
3740
    env->nb_ways = 1;
3741
    env->id_tlbs = 0;
3742
    env->tlb_type = TLB_EMB;
3743
#endif
3744
    init_excp_BookE(env);
3745
    env->dcache_line_size = 32;
3746
    env->icache_line_size = 32;
3747
    ppc40x_irq_init(env);
3748

    
3749
    SET_FIT_PERIOD(12, 16, 20, 24);
3750
    SET_WDT_PERIOD(20, 24, 28, 32);
3751
}
3752

    
3753
POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3754
{
3755
    DeviceClass *dc = DEVICE_CLASS(oc);
3756
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3757

    
3758
    dc->desc = "PowerPC 440x5";
3759
    pcc->init_proc = init_proc_440x5;
3760
    pcc->check_pow = check_pow_nocheck;
3761
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3762
                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3763
                       PPC_CACHE | PPC_CACHE_ICBI |
3764
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3765
                       PPC_MEM_TLBSYNC | PPC_MFTB |
3766
                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3767
                       PPC_440_SPEC;
3768
    pcc->msr_mask = 0x000000000006FF30ULL;
3769
    pcc->mmu_model = POWERPC_MMU_BOOKE;
3770
    pcc->excp_model = POWERPC_EXCP_BOOKE;
3771
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3772
    pcc->bfd_mach = bfd_mach_ppc_403;
3773
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3774
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3775
}
3776

    
3777
static void init_proc_460 (CPUPPCState *env)
3778
{
3779
    /* Time base */
3780
    gen_tbl(env);
3781
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3782
    gen_spr_440(env);
3783
    gen_spr_usprgh(env);
3784
    /* Processor identification */
3785
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3786
                 SPR_NOACCESS, SPR_NOACCESS,
3787
                 &spr_read_generic, &spr_write_pir,
3788
                 0x00000000);
3789
    /* XXX : not implemented */
3790
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3791
                 SPR_NOACCESS, SPR_NOACCESS,
3792
                 &spr_read_generic, &spr_write_generic,
3793
                 0x00000000);
3794
    /* XXX : not implemented */
3795
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3796
                 SPR_NOACCESS, SPR_NOACCESS,
3797
                 &spr_read_generic, &spr_write_generic,
3798
                 0x00000000);
3799
    /* XXX : not implemented */
3800
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3801
                 SPR_NOACCESS, SPR_NOACCESS,
3802
                 &spr_read_generic, &spr_write_generic,
3803
                 0x00000000);
3804
    /* XXX : not implemented */
3805
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3806
                 SPR_NOACCESS, SPR_NOACCESS,
3807
                 &spr_read_generic, &spr_write_generic,
3808
                 0x00000000);
3809
    /* XXX : not implemented */
3810
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3811
                 SPR_NOACCESS, SPR_NOACCESS,
3812
                 &spr_read_generic, &spr_write_generic,
3813
                 0x00000000);
3814
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3815
                 SPR_NOACCESS, SPR_NOACCESS,
3816
                 &spr_read_generic, &spr_write_generic,
3817
                 0x00000000);
3818
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3819
                 SPR_NOACCESS, SPR_NOACCESS,
3820
                 &spr_read_generic, &spr_write_generic,
3821
                 0x00000000);
3822
    /* XXX : not implemented */
3823
    spr_register(env, SPR_440_CCR1, "CCR1",
3824
                 SPR_NOACCESS, SPR_NOACCESS,
3825
                 &spr_read_generic, &spr_write_generic,
3826
                 0x00000000);
3827
    /* XXX : not implemented */
3828
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3829
                 &spr_read_generic, &spr_write_generic,
3830
                 &spr_read_generic, &spr_write_generic,
3831
                 0x00000000);
3832
    /* Memory management */
3833
#if !defined(CONFIG_USER_ONLY)
3834
    env->nb_tlb = 64;
3835
    env->nb_ways = 1;
3836
    env->id_tlbs = 0;
3837
    env->tlb_type = TLB_EMB;
3838
#endif
3839
    init_excp_BookE(env);
3840
    env->dcache_line_size = 32;
3841
    env->icache_line_size = 32;
3842
    /* XXX: TODO: allocate internal IRQ controller */
3843

    
3844
    SET_FIT_PERIOD(12, 16, 20, 24);
3845
    SET_WDT_PERIOD(20, 24, 28, 32);
3846
}
3847

    
3848
POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3849
{
3850
    DeviceClass *dc = DEVICE_CLASS(oc);
3851
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3852

    
3853
    dc->desc = "PowerPC 460 (guessed)";
3854
    pcc->init_proc = init_proc_460;
3855
    pcc->check_pow = check_pow_nocheck;
3856
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3857
                       PPC_DCR | PPC_DCRX  | PPC_DCRUX |
3858
                       PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3859
                       PPC_CACHE | PPC_CACHE_ICBI |
3860
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3861
                       PPC_MEM_TLBSYNC | PPC_TLBIVA |
3862
                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3863
                       PPC_440_SPEC;
3864
    pcc->msr_mask = 0x000000000006FF30ULL;
3865
    pcc->mmu_model = POWERPC_MMU_BOOKE;
3866
    pcc->excp_model = POWERPC_EXCP_BOOKE;
3867
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3868
    pcc->bfd_mach = bfd_mach_ppc_403;
3869
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3870
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3871
}
3872

    
3873
static void init_proc_460F (CPUPPCState *env)
3874
{
3875
    /* Time base */
3876
    gen_tbl(env);
3877
    gen_spr_BookE(env, 0x000000000000FFFFULL);
3878
    gen_spr_440(env);
3879
    gen_spr_usprgh(env);
3880
    /* Processor identification */
3881
    spr_register(env, SPR_BOOKE_PIR, "PIR",
3882
                 SPR_NOACCESS, SPR_NOACCESS,
3883
                 &spr_read_generic, &spr_write_pir,
3884
                 0x00000000);
3885
    /* XXX : not implemented */
3886
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3887
                 SPR_NOACCESS, SPR_NOACCESS,
3888
                 &spr_read_generic, &spr_write_generic,
3889
                 0x00000000);
3890
    /* XXX : not implemented */
3891
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3892
                 SPR_NOACCESS, SPR_NOACCESS,
3893
                 &spr_read_generic, &spr_write_generic,
3894
                 0x00000000);
3895
    /* XXX : not implemented */
3896
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3897
                 SPR_NOACCESS, SPR_NOACCESS,
3898
                 &spr_read_generic, &spr_write_generic,
3899
                 0x00000000);
3900
    /* XXX : not implemented */
3901
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3902
                 SPR_NOACCESS, SPR_NOACCESS,
3903
                 &spr_read_generic, &spr_write_generic,
3904
                 0x00000000);
3905
    /* XXX : not implemented */
3906
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3907
                 SPR_NOACCESS, SPR_NOACCESS,
3908
                 &spr_read_generic, &spr_write_generic,
3909
                 0x00000000);
3910
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3911
                 SPR_NOACCESS, SPR_NOACCESS,
3912
                 &spr_read_generic, &spr_write_generic,
3913
                 0x00000000);
3914
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3915
                 SPR_NOACCESS, SPR_NOACCESS,
3916
                 &spr_read_generic, &spr_write_generic,
3917
                 0x00000000);
3918
    /* XXX : not implemented */
3919
    spr_register(env, SPR_440_CCR1, "CCR1",
3920
                 SPR_NOACCESS, SPR_NOACCESS,
3921
                 &spr_read_generic, &spr_write_generic,
3922
                 0x00000000);
3923
    /* XXX : not implemented */
3924
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3925
                 &spr_read_generic, &spr_write_generic,
3926
                 &spr_read_generic, &spr_write_generic,
3927
                 0x00000000);
3928
    /* Memory management */
3929
#if !defined(CONFIG_USER_ONLY)
3930
    env->nb_tlb = 64;
3931
    env->nb_ways = 1;
3932
    env->id_tlbs = 0;
3933
    env->tlb_type = TLB_EMB;
3934
#endif
3935
    init_excp_BookE(env);
3936
    env->dcache_line_size = 32;
3937
    env->icache_line_size = 32;
3938
    /* XXX: TODO: allocate internal IRQ controller */
3939

    
3940
    SET_FIT_PERIOD(12, 16, 20, 24);
3941
    SET_WDT_PERIOD(20, 24, 28, 32);
3942
}
3943

    
3944
POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3945
{
3946
    DeviceClass *dc = DEVICE_CLASS(oc);
3947
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3948

    
3949
    dc->desc = "PowerPC 460F (guessed)";
3950
    pcc->init_proc = init_proc_460F;
3951
    pcc->check_pow = check_pow_nocheck;
3952
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3953
                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3954
                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3955
                       PPC_FLOAT_STFIWX | PPC_MFTB |
3956
                       PPC_DCR | PPC_DCRX | PPC_DCRUX |
3957
                       PPC_WRTEE | PPC_MFAPIDI |
3958
                       PPC_CACHE | PPC_CACHE_ICBI |
3959
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3960
                       PPC_MEM_TLBSYNC | PPC_TLBIVA |
3961
                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3962
                       PPC_440_SPEC;
3963
    pcc->msr_mask = 0x000000000006FF30ULL;
3964
    pcc->mmu_model = POWERPC_MMU_BOOKE;
3965
    pcc->excp_model = POWERPC_EXCP_BOOKE;
3966
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3967
    pcc->bfd_mach = bfd_mach_ppc_403;
3968
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3969
                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3970
}
3971

    
3972
static void init_proc_MPC5xx (CPUPPCState *env)
3973
{
3974
    /* Time base */
3975
    gen_tbl(env);
3976
    gen_spr_5xx_8xx(env);
3977
    gen_spr_5xx(env);
3978
    init_excp_MPC5xx(env);
3979
    env->dcache_line_size = 32;
3980
    env->icache_line_size = 32;
3981
    /* XXX: TODO: allocate internal IRQ controller */
3982
}
3983

    
3984
POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3985
{
3986
    DeviceClass *dc = DEVICE_CLASS(oc);
3987
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3988

    
3989
    dc->desc = "Freescale 5xx cores (aka RCPU)";
3990
    pcc->init_proc = init_proc_MPC5xx;
3991
    pcc->check_pow = check_pow_none;
3992
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3993
                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
3994
                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
3995
                       PPC_MFTB;
3996
    pcc->msr_mask = 0x000000000001FF43ULL;
3997
    pcc->mmu_model = POWERPC_MMU_REAL;
3998
    pcc->excp_model = POWERPC_EXCP_603;
3999
    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4000
    pcc->bfd_mach = bfd_mach_ppc_505;
4001
    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4002
                 POWERPC_FLAG_BUS_CLK;
4003
}
4004

    
4005
static void init_proc_MPC8xx (CPUPPCState *env)
4006
{
4007
    /* Time base */
4008
    gen_tbl(env);
4009
    gen_spr_5xx_8xx(env);
4010
    gen_spr_8xx(env);
4011
    init_excp_MPC8xx(env);
4012
    env->dcache_line_size = 32;
4013
    env->icache_line_size = 32;
4014
    /* XXX: TODO: allocate internal IRQ controller */
4015
}
4016

    
4017
POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4018
{
4019
    DeviceClass *dc = DEVICE_CLASS(oc);
4020
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4021

    
4022
    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4023
    pcc->init_proc = init_proc_MPC8xx;
4024
    pcc->check_pow = check_pow_none;
4025
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
4026
                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4027
                       PPC_CACHE_ICBI | PPC_MFTB;
4028
    pcc->msr_mask = 0x000000000001F673ULL;
4029
    pcc->mmu_model = POWERPC_MMU_MPC8xx;
4030
    pcc->excp_model = POWERPC_EXCP_603;
4031
    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4032
    pcc->bfd_mach = bfd_mach_ppc_860;
4033
    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4034
                 POWERPC_FLAG_BUS_CLK;
4035
}
4036

    
4037
/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
4038

    
4039
static void init_proc_G2 (CPUPPCState *env)
4040
{
4041
    gen_spr_ne_601(env);
4042
    gen_spr_G2_755(env);
4043
    gen_spr_G2(env);
4044
    /* Time base */
4045
    gen_tbl(env);
4046
    /* External access control */
4047
    /* XXX : not implemented */
4048
    spr_register(env, SPR_EAR, "EAR",
4049
                 SPR_NOACCESS, SPR_NOACCESS,
4050
                 &spr_read_generic, &spr_write_generic,
4051
                 0x00000000);
4052
    /* Hardware implementation register */
4053
    /* XXX : not implemented */
4054
    spr_register(env, SPR_HID0, "HID0",
4055
                 SPR_NOACCESS, SPR_NOACCESS,
4056
                 &spr_read_generic, &spr_write_generic,
4057
                 0x00000000);
4058
    /* XXX : not implemented */
4059
    spr_register(env, SPR_HID1, "HID1",
4060
                 SPR_NOACCESS, SPR_NOACCESS,
4061
                 &spr_read_generic, &spr_write_generic,
4062
                 0x00000000);
4063
    /* XXX : not implemented */
4064
    spr_register(env, SPR_HID2, "HID2",
4065
                 SPR_NOACCESS, SPR_NOACCESS,
4066
                 &spr_read_generic, &spr_write_generic,
4067
                 0x00000000);
4068
    /* Memory management */
4069
    gen_low_BATs(env);
4070
    gen_high_BATs(env);
4071
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4072
    init_excp_G2(env);
4073
    env->dcache_line_size = 32;
4074
    env->icache_line_size = 32;
4075
    /* Allocate hardware IRQ controller */
4076
    ppc6xx_irq_init(env);
4077
}
4078

    
4079
POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4080
{
4081
    DeviceClass *dc = DEVICE_CLASS(oc);
4082
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4083

    
4084
    dc->desc = "PowerPC G2";
4085
    pcc->init_proc = init_proc_G2;
4086
    pcc->check_pow = check_pow_hid0;
4087
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4088
                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4089
                       PPC_FLOAT_STFIWX |
4090
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4091
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4092
                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4093
                       PPC_SEGMENT | PPC_EXTERN;
4094
    pcc->msr_mask = 0x000000000006FFF2ULL;
4095
    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4096
    pcc->excp_model = POWERPC_EXCP_G2;
4097
    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4098
    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4099
    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4100
                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4101
}
4102

    
4103
static void init_proc_G2LE (CPUPPCState *env)
4104
{
4105
    gen_spr_ne_601(env);
4106
    gen_spr_G2_755(env);
4107
    gen_spr_G2(env);
4108
    /* Time base */
4109
    gen_tbl(env);
4110
    /* External access control */
4111
    /* XXX : not implemented */
4112
    spr_register(env, SPR_EAR, "EAR",
4113
                 SPR_NOACCESS, SPR_NOACCESS,
4114
                 &spr_read_generic, &spr_write_generic,
4115
                 0x00000000);
4116
    /* Hardware implementation register */
4117
    /* XXX : not implemented */
4118
    spr_register(env, SPR_HID0, "HID0",
4119
                 SPR_NOACCESS, SPR_NOACCESS,
4120
                 &spr_read_generic, &spr_write_generic,
4121
                 0x00000000);
4122
    /* XXX : not implemented */
4123
    spr_register(env, SPR_HID1, "HID1",
4124
                 SPR_NOACCESS, SPR_NOACCESS,
4125
                 &spr_read_generic, &spr_write_generic,
4126
                 0x00000000);
4127
    /* XXX : not implemented */
4128
    spr_register(env, SPR_HID2, "HID2",
4129
                 SPR_NOACCESS, SPR_NOACCESS,
4130
                 &spr_read_generic, &spr_write_generic,
4131
                 0x00000000);
4132
    /* Breakpoints */
4133
    /* XXX : not implemented */
4134
    spr_register(env, SPR_DABR, "DABR",
4135
                 SPR_NOACCESS, SPR_NOACCESS,
4136
                 &spr_read_generic, &spr_write_generic,
4137
                 0x00000000);
4138
    /* XXX : not implemented */
4139
    spr_register(env, SPR_DABR2, "DABR2",
4140
                 SPR_NOACCESS, SPR_NOACCESS,
4141
                 &spr_read_generic, &spr_write_generic,
4142
                 0x00000000);
4143
    /* XXX : not implemented */
4144
    spr_register(env, SPR_IABR2, "IABR2",
4145
                 SPR_NOACCESS, SPR_NOACCESS,
4146
                 &spr_read_generic, &spr_write_generic,
4147
                 0x00000000);
4148
    /* XXX : not implemented */
4149
    spr_register(env, SPR_IBCR, "IBCR",
4150
                 SPR_NOACCESS, SPR_NOACCESS,
4151
                 &spr_read_generic, &spr_write_generic,
4152
                 0x00000000);
4153
    /* XXX : not implemented */
4154
    spr_register(env, SPR_DBCR, "DBCR",
4155
                 SPR_NOACCESS, SPR_NOACCESS,
4156
                 &spr_read_generic, &spr_write_generic,
4157
                 0x00000000);
4158

    
4159
    /* Memory management */
4160
    gen_low_BATs(env);
4161
    gen_high_BATs(env);
4162
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4163
    init_excp_G2(env);
4164
    env->dcache_line_size = 32;
4165
    env->icache_line_size = 32;
4166
    /* Allocate hardware IRQ controller */
4167
    ppc6xx_irq_init(env);
4168
}
4169

    
4170
POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4171
{
4172
    DeviceClass *dc = DEVICE_CLASS(oc);
4173
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4174

    
4175
    dc->desc = "PowerPC G2LE";
4176
    pcc->init_proc = init_proc_G2LE;
4177
    pcc->check_pow = check_pow_hid0;
4178
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4179
                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4180
                       PPC_FLOAT_STFIWX |
4181
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4182
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4183
                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4184
                       PPC_SEGMENT | PPC_EXTERN;
4185
    pcc->msr_mask = 0x000000000007FFF3ULL;
4186
    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4187
    pcc->excp_model = POWERPC_EXCP_G2;
4188
    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4189
    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4190
    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4191
                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4192
}
4193

    
4194
static void init_proc_e200 (CPUPPCState *env)
4195
{
4196
    /* Time base */
4197
    gen_tbl(env);
4198
    gen_spr_BookE(env, 0x000000070000FFFFULL);
4199
    /* XXX : not implemented */
4200
    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4201
                 &spr_read_spefscr, &spr_write_spefscr,
4202
                 &spr_read_spefscr, &spr_write_spefscr,
4203
                 0x00000000);
4204
    /* Memory management */
4205
    gen_spr_BookE206(env, 0x0000005D, NULL);
4206
    /* XXX : not implemented */
4207
    spr_register(env, SPR_HID0, "HID0",
4208
                 SPR_NOACCESS, SPR_NOACCESS,
4209
                 &spr_read_generic, &spr_write_generic,
4210
                 0x00000000);
4211
    /* XXX : not implemented */
4212
    spr_register(env, SPR_HID1, "HID1",
4213
                 SPR_NOACCESS, SPR_NOACCESS,
4214
                 &spr_read_generic, &spr_write_generic,
4215
                 0x00000000);
4216
    /* XXX : not implemented */
4217
    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4218
                 SPR_NOACCESS, SPR_NOACCESS,
4219
                 &spr_read_generic, &spr_write_generic,
4220
                 0x00000000);
4221
    /* XXX : not implemented */
4222
    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4223
                 SPR_NOACCESS, SPR_NOACCESS,
4224
                 &spr_read_generic, &spr_write_generic,
4225
                 0x00000000);
4226
    /* XXX : not implemented */
4227
    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4228
                 SPR_NOACCESS, SPR_NOACCESS,
4229
                 &spr_read_generic, &spr_write_generic,
4230
                 0x00000000);
4231
    /* XXX : not implemented */
4232
    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4233
                 SPR_NOACCESS, SPR_NOACCESS,
4234
                 &spr_read_generic, &spr_write_generic,
4235
                 0x00000000);
4236
    /* XXX : not implemented */
4237
    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4238
                 SPR_NOACCESS, SPR_NOACCESS,
4239
                 &spr_read_generic, &spr_write_generic,
4240
                 0x00000000);
4241
    /* XXX : not implemented */
4242
    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4243
                 SPR_NOACCESS, SPR_NOACCESS,
4244
                 &spr_read_generic, &spr_write_generic,
4245
                 0x00000000);
4246
    /* XXX : not implemented */
4247
    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4248
                 SPR_NOACCESS, SPR_NOACCESS,
4249
                 &spr_read_generic, &spr_write_generic,
4250
                 0x00000000);
4251
    /* XXX : not implemented */
4252
    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4253
                 SPR_NOACCESS, SPR_NOACCESS,
4254
                 &spr_read_generic, &spr_write_generic,
4255
                 0x00000000);
4256
    /* XXX : not implemented */
4257
    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4258
                 SPR_NOACCESS, SPR_NOACCESS,
4259
                 &spr_read_generic, &spr_write_generic,
4260
                 0x00000000);
4261
    /* XXX : not implemented */
4262
    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4263
                 SPR_NOACCESS, SPR_NOACCESS,
4264
                 &spr_read_generic, &spr_write_generic,
4265
                 0x00000000);
4266
    /* XXX : not implemented */
4267
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4268
                 SPR_NOACCESS, SPR_NOACCESS,
4269
                 &spr_read_generic, &spr_write_generic,
4270
                 0x00000000);
4271
    /* XXX : not implemented */
4272
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4273
                 SPR_NOACCESS, SPR_NOACCESS,
4274
                 &spr_read_generic, &spr_write_generic,
4275
                 0x00000000);
4276
    /* XXX : not implemented */
4277
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4278
                 SPR_NOACCESS, SPR_NOACCESS,
4279
                 &spr_read_generic, &spr_write_generic,
4280
                 0x00000000); /* TOFIX */
4281
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4282
                 SPR_NOACCESS, SPR_NOACCESS,
4283
                 &spr_read_generic, &spr_write_generic,
4284
                 0x00000000);
4285
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4286
                 SPR_NOACCESS, SPR_NOACCESS,
4287
                 &spr_read_generic, &spr_write_generic,
4288
                 0x00000000);
4289
#if !defined(CONFIG_USER_ONLY)
4290
    env->nb_tlb = 64;
4291
    env->nb_ways = 1;
4292
    env->id_tlbs = 0;
4293
    env->tlb_type = TLB_EMB;
4294
#endif
4295
    init_excp_e200(env, 0xFFFF0000UL);
4296
    env->dcache_line_size = 32;
4297
    env->icache_line_size = 32;
4298
    /* XXX: TODO: allocate internal IRQ controller */
4299
}
4300

    
4301
POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4302
{
4303
    DeviceClass *dc = DEVICE_CLASS(oc);
4304
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4305

    
4306
    dc->desc = "e200 core";
4307
    pcc->init_proc = init_proc_e200;
4308
    pcc->check_pow = check_pow_hid0;
4309
    /* XXX: unimplemented instructions:
4310
     * dcblc
4311
     * dcbtlst
4312
     * dcbtstls
4313
     * icblc
4314
     * icbtls
4315
     * tlbivax
4316
     * all SPE multiply-accumulate instructions
4317
     */
4318
    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4319
                       PPC_SPE | PPC_SPE_SINGLE |
4320
                       PPC_WRTEE | PPC_RFDI |
4321
                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4322
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4323
                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4324
                       PPC_BOOKE;
4325
    pcc->msr_mask = 0x000000000606FF30ULL;
4326
    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4327
    pcc->excp_model = POWERPC_EXCP_BOOKE;
4328
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4329
    pcc->bfd_mach = bfd_mach_ppc_860;
4330
    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4331
                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4332
                 POWERPC_FLAG_BUS_CLK;
4333
}
4334

    
4335
static void init_proc_e300 (CPUPPCState *env)
4336
{
4337
    gen_spr_ne_601(env);
4338
    gen_spr_603(env);
4339
    /* Time base */
4340
    gen_tbl(env);
4341
    /* hardware implementation registers */
4342
    /* XXX : not implemented */
4343
    spr_register(env, SPR_HID0, "HID0",
4344
                 SPR_NOACCESS, SPR_NOACCESS,
4345
                 &spr_read_generic, &spr_write_generic,
4346
                 0x00000000);
4347
    /* XXX : not implemented */
4348
    spr_register(env, SPR_HID1, "HID1",
4349
                 SPR_NOACCESS, SPR_NOACCESS,
4350
                 &spr_read_generic, &spr_write_generic,
4351
                 0x00000000);
4352
    /* XXX : not implemented */
4353
    spr_register(env, SPR_HID2, "HID2",
4354
                 SPR_NOACCESS, SPR_NOACCESS,
4355
                 &spr_read_generic, &spr_write_generic,
4356
                 0x00000000);
4357
    /* Memory management */
4358
    gen_low_BATs(env);
4359
    gen_high_BATs(env);
4360
    gen_6xx_7xx_soft_tlb(env, 64, 2);
4361
    init_excp_603(env);
4362
    env->dcache_line_size = 32;
4363
    env->icache_line_size = 32;
4364
    /* Allocate hardware IRQ controller */
4365
    ppc6xx_irq_init(env);
4366
}
4367

    
4368
POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4369
{
4370
    DeviceClass *dc = DEVICE_CLASS(oc);
4371
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4372

    
4373
    dc->desc = "e300 core";
4374
    pcc->init_proc = init_proc_e300;
4375
    pcc->check_pow = check_pow_hid0;
4376
    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4377
                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4378
                       PPC_FLOAT_STFIWX |
4379
                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4380
                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4381
                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4382
                       PPC_SEGMENT | PPC_EXTERN;
4383
    pcc->msr_mask = 0x000000000007FFF3ULL;
4384
    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4385
    pcc->excp_model = POWERPC_EXCP_603;
4386
    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4387
    pcc->bfd_mach = bfd_mach_ppc_603;
4388
    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4389
                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4390
}
4391

    
4392
#if !defined(CONFIG_USER_ONLY)
4393
static void spr_write_mas73(void *opaque, int sprn, int gprn)
4394
{
4395
    TCGv val = tcg_temp_new();
4396
    tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4397
    gen_store_spr(SPR_BOOKE_MAS3, val);
4398
    tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4399
    gen_store_spr(SPR_BOOKE_MAS7, val);
4400
    tcg_temp_free(val);
4401
}
4402

    
4403
static void spr_read_mas73(void *opaque, int gprn, int sprn)
4404
{
4405
    TCGv mas7 = tcg_temp_new();
4406
    TCGv mas3 = tcg_temp_new();
4407
    gen_load_spr(mas7, SPR_BOOKE_MAS7);
4408
    tcg_gen_shli_tl(mas7, mas7, 32);
4409
    gen_load_spr(mas3, SPR_BOOKE_MAS3);
4410
    tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4411
    tcg_temp_free(mas3);
4412
    tcg_temp_free(mas7);
4413
}
4414

    
4415
#endif
4416

    
4417
enum fsl_e500_version {
4418
    fsl_e500v1,
4419
    fsl_e500v2,
4420
    fsl_e500mc,
4421
    fsl_e5500,
4422
};
4423

    
4424
static void init_proc_e500 (CPUPPCState *env, int version)
4425
{
4426
    uint32_t tlbncfg[2];
4427
    uint64_t ivor_mask;
4428
    uint64_t ivpr_mask = 0xFFFF0000ULL;
4429
    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4430
                    | 0x0020; /* 32 kb */
4431
#if !defined(CONFIG_USER_ONLY)
4432
    int i;
4433
#endif
4434

    
4435
    /* Time base */
4436
    gen_tbl(env);
4437
    /*
4438
     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4439
     *     complain when accessing them.
4440
     * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4441
     */
4442
    switch (version) {
4443
        case fsl_e500v1:
4444
        case fsl_e500v2:
4445
        default:
4446
            ivor_mask = 0x0000000F0000FFFFULL;
4447
            break;
4448
        case fsl_e500mc:
4449
        case fsl_e5500:
4450
            ivor_mask = 0x000003FE0000FFFFULL;
4451
            break;
4452
    }
4453
    gen_spr_BookE(env, ivor_mask);
4454
    /* Processor identification */
4455
    spr_register(env, SPR_BOOKE_PIR, "PIR",
4456
                 SPR_NOACCESS, SPR_NOACCESS,
4457
                 &spr_read_generic, &spr_write_pir,
4458
                 0x00000000);
4459
    /* XXX : not implemented */
4460
    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4461
                 &spr_read_spefscr, &spr_write_spefscr,
4462
                 &spr_read_spefscr, &spr_write_spefscr,
4463
                 0x00000000);
4464
#if !defined(CONFIG_USER_ONLY)
4465
    /* Memory management */
4466
    env->nb_pids = 3;
4467
    env->nb_ways = 2;
4468
    env->id_tlbs = 0;
4469
    switch (version) {
4470
    case fsl_e500v1:
4471
        tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4472
        tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4473
        break;
4474
    case fsl_e500v2:
4475
        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4476
        tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4477
        break;
4478
    case fsl_e500mc:
4479
    case fsl_e5500:
4480
        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4481
        tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4482
        break;
4483
    default:
4484
        cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4485
    }
4486
#endif
4487
    /* Cache sizes */
4488
    switch (version) {
4489
    case fsl_e500v1:
4490
    case fsl_e500v2:
4491
        env->dcache_line_size = 32;
4492
        env->icache_line_size = 32;
4493
        break;
4494
    case fsl_e500mc:
4495
    case fsl_e5500:
4496
        env->dcache_line_size = 64;
4497
        env->icache_line_size = 64;
4498
        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4499
        break;
4500
    default:
4501
        cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4502
    }
4503
    gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4504
    /* XXX : not implemented */
4505
    spr_register(env, SPR_HID0, "HID0",
4506
                 SPR_NOACCESS, SPR_NOACCESS,
4507
                 &spr_read_generic, &spr_write_generic,
4508
                 0x00000000);
4509
    /* XXX : not implemented */
4510
    spr_register(env, SPR_HID1, "HID1",
4511
                 SPR_NOACCESS, SPR_NOACCESS,
4512
                 &spr_read_generic, &spr_write_generic,
4513
                 0x00000000);
4514
    /* XXX : not implemented */
4515
    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4516
                 SPR_NOACCESS, SPR_NOACCESS,
4517
                 &spr_read_generic, &spr_write_generic,
4518
                 0x00000000);
4519
    /* XXX : not implemented */
4520
    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4521
                 SPR_NOACCESS, SPR_NOACCESS,
4522
                 &spr_read_generic, &spr_write_generic,
4523
                 0x00000000);
4524
    /* XXX : not implemented */
4525
    spr_register(env, SPR_Exxx_MCAR, "MCAR",
4526
                 SPR_NOACCESS, SPR_NOACCESS,
4527
                 &spr_read_generic, &spr_write_generic,
4528
                 0x00000000);
4529
    /* XXX : not implemented */
4530
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4531
                 SPR_NOACCESS, SPR_NOACCESS,
4532
                 &spr_read_generic, &spr_write_generic,
4533
                 0x00000000);
4534
    /* XXX : not implemented */
4535
    spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4536
                 SPR_NOACCESS, SPR_NOACCESS,
4537
                 &spr_read_generic, &spr_write_generic,
4538
                 0x00000000);
4539
    /* XXX : not implemented */
4540
    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4541
                 SPR_NOACCESS, SPR_NOACCESS,
4542
                 &spr_read_generic, &spr_write_generic,
4543
                 0x00000000);
4544
    /* XXX : not implemented */
4545
    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4546
                 SPR_NOACCESS, SPR_NOACCESS,
4547
                 &spr_read_generic, &spr_write_generic,
4548
                 l1cfg0);
4549
    /* XXX : not implemented */
4550
    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4551
                 SPR_NOACCESS, SPR_NOACCESS,
4552
                 &spr_read_generic, &spr_write_e500_l1csr0,
4553
                 0x00000000);
4554
    /* XXX : not implemented */
4555
    spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4556
                 SPR_NOACCESS, SPR_NOACCESS,
4557
                 &spr_read_generic, &spr_write_generic,
4558
                 0x00000000);
4559
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4560
                 SPR_NOACCESS, SPR_NOACCESS,
4561
                 &spr_read_generic, &spr_write_generic,
4562
                 0x00000000);
4563
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4564
                 SPR_NOACCESS, SPR_NOACCESS,
4565
                 &spr_read_generic, &spr_write_generic,
4566
                 0x00000000);
4567
    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4568
                 SPR_NOACCESS, SPR_NOACCESS,
4569
                 &spr_read_generic, &spr_write_booke206_mmucsr0,
4570
                 0x00000000);
4571
    spr_register(env, SPR_BOOKE_EPR, "EPR",
4572
                 SPR_NOACCESS, SPR_NOACCESS,
4573
                 &spr_read_generic, SPR_NOACCESS,
4574
                 0x00000000);
4575
    /* XXX better abstract into Emb.xxx features */
4576
    if (version == fsl_e5500) {
4577
        spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4578
                     SPR_NOACCESS, SPR_NOACCESS,
4579
                     &spr_read_generic, &spr_write_generic,
4580
                     0x00000000);
4581
        spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4582
                     SPR_NOACCESS, SPR_NOACCESS,
4583
                     &spr_read_mas73, &spr_write_mas73,
4584
                     0x00000000);
4585
        ivpr_mask = (target_ulong)~0xFFFFULL;
4586
    }
4587

    
4588
#if !defined(CONFIG_USER_ONLY)
4589
    env->nb_tlb = 0;
4590
    env->tlb_type = TLB_MAS;
4591
    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4592
        env->nb_tlb += booke206_tlb_size(env, i);
4593
    }
4594
#endif
4595

    
4596
    init_excp_e200(env, ivpr_mask);
4597
    /* Allocate hardware IRQ controller */
4598
    ppce500_irq_init(env);
4599
}
4600

    
4601
static void init_proc_e500v1(CPUPPCState *env)
4602
{
4603
    init_proc_e500(env, fsl_e500v1);
4604
}
4605

    
4606
POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4607
{
4608
    DeviceClass *dc = DEVICE_CLASS(oc);
4609
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4610

    
4611
    dc->desc = "e500v1 core";
4612
    pcc->init_proc = init_proc_e500v1;
4613
    pcc->check_pow = check_pow_hid0;
4614
    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4615
                       PPC_SPE | PPC_SPE_SINGLE |
4616
                       PPC_WRTEE | PPC_RFDI |
4617
                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4618
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4619
                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4620
    pcc->insns_flags2 = PPC2_BOOKE206;
4621
    pcc->msr_mask = 0x000000000606FF30ULL;
4622
    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4623
    pcc->excp_model = POWERPC_EXCP_BOOKE;
4624
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4625
    pcc->bfd_mach = bfd_mach_ppc_860;
4626
    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4627
                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4628
                 POWERPC_FLAG_BUS_CLK;
4629
}
4630

    
4631
static void init_proc_e500v2(CPUPPCState *env)
4632
{
4633
    init_proc_e500(env, fsl_e500v2);
4634
}
4635

    
4636
POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4637
{
4638
    DeviceClass *dc = DEVICE_CLASS(oc);
4639
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4640

    
4641
    dc->desc = "e500v2 core";
4642
    pcc->init_proc = init_proc_e500v2;
4643
    pcc->check_pow = check_pow_hid0;
4644
    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4645
                       PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4646
                       PPC_WRTEE | PPC_RFDI |
4647
                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4648
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4649
                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4650
    pcc->insns_flags2 = PPC2_BOOKE206;
4651
    pcc->msr_mask = 0x000000000606FF30ULL;
4652
    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4653
    pcc->excp_model = POWERPC_EXCP_BOOKE;
4654
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4655
    pcc->bfd_mach = bfd_mach_ppc_860;
4656
    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4657
                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4658
                 POWERPC_FLAG_BUS_CLK;
4659
}
4660

    
4661
static void init_proc_e500mc(CPUPPCState *env)
4662
{
4663
    init_proc_e500(env, fsl_e500mc);
4664
}
4665

    
4666
POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4667
{
4668
    DeviceClass *dc = DEVICE_CLASS(oc);
4669
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4670

    
4671
    dc->desc = "e500mc core";
4672
    pcc->init_proc = init_proc_e500mc;
4673
    pcc->check_pow = check_pow_none;
4674
    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4675
                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4676
                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4677
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4678
                       PPC_FLOAT | PPC_FLOAT_FRES |
4679
                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4680
                       PPC_FLOAT_STFIWX | PPC_WAIT |
4681
                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4682
    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4683
    pcc->msr_mask = 0x000000001402FB36ULL;
4684
    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4685
    pcc->excp_model = POWERPC_EXCP_BOOKE;
4686
    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4687
    /* FIXME: figure out the correct flag for e500mc */
4688
    pcc->bfd_mach = bfd_mach_ppc_e500;
4689
    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4690
                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4691
}
4692

    
4693
#ifdef TARGET_PPC64
4694
static void init_proc_e5500(CPUPPCState *env)
4695
{
4696
    init_proc_e500(env, fsl_e5500);
4697
}
4698

    
4699
POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4700
{
4701
    DeviceClass *dc = DEVICE_CLASS(oc);
4702
    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4703

    
4704
    dc->desc = "e5500 core";
4705
    pcc->init_proc = init_proc_e5500;
4706
    pcc->check_pow = check_pow_none;
4707
    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4708
                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4709
                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4710
                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4711
                       PPC_FLOAT | PPC_FLOAT_FRES |
4712
                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4713
                       PPC_FLOAT_STFIWX | PPC_WAIT |
4714
                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4715
                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4716
    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4717
    pcc->msr_mask = 0x000000009402FB36ULL;
4718