root / target-ppc / helper.c @ 5b52b991
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation helpers for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | fdabc366 | bellard | #include <stdarg.h> |
21 | fdabc366 | bellard | #include <stdlib.h> |
22 | fdabc366 | bellard | #include <stdio.h> |
23 | fdabc366 | bellard | #include <string.h> |
24 | fdabc366 | bellard | #include <inttypes.h> |
25 | fdabc366 | bellard | #include <signal.h> |
26 | fdabc366 | bellard | #include <assert.h> |
27 | fdabc366 | bellard | |
28 | fdabc366 | bellard | #include "cpu.h" |
29 | fdabc366 | bellard | #include "exec-all.h" |
30 | 0411a972 | j_mayer | #include "helper_regs.h" |
31 | 9a64fbe4 | bellard | |
32 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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33 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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34 | 76a66253 | j_mayer | //#define DEBUG_SOFTWARE_TLB
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35 | 0411a972 | j_mayer | //#define DUMP_PAGE_TABLES
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36 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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37 | fdabc366 | bellard | //#define FLUSH_ALL_TLBS
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38 | 9a64fbe4 | bellard | |
39 | 9a64fbe4 | bellard | /*****************************************************************************/
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40 | 3fc6c082 | bellard | /* PowerPC MMU emulation */
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41 | a541f297 | bellard | |
42 | d9bce9d9 | j_mayer | #if defined(CONFIG_USER_ONLY)
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43 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
44 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
45 | 24741ef3 | bellard | { |
46 | 24741ef3 | bellard | int exception, error_code;
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47 | d9bce9d9 | j_mayer | |
48 | 24741ef3 | bellard | if (rw == 2) { |
49 | e1833e1f | j_mayer | exception = POWERPC_EXCP_ISI; |
50 | 8f793433 | j_mayer | error_code = 0x40000000;
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51 | 24741ef3 | bellard | } else {
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52 | e1833e1f | j_mayer | exception = POWERPC_EXCP_DSI; |
53 | 8f793433 | j_mayer | error_code = 0x40000000;
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54 | 24741ef3 | bellard | if (rw)
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55 | 24741ef3 | bellard | error_code |= 0x02000000;
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56 | 24741ef3 | bellard | env->spr[SPR_DAR] = address; |
57 | 24741ef3 | bellard | env->spr[SPR_DSISR] = error_code; |
58 | 24741ef3 | bellard | } |
59 | 24741ef3 | bellard | env->exception_index = exception; |
60 | 24741ef3 | bellard | env->error_code = error_code; |
61 | 76a66253 | j_mayer | |
62 | 24741ef3 | bellard | return 1; |
63 | 24741ef3 | bellard | } |
64 | 76a66253 | j_mayer | |
65 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
66 | 24741ef3 | bellard | { |
67 | 24741ef3 | bellard | return addr;
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68 | 24741ef3 | bellard | } |
69 | 36081602 | j_mayer | |
70 | 24741ef3 | bellard | #else
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71 | 76a66253 | j_mayer | /* Common routines used by software and hardware TLBs emulation */
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72 | b068d6a7 | j_mayer | static always_inline int pte_is_valid (target_ulong pte0) |
73 | 76a66253 | j_mayer | { |
74 | 76a66253 | j_mayer | return pte0 & 0x80000000 ? 1 : 0; |
75 | 76a66253 | j_mayer | } |
76 | 76a66253 | j_mayer | |
77 | b068d6a7 | j_mayer | static always_inline void pte_invalidate (target_ulong *pte0) |
78 | 76a66253 | j_mayer | { |
79 | 76a66253 | j_mayer | *pte0 &= ~0x80000000;
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80 | 76a66253 | j_mayer | } |
81 | 76a66253 | j_mayer | |
82 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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83 | b068d6a7 | j_mayer | static always_inline int pte64_is_valid (target_ulong pte0) |
84 | caa4039c | j_mayer | { |
85 | caa4039c | j_mayer | return pte0 & 0x0000000000000001ULL ? 1 : 0; |
86 | caa4039c | j_mayer | } |
87 | caa4039c | j_mayer | |
88 | b068d6a7 | j_mayer | static always_inline void pte64_invalidate (target_ulong *pte0) |
89 | caa4039c | j_mayer | { |
90 | caa4039c | j_mayer | *pte0 &= ~0x0000000000000001ULL;
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91 | caa4039c | j_mayer | } |
92 | caa4039c | j_mayer | #endif
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93 | caa4039c | j_mayer | |
94 | 76a66253 | j_mayer | #define PTE_PTEM_MASK 0x7FFFFFBF |
95 | 76a66253 | j_mayer | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
96 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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97 | caa4039c | j_mayer | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
98 | caa4039c | j_mayer | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
99 | caa4039c | j_mayer | #endif
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100 | 76a66253 | j_mayer | |
101 | b227a8e9 | j_mayer | static always_inline int pp_check (int key, int pp, int nx) |
102 | b227a8e9 | j_mayer | { |
103 | b227a8e9 | j_mayer | int access;
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104 | b227a8e9 | j_mayer | |
105 | b227a8e9 | j_mayer | /* Compute access rights */
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106 | b227a8e9 | j_mayer | /* When pp is 3/7, the result is undefined. Set it to noaccess */
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107 | b227a8e9 | j_mayer | access = 0;
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108 | b227a8e9 | j_mayer | if (key == 0) { |
109 | b227a8e9 | j_mayer | switch (pp) {
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110 | b227a8e9 | j_mayer | case 0x0: |
111 | b227a8e9 | j_mayer | case 0x1: |
112 | b227a8e9 | j_mayer | case 0x2: |
113 | b227a8e9 | j_mayer | access |= PAGE_WRITE; |
114 | b227a8e9 | j_mayer | /* No break here */
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115 | b227a8e9 | j_mayer | case 0x3: |
116 | b227a8e9 | j_mayer | case 0x6: |
117 | b227a8e9 | j_mayer | access |= PAGE_READ; |
118 | b227a8e9 | j_mayer | break;
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119 | b227a8e9 | j_mayer | } |
120 | b227a8e9 | j_mayer | } else {
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121 | b227a8e9 | j_mayer | switch (pp) {
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122 | b227a8e9 | j_mayer | case 0x0: |
123 | b227a8e9 | j_mayer | case 0x6: |
124 | b227a8e9 | j_mayer | access = 0;
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125 | b227a8e9 | j_mayer | break;
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126 | b227a8e9 | j_mayer | case 0x1: |
127 | b227a8e9 | j_mayer | case 0x3: |
128 | b227a8e9 | j_mayer | access = PAGE_READ; |
129 | b227a8e9 | j_mayer | break;
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130 | b227a8e9 | j_mayer | case 0x2: |
131 | b227a8e9 | j_mayer | access = PAGE_READ | PAGE_WRITE; |
132 | b227a8e9 | j_mayer | break;
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133 | b227a8e9 | j_mayer | } |
134 | b227a8e9 | j_mayer | } |
135 | b227a8e9 | j_mayer | if (nx == 0) |
136 | b227a8e9 | j_mayer | access |= PAGE_EXEC; |
137 | b227a8e9 | j_mayer | |
138 | b227a8e9 | j_mayer | return access;
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139 | b227a8e9 | j_mayer | } |
140 | b227a8e9 | j_mayer | |
141 | b227a8e9 | j_mayer | static always_inline int check_prot (int prot, int rw, int access_type) |
142 | b227a8e9 | j_mayer | { |
143 | b227a8e9 | j_mayer | int ret;
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144 | b227a8e9 | j_mayer | |
145 | b227a8e9 | j_mayer | if (access_type == ACCESS_CODE) {
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146 | b227a8e9 | j_mayer | if (prot & PAGE_EXEC)
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147 | b227a8e9 | j_mayer | ret = 0;
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148 | b227a8e9 | j_mayer | else
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149 | b227a8e9 | j_mayer | ret = -2;
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150 | b227a8e9 | j_mayer | } else if (rw) { |
151 | b227a8e9 | j_mayer | if (prot & PAGE_WRITE)
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152 | b227a8e9 | j_mayer | ret = 0;
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153 | b227a8e9 | j_mayer | else
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154 | b227a8e9 | j_mayer | ret = -2;
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155 | b227a8e9 | j_mayer | } else {
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156 | b227a8e9 | j_mayer | if (prot & PAGE_READ)
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157 | b227a8e9 | j_mayer | ret = 0;
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158 | b227a8e9 | j_mayer | else
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159 | b227a8e9 | j_mayer | ret = -2;
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160 | b227a8e9 | j_mayer | } |
161 | b227a8e9 | j_mayer | |
162 | b227a8e9 | j_mayer | return ret;
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163 | b227a8e9 | j_mayer | } |
164 | b227a8e9 | j_mayer | |
165 | b068d6a7 | j_mayer | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
166 | b068d6a7 | j_mayer | target_ulong pte0, target_ulong pte1, |
167 | b227a8e9 | j_mayer | int h, int rw, int type) |
168 | 76a66253 | j_mayer | { |
169 | caa4039c | j_mayer | target_ulong ptem, mmask; |
170 | b227a8e9 | j_mayer | int access, ret, pteh, ptev, pp;
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171 | 76a66253 | j_mayer | |
172 | 76a66253 | j_mayer | access = 0;
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173 | 76a66253 | j_mayer | ret = -1;
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174 | 76a66253 | j_mayer | /* Check validity and table match */
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175 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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176 | caa4039c | j_mayer | if (is_64b) {
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177 | caa4039c | j_mayer | ptev = pte64_is_valid(pte0); |
178 | caa4039c | j_mayer | pteh = (pte0 >> 1) & 1; |
179 | caa4039c | j_mayer | } else
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180 | caa4039c | j_mayer | #endif
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181 | caa4039c | j_mayer | { |
182 | caa4039c | j_mayer | ptev = pte_is_valid(pte0); |
183 | caa4039c | j_mayer | pteh = (pte0 >> 6) & 1; |
184 | caa4039c | j_mayer | } |
185 | caa4039c | j_mayer | if (ptev && h == pteh) {
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186 | 76a66253 | j_mayer | /* Check vsid & api */
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187 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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188 | caa4039c | j_mayer | if (is_64b) {
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189 | caa4039c | j_mayer | ptem = pte0 & PTE64_PTEM_MASK; |
190 | caa4039c | j_mayer | mmask = PTE64_CHECK_MASK; |
191 | b227a8e9 | j_mayer | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
192 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */ |
193 | b227a8e9 | j_mayer | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
194 | caa4039c | j_mayer | } else
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195 | caa4039c | j_mayer | #endif
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196 | caa4039c | j_mayer | { |
197 | caa4039c | j_mayer | ptem = pte0 & PTE_PTEM_MASK; |
198 | caa4039c | j_mayer | mmask = PTE_CHECK_MASK; |
199 | b227a8e9 | j_mayer | pp = pte1 & 0x00000003;
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200 | caa4039c | j_mayer | } |
201 | caa4039c | j_mayer | if (ptem == ctx->ptem) {
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202 | 76a66253 | j_mayer | if (ctx->raddr != (target_ulong)-1) { |
203 | 76a66253 | j_mayer | /* all matches should have equal RPN, WIMG & PP */
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204 | caa4039c | j_mayer | if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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205 | caa4039c | j_mayer | if (loglevel != 0) |
206 | 76a66253 | j_mayer | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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207 | 76a66253 | j_mayer | return -3; |
208 | 76a66253 | j_mayer | } |
209 | 76a66253 | j_mayer | } |
210 | 76a66253 | j_mayer | /* Compute access rights */
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211 | b227a8e9 | j_mayer | access = pp_check(ctx->key, pp, ctx->nx); |
212 | 76a66253 | j_mayer | /* Keep the matching PTE informations */
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213 | 76a66253 | j_mayer | ctx->raddr = pte1; |
214 | 76a66253 | j_mayer | ctx->prot = access; |
215 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
216 | b227a8e9 | j_mayer | if (ret == 0) { |
217 | 76a66253 | j_mayer | /* Access granted */
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218 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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219 | 4a057712 | j_mayer | if (loglevel != 0) |
220 | 76a66253 | j_mayer | fprintf(logfile, "PTE access granted !\n");
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221 | 76a66253 | j_mayer | #endif
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222 | 76a66253 | j_mayer | } else {
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223 | 76a66253 | j_mayer | /* Access right violation */
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224 | 76a66253 | j_mayer | #if defined (DEBUG_MMU)
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225 | 4a057712 | j_mayer | if (loglevel != 0) |
226 | 76a66253 | j_mayer | fprintf(logfile, "PTE access rejected\n");
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227 | 76a66253 | j_mayer | #endif
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228 | 76a66253 | j_mayer | } |
229 | 76a66253 | j_mayer | } |
230 | 76a66253 | j_mayer | } |
231 | 76a66253 | j_mayer | |
232 | 76a66253 | j_mayer | return ret;
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233 | 76a66253 | j_mayer | } |
234 | 76a66253 | j_mayer | |
235 | a11b8151 | j_mayer | static always_inline int pte32_check (mmu_ctx_t *ctx, |
236 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
237 | a11b8151 | j_mayer | int h, int rw, int type) |
238 | caa4039c | j_mayer | { |
239 | b227a8e9 | j_mayer | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
240 | caa4039c | j_mayer | } |
241 | caa4039c | j_mayer | |
242 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
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243 | a11b8151 | j_mayer | static always_inline int pte64_check (mmu_ctx_t *ctx, |
244 | a11b8151 | j_mayer | target_ulong pte0, target_ulong pte1, |
245 | a11b8151 | j_mayer | int h, int rw, int type) |
246 | caa4039c | j_mayer | { |
247 | b227a8e9 | j_mayer | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
248 | caa4039c | j_mayer | } |
249 | caa4039c | j_mayer | #endif
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250 | caa4039c | j_mayer | |
251 | a11b8151 | j_mayer | static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
252 | a11b8151 | j_mayer | int ret, int rw) |
253 | 76a66253 | j_mayer | { |
254 | 76a66253 | j_mayer | int store = 0; |
255 | 76a66253 | j_mayer | |
256 | 76a66253 | j_mayer | /* Update page flags */
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257 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000100)) { |
258 | 76a66253 | j_mayer | /* Update accessed flag */
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259 | 76a66253 | j_mayer | *pte1p |= 0x00000100;
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260 | 76a66253 | j_mayer | store = 1;
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261 | 76a66253 | j_mayer | } |
262 | 76a66253 | j_mayer | if (!(*pte1p & 0x00000080)) { |
263 | 76a66253 | j_mayer | if (rw == 1 && ret == 0) { |
264 | 76a66253 | j_mayer | /* Update changed flag */
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265 | 76a66253 | j_mayer | *pte1p |= 0x00000080;
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266 | 76a66253 | j_mayer | store = 1;
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267 | 76a66253 | j_mayer | } else {
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268 | 76a66253 | j_mayer | /* Force page fault for first write access */
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269 | 76a66253 | j_mayer | ctx->prot &= ~PAGE_WRITE; |
270 | 76a66253 | j_mayer | } |
271 | 76a66253 | j_mayer | } |
272 | 76a66253 | j_mayer | |
273 | 76a66253 | j_mayer | return store;
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274 | 76a66253 | j_mayer | } |
275 | 76a66253 | j_mayer | |
276 | 76a66253 | j_mayer | /* Software driven TLB helpers */
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277 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
278 | a11b8151 | j_mayer | int way, int is_code) |
279 | 76a66253 | j_mayer | { |
280 | 76a66253 | j_mayer | int nr;
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281 | 76a66253 | j_mayer | |
282 | 76a66253 | j_mayer | /* Select TLB num in a way from address */
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283 | 76a66253 | j_mayer | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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284 | 76a66253 | j_mayer | /* Select TLB way */
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285 | 76a66253 | j_mayer | nr += env->tlb_per_way * way; |
286 | 76a66253 | j_mayer | /* 6xx have separate TLBs for instructions and data */
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287 | 76a66253 | j_mayer | if (is_code && env->id_tlbs == 1) |
288 | 76a66253 | j_mayer | nr += env->nb_tlb; |
289 | 76a66253 | j_mayer | |
290 | 76a66253 | j_mayer | return nr;
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291 | 76a66253 | j_mayer | } |
292 | 76a66253 | j_mayer | |
293 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) |
294 | 76a66253 | j_mayer | { |
295 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
296 | 76a66253 | j_mayer | int nr, max;
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297 | 76a66253 | j_mayer | |
298 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB) && 0 |
299 | 76a66253 | j_mayer | if (loglevel != 0) { |
300 | 76a66253 | j_mayer | fprintf(logfile, "Invalidate all TLBs\n");
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301 | 76a66253 | j_mayer | } |
302 | 76a66253 | j_mayer | #endif
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303 | 76a66253 | j_mayer | /* Invalidate all defined software TLB */
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304 | 76a66253 | j_mayer | max = env->nb_tlb; |
305 | 76a66253 | j_mayer | if (env->id_tlbs == 1) |
306 | 76a66253 | j_mayer | max *= 2;
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307 | 76a66253 | j_mayer | for (nr = 0; nr < max; nr++) { |
308 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
309 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
310 | 76a66253 | j_mayer | } |
311 | 76a66253 | j_mayer | tlb_flush(env, 1);
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312 | 76a66253 | j_mayer | } |
313 | 76a66253 | j_mayer | |
314 | b068d6a7 | j_mayer | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
315 | b068d6a7 | j_mayer | target_ulong eaddr, |
316 | b068d6a7 | j_mayer | int is_code,
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317 | b068d6a7 | j_mayer | int match_epn)
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318 | 76a66253 | j_mayer | { |
319 | 4a057712 | j_mayer | #if !defined(FLUSH_ALL_TLBS)
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320 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
321 | 76a66253 | j_mayer | int way, nr;
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322 | 76a66253 | j_mayer | |
323 | 76a66253 | j_mayer | /* Invalidate ITLB + DTLB, all ways */
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324 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
325 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
326 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
327 | 76a66253 | j_mayer | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
328 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
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329 | 76a66253 | j_mayer | if (loglevel != 0) { |
330 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
331 | 76a66253 | j_mayer | nr, env->nb_tlb, eaddr); |
332 | 76a66253 | j_mayer | } |
333 | 76a66253 | j_mayer | #endif
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334 | 76a66253 | j_mayer | pte_invalidate(&tlb->pte0); |
335 | 76a66253 | j_mayer | tlb_flush_page(env, tlb->EPN); |
336 | 76a66253 | j_mayer | } |
337 | 76a66253 | j_mayer | } |
338 | 76a66253 | j_mayer | #else
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339 | 76a66253 | j_mayer | /* XXX: PowerPC specification say this is valid as well */
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340 | 76a66253 | j_mayer | ppc6xx_tlb_invalidate_all(env); |
341 | 76a66253 | j_mayer | #endif
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342 | 76a66253 | j_mayer | } |
343 | 76a66253 | j_mayer | |
344 | a11b8151 | j_mayer | static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
345 | a11b8151 | j_mayer | target_ulong eaddr, |
346 | a11b8151 | j_mayer | int is_code)
|
347 | 76a66253 | j_mayer | { |
348 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
349 | 76a66253 | j_mayer | } |
350 | 76a66253 | j_mayer | |
351 | 76a66253 | j_mayer | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
352 | 76a66253 | j_mayer | target_ulong pte0, target_ulong pte1) |
353 | 76a66253 | j_mayer | { |
354 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
355 | 76a66253 | j_mayer | int nr;
|
356 | 76a66253 | j_mayer | |
357 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
358 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
359 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
360 | 76a66253 | j_mayer | if (loglevel != 0) { |
361 | 5fafdf24 | ths | fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
362 | 1b9eb036 | j_mayer | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
363 | 76a66253 | j_mayer | } |
364 | 76a66253 | j_mayer | #endif
|
365 | 76a66253 | j_mayer | /* Invalidate any pending reference in Qemu for this virtual address */
|
366 | 76a66253 | j_mayer | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
367 | 76a66253 | j_mayer | tlb->pte0 = pte0; |
368 | 76a66253 | j_mayer | tlb->pte1 = pte1; |
369 | 76a66253 | j_mayer | tlb->EPN = EPN; |
370 | 76a66253 | j_mayer | /* Store last way for LRU mechanism */
|
371 | 76a66253 | j_mayer | env->last_way = way; |
372 | 76a66253 | j_mayer | } |
373 | 76a66253 | j_mayer | |
374 | a11b8151 | j_mayer | static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
375 | a11b8151 | j_mayer | target_ulong eaddr, int rw,
|
376 | a11b8151 | j_mayer | int access_type)
|
377 | 76a66253 | j_mayer | { |
378 | 1d0a48fb | j_mayer | ppc6xx_tlb_t *tlb; |
379 | 76a66253 | j_mayer | int nr, best, way;
|
380 | 76a66253 | j_mayer | int ret;
|
381 | d9bce9d9 | j_mayer | |
382 | 76a66253 | j_mayer | best = -1;
|
383 | 76a66253 | j_mayer | ret = -1; /* No TLB found */ |
384 | 76a66253 | j_mayer | for (way = 0; way < env->nb_ways; way++) { |
385 | 76a66253 | j_mayer | nr = ppc6xx_tlb_getnum(env, eaddr, way, |
386 | 76a66253 | j_mayer | access_type == ACCESS_CODE ? 1 : 0); |
387 | 1d0a48fb | j_mayer | tlb = &env->tlb[nr].tlb6; |
388 | 76a66253 | j_mayer | /* This test "emulates" the PTE index match for hardware TLBs */
|
389 | 76a66253 | j_mayer | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
390 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
391 | 76a66253 | j_mayer | if (loglevel != 0) { |
392 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
393 | 1b9eb036 | j_mayer | "] <> " ADDRX "\n", |
394 | 76a66253 | j_mayer | nr, env->nb_tlb, |
395 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
396 | 76a66253 | j_mayer | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
397 | 76a66253 | j_mayer | } |
398 | 76a66253 | j_mayer | #endif
|
399 | 76a66253 | j_mayer | continue;
|
400 | 76a66253 | j_mayer | } |
401 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
402 | 76a66253 | j_mayer | if (loglevel != 0) { |
403 | 1b9eb036 | j_mayer | fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
404 | 1b9eb036 | j_mayer | " %c %c\n",
|
405 | 76a66253 | j_mayer | nr, env->nb_tlb, |
406 | 76a66253 | j_mayer | pte_is_valid(tlb->pte0) ? "valid" : "inval", |
407 | 76a66253 | j_mayer | tlb->EPN, eaddr, tlb->pte1, |
408 | 76a66253 | j_mayer | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
409 | 76a66253 | j_mayer | } |
410 | 76a66253 | j_mayer | #endif
|
411 | b227a8e9 | j_mayer | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
412 | 76a66253 | j_mayer | case -3: |
413 | 76a66253 | j_mayer | /* TLB inconsistency */
|
414 | 76a66253 | j_mayer | return -1; |
415 | 76a66253 | j_mayer | case -2: |
416 | 76a66253 | j_mayer | /* Access violation */
|
417 | 76a66253 | j_mayer | ret = -2;
|
418 | 76a66253 | j_mayer | best = nr; |
419 | 76a66253 | j_mayer | break;
|
420 | 76a66253 | j_mayer | case -1: |
421 | 76a66253 | j_mayer | default:
|
422 | 76a66253 | j_mayer | /* No match */
|
423 | 76a66253 | j_mayer | break;
|
424 | 76a66253 | j_mayer | case 0: |
425 | 76a66253 | j_mayer | /* access granted */
|
426 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all TLBs consistency
|
427 | 76a66253 | j_mayer | * but we can speed-up the whole thing as the
|
428 | 76a66253 | j_mayer | * result would be undefined if TLBs are not consistent.
|
429 | 76a66253 | j_mayer | */
|
430 | 76a66253 | j_mayer | ret = 0;
|
431 | 76a66253 | j_mayer | best = nr; |
432 | 76a66253 | j_mayer | goto done;
|
433 | 76a66253 | j_mayer | } |
434 | 76a66253 | j_mayer | } |
435 | 76a66253 | j_mayer | if (best != -1) { |
436 | 76a66253 | j_mayer | done:
|
437 | 76a66253 | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
438 | 4a057712 | j_mayer | if (loglevel != 0) { |
439 | 76a66253 | j_mayer | fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
|
440 | 76a66253 | j_mayer | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
441 | 76a66253 | j_mayer | } |
442 | 76a66253 | j_mayer | #endif
|
443 | 76a66253 | j_mayer | /* Update page flags */
|
444 | 1d0a48fb | j_mayer | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
445 | 76a66253 | j_mayer | } |
446 | 76a66253 | j_mayer | |
447 | 76a66253 | j_mayer | return ret;
|
448 | 76a66253 | j_mayer | } |
449 | 76a66253 | j_mayer | |
450 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
|
451 | a11b8151 | j_mayer | static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, |
452 | a11b8151 | j_mayer | target_ulong virtual, int rw, int type) |
453 | 9a64fbe4 | bellard | { |
454 | 76a66253 | j_mayer | target_ulong *BATlt, *BATut, *BATu, *BATl; |
455 | 76a66253 | j_mayer | target_ulong base, BEPIl, BEPIu, bl; |
456 | 0411a972 | j_mayer | int i, pp, pr;
|
457 | 9a64fbe4 | bellard | int ret = -1; |
458 | 9a64fbe4 | bellard | |
459 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
460 | 4a057712 | j_mayer | if (loglevel != 0) { |
461 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
462 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
463 | 9a64fbe4 | bellard | } |
464 | 9a64fbe4 | bellard | #endif
|
465 | 0411a972 | j_mayer | pr = msr_pr; |
466 | 9a64fbe4 | bellard | switch (type) {
|
467 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
468 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
|
469 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
|
470 | 9a64fbe4 | bellard | break;
|
471 | 9a64fbe4 | bellard | default:
|
472 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
|
473 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
|
474 | 9a64fbe4 | bellard | break;
|
475 | 9a64fbe4 | bellard | } |
476 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
477 | 4a057712 | j_mayer | if (loglevel != 0) { |
478 | 1b9eb036 | j_mayer | fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
479 | 76a66253 | j_mayer | type == ACCESS_CODE ? 'I' : 'D', virtual); |
480 | 9a64fbe4 | bellard | } |
481 | 9a64fbe4 | bellard | #endif
|
482 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
|
483 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
484 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
485 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
486 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
|
487 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
|
488 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
489 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
490 | 4a057712 | j_mayer | if (loglevel != 0) { |
491 | 5fafdf24 | ths | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
492 | 1b9eb036 | j_mayer | " BATl 0x" ADDRX "\n", |
493 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
494 | 9a64fbe4 | bellard | *BATu, *BATl); |
495 | 9a64fbe4 | bellard | } |
496 | 9a64fbe4 | bellard | #endif
|
497 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
498 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
499 | 9a64fbe4 | bellard | /* BAT matches */
|
500 | 0411a972 | j_mayer | if (((pr == 0) && (*BATu & 0x00000002)) || |
501 | 0411a972 | j_mayer | ((pr != 0) && (*BATu & 0x00000001))) { |
502 | 9a64fbe4 | bellard | /* Get physical address */
|
503 | 76a66253 | j_mayer | ctx->raddr = (*BATl & 0xF0000000) |
|
504 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
505 | a541f297 | bellard | (virtual & 0x0001F000);
|
506 | b227a8e9 | j_mayer | /* Compute access rights */
|
507 | b227a8e9 | j_mayer | pp = *BATl & 0x00000003;
|
508 | b227a8e9 | j_mayer | ctx->prot = 0;
|
509 | b227a8e9 | j_mayer | if (pp != 0) { |
510 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
511 | b227a8e9 | j_mayer | if (pp == 0x2) |
512 | b227a8e9 | j_mayer | ctx->prot |= PAGE_WRITE; |
513 | b227a8e9 | j_mayer | } |
514 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, type); |
515 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
516 | b227a8e9 | j_mayer | if (ret == 0 && loglevel != 0) { |
517 | 4a057712 | j_mayer | fprintf(logfile, "BAT %d match: r 0x" PADDRX
|
518 | 1b9eb036 | j_mayer | " prot=%c%c\n",
|
519 | 76a66253 | j_mayer | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
520 | 76a66253 | j_mayer | ctx->prot & PAGE_WRITE ? 'W' : '-'); |
521 | 9a64fbe4 | bellard | } |
522 | 9a64fbe4 | bellard | #endif
|
523 | 9a64fbe4 | bellard | break;
|
524 | 9a64fbe4 | bellard | } |
525 | 9a64fbe4 | bellard | } |
526 | 9a64fbe4 | bellard | } |
527 | 9a64fbe4 | bellard | if (ret < 0) { |
528 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
|
529 | 4a057712 | j_mayer | if (loglevel != 0) { |
530 | 4a057712 | j_mayer | fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual); |
531 | 4a057712 | j_mayer | for (i = 0; i < 4; i++) { |
532 | 4a057712 | j_mayer | BATu = &BATut[i]; |
533 | 4a057712 | j_mayer | BATl = &BATlt[i]; |
534 | 4a057712 | j_mayer | BEPIu = *BATu & 0xF0000000;
|
535 | 4a057712 | j_mayer | BEPIl = *BATu & 0x0FFE0000;
|
536 | 4a057712 | j_mayer | bl = (*BATu & 0x00001FFC) << 15; |
537 | 4a057712 | j_mayer | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
538 | 4a057712 | j_mayer | " BATl 0x" ADDRX " \n\t" |
539 | 4a057712 | j_mayer | "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", |
540 | 4a057712 | j_mayer | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
541 | 4a057712 | j_mayer | *BATu, *BATl, BEPIu, BEPIl, bl); |
542 | 4a057712 | j_mayer | } |
543 | 9a64fbe4 | bellard | } |
544 | 9a64fbe4 | bellard | #endif
|
545 | 9a64fbe4 | bellard | } |
546 | b227a8e9 | j_mayer | |
547 | 9a64fbe4 | bellard | /* No hit */
|
548 | 9a64fbe4 | bellard | return ret;
|
549 | 9a64fbe4 | bellard | } |
550 | 9a64fbe4 | bellard | |
551 | 9a64fbe4 | bellard | /* PTE table lookup */
|
552 | b227a8e9 | j_mayer | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
553 | b227a8e9 | j_mayer | int rw, int type) |
554 | 9a64fbe4 | bellard | { |
555 | 76a66253 | j_mayer | target_ulong base, pte0, pte1; |
556 | 76a66253 | j_mayer | int i, good = -1; |
557 | caa4039c | j_mayer | int ret, r;
|
558 | 9a64fbe4 | bellard | |
559 | 76a66253 | j_mayer | ret = -1; /* No entry found */ |
560 | 76a66253 | j_mayer | base = ctx->pg_addr[h]; |
561 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
562 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
563 | caa4039c | j_mayer | if (is_64b) {
|
564 | caa4039c | j_mayer | pte0 = ldq_phys(base + (i * 16));
|
565 | caa4039c | j_mayer | pte1 = ldq_phys(base + (i * 16) + 8); |
566 | b227a8e9 | j_mayer | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
567 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
568 | 12de9a39 | j_mayer | if (loglevel != 0) { |
569 | 12de9a39 | j_mayer | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
570 | 12de9a39 | j_mayer | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
571 | 12de9a39 | j_mayer | base + (i * 16), pte0, pte1,
|
572 | 12de9a39 | j_mayer | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), |
573 | 12de9a39 | j_mayer | ctx->ptem); |
574 | 12de9a39 | j_mayer | } |
575 | 12de9a39 | j_mayer | #endif
|
576 | caa4039c | j_mayer | } else
|
577 | caa4039c | j_mayer | #endif
|
578 | caa4039c | j_mayer | { |
579 | caa4039c | j_mayer | pte0 = ldl_phys(base + (i * 8));
|
580 | caa4039c | j_mayer | pte1 = ldl_phys(base + (i * 8) + 4); |
581 | b227a8e9 | j_mayer | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
582 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
583 | 12de9a39 | j_mayer | if (loglevel != 0) { |
584 | 12de9a39 | j_mayer | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
585 | 12de9a39 | j_mayer | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", |
586 | 12de9a39 | j_mayer | base + (i * 8), pte0, pte1,
|
587 | 12de9a39 | j_mayer | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), |
588 | 12de9a39 | j_mayer | ctx->ptem); |
589 | 12de9a39 | j_mayer | } |
590 | 9a64fbe4 | bellard | #endif
|
591 | 12de9a39 | j_mayer | } |
592 | caa4039c | j_mayer | switch (r) {
|
593 | 76a66253 | j_mayer | case -3: |
594 | 76a66253 | j_mayer | /* PTE inconsistency */
|
595 | 76a66253 | j_mayer | return -1; |
596 | 76a66253 | j_mayer | case -2: |
597 | 76a66253 | j_mayer | /* Access violation */
|
598 | 76a66253 | j_mayer | ret = -2;
|
599 | 76a66253 | j_mayer | good = i; |
600 | 76a66253 | j_mayer | break;
|
601 | 76a66253 | j_mayer | case -1: |
602 | 76a66253 | j_mayer | default:
|
603 | 76a66253 | j_mayer | /* No PTE match */
|
604 | 76a66253 | j_mayer | break;
|
605 | 76a66253 | j_mayer | case 0: |
606 | 76a66253 | j_mayer | /* access granted */
|
607 | 76a66253 | j_mayer | /* XXX: we should go on looping to check all PTEs consistency
|
608 | 76a66253 | j_mayer | * but if we can speed-up the whole thing as the
|
609 | 76a66253 | j_mayer | * result would be undefined if PTEs are not consistent.
|
610 | 76a66253 | j_mayer | */
|
611 | 76a66253 | j_mayer | ret = 0;
|
612 | 76a66253 | j_mayer | good = i; |
613 | 76a66253 | j_mayer | goto done;
|
614 | 9a64fbe4 | bellard | } |
615 | 9a64fbe4 | bellard | } |
616 | 9a64fbe4 | bellard | if (good != -1) { |
617 | 76a66253 | j_mayer | done:
|
618 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
619 | 4a057712 | j_mayer | if (loglevel != 0) { |
620 | 4a057712 | j_mayer | fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x " |
621 | 1b9eb036 | j_mayer | "ret=%d\n",
|
622 | 76a66253 | j_mayer | ctx->raddr, ctx->prot, ret); |
623 | 76a66253 | j_mayer | } |
624 | 9a64fbe4 | bellard | #endif
|
625 | 9a64fbe4 | bellard | /* Update page flags */
|
626 | 76a66253 | j_mayer | pte1 = ctx->raddr; |
627 | caa4039c | j_mayer | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
628 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
629 | caa4039c | j_mayer | if (is_64b) {
|
630 | caa4039c | j_mayer | stq_phys_notdirty(base + (good * 16) + 8, pte1); |
631 | caa4039c | j_mayer | } else
|
632 | caa4039c | j_mayer | #endif
|
633 | caa4039c | j_mayer | { |
634 | caa4039c | j_mayer | stl_phys_notdirty(base + (good * 8) + 4, pte1); |
635 | caa4039c | j_mayer | } |
636 | caa4039c | j_mayer | } |
637 | 9a64fbe4 | bellard | } |
638 | 9a64fbe4 | bellard | |
639 | 9a64fbe4 | bellard | return ret;
|
640 | 79aceca5 | bellard | } |
641 | 79aceca5 | bellard | |
642 | a11b8151 | j_mayer | static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type) |
643 | caa4039c | j_mayer | { |
644 | b227a8e9 | j_mayer | return _find_pte(ctx, 0, h, rw, type); |
645 | caa4039c | j_mayer | } |
646 | caa4039c | j_mayer | |
647 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
648 | a11b8151 | j_mayer | static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type) |
649 | caa4039c | j_mayer | { |
650 | b227a8e9 | j_mayer | return _find_pte(ctx, 1, h, rw, type); |
651 | caa4039c | j_mayer | } |
652 | caa4039c | j_mayer | #endif
|
653 | caa4039c | j_mayer | |
654 | b068d6a7 | j_mayer | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
655 | b227a8e9 | j_mayer | int h, int rw, int type) |
656 | caa4039c | j_mayer | { |
657 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
658 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B)
|
659 | b227a8e9 | j_mayer | return find_pte64(ctx, h, rw, type);
|
660 | caa4039c | j_mayer | #endif
|
661 | caa4039c | j_mayer | |
662 | b227a8e9 | j_mayer | return find_pte32(ctx, h, rw, type);
|
663 | caa4039c | j_mayer | } |
664 | caa4039c | j_mayer | |
665 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
666 | a11b8151 | j_mayer | static always_inline int slb_is_valid (uint64_t slb64) |
667 | eacc3249 | j_mayer | { |
668 | eacc3249 | j_mayer | return slb64 & 0x0000000008000000ULL ? 1 : 0; |
669 | eacc3249 | j_mayer | } |
670 | eacc3249 | j_mayer | |
671 | a11b8151 | j_mayer | static always_inline void slb_invalidate (uint64_t *slb64) |
672 | eacc3249 | j_mayer | { |
673 | eacc3249 | j_mayer | *slb64 &= ~0x0000000008000000ULL;
|
674 | eacc3249 | j_mayer | } |
675 | eacc3249 | j_mayer | |
676 | a11b8151 | j_mayer | static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
677 | a11b8151 | j_mayer | target_ulong *vsid, |
678 | a11b8151 | j_mayer | target_ulong *page_mask, int *attr)
|
679 | caa4039c | j_mayer | { |
680 | caa4039c | j_mayer | target_phys_addr_t sr_base; |
681 | caa4039c | j_mayer | target_ulong mask; |
682 | caa4039c | j_mayer | uint64_t tmp64; |
683 | caa4039c | j_mayer | uint32_t tmp; |
684 | caa4039c | j_mayer | int n, ret;
|
685 | caa4039c | j_mayer | |
686 | caa4039c | j_mayer | ret = -5;
|
687 | caa4039c | j_mayer | sr_base = env->spr[SPR_ASR]; |
688 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
689 | 12de9a39 | j_mayer | if (loglevel != 0) { |
690 | 12de9a39 | j_mayer | fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n", |
691 | 12de9a39 | j_mayer | __func__, eaddr, sr_base); |
692 | 12de9a39 | j_mayer | } |
693 | 12de9a39 | j_mayer | #endif
|
694 | caa4039c | j_mayer | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
695 | eacc3249 | j_mayer | for (n = 0; n < env->slb_nr; n++) { |
696 | caa4039c | j_mayer | tmp64 = ldq_phys(sr_base); |
697 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
698 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
699 | 12de9a39 | j_mayer | if (loglevel != 0) { |
700 | b33c17e1 | j_mayer | fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08" |
701 | b33c17e1 | j_mayer | PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
|
702 | 12de9a39 | j_mayer | } |
703 | 12de9a39 | j_mayer | #endif
|
704 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
705 | caa4039c | j_mayer | /* SLB entry is valid */
|
706 | caa4039c | j_mayer | switch (tmp64 & 0x0000000006000000ULL) { |
707 | caa4039c | j_mayer | case 0x0000000000000000ULL: |
708 | caa4039c | j_mayer | /* 256 MB segment */
|
709 | caa4039c | j_mayer | mask = 0xFFFFFFFFF0000000ULL;
|
710 | caa4039c | j_mayer | break;
|
711 | caa4039c | j_mayer | case 0x0000000002000000ULL: |
712 | caa4039c | j_mayer | /* 1 TB segment */
|
713 | caa4039c | j_mayer | mask = 0xFFFF000000000000ULL;
|
714 | caa4039c | j_mayer | break;
|
715 | caa4039c | j_mayer | case 0x0000000004000000ULL: |
716 | caa4039c | j_mayer | case 0x0000000006000000ULL: |
717 | caa4039c | j_mayer | /* Reserved => segment is invalid */
|
718 | caa4039c | j_mayer | continue;
|
719 | caa4039c | j_mayer | } |
720 | caa4039c | j_mayer | if ((eaddr & mask) == (tmp64 & mask)) {
|
721 | caa4039c | j_mayer | /* SLB match */
|
722 | caa4039c | j_mayer | *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
723 | caa4039c | j_mayer | *page_mask = ~mask; |
724 | caa4039c | j_mayer | *attr = tmp & 0xFF;
|
725 | eacc3249 | j_mayer | ret = n; |
726 | caa4039c | j_mayer | break;
|
727 | caa4039c | j_mayer | } |
728 | caa4039c | j_mayer | } |
729 | caa4039c | j_mayer | sr_base += 12;
|
730 | caa4039c | j_mayer | } |
731 | caa4039c | j_mayer | |
732 | caa4039c | j_mayer | return ret;
|
733 | 79aceca5 | bellard | } |
734 | 12de9a39 | j_mayer | |
735 | eacc3249 | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env)
|
736 | eacc3249 | j_mayer | { |
737 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
738 | eacc3249 | j_mayer | uint64_t tmp64; |
739 | eacc3249 | j_mayer | int n, do_invalidate;
|
740 | eacc3249 | j_mayer | |
741 | eacc3249 | j_mayer | do_invalidate = 0;
|
742 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
743 | 2c1ee068 | j_mayer | /* XXX: Warning: slbia never invalidates the first segment */
|
744 | 2c1ee068 | j_mayer | for (n = 1; n < env->slb_nr; n++) { |
745 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
746 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
747 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
748 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
749 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
750 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
751 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
752 | eacc3249 | j_mayer | */
|
753 | eacc3249 | j_mayer | do_invalidate = 1;
|
754 | eacc3249 | j_mayer | } |
755 | eacc3249 | j_mayer | sr_base += 12;
|
756 | eacc3249 | j_mayer | } |
757 | eacc3249 | j_mayer | if (do_invalidate)
|
758 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
759 | eacc3249 | j_mayer | } |
760 | eacc3249 | j_mayer | |
761 | eacc3249 | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
762 | eacc3249 | j_mayer | { |
763 | eacc3249 | j_mayer | target_phys_addr_t sr_base; |
764 | eacc3249 | j_mayer | target_ulong vsid, page_mask; |
765 | eacc3249 | j_mayer | uint64_t tmp64; |
766 | eacc3249 | j_mayer | int attr;
|
767 | eacc3249 | j_mayer | int n;
|
768 | eacc3249 | j_mayer | |
769 | eacc3249 | j_mayer | n = slb_lookup(env, T0, &vsid, &page_mask, &attr); |
770 | eacc3249 | j_mayer | if (n >= 0) { |
771 | eacc3249 | j_mayer | sr_base = env->spr[SPR_ASR]; |
772 | eacc3249 | j_mayer | sr_base += 12 * n;
|
773 | eacc3249 | j_mayer | tmp64 = ldq_phys(sr_base); |
774 | eacc3249 | j_mayer | if (slb_is_valid(tmp64)) {
|
775 | eacc3249 | j_mayer | slb_invalidate(&tmp64); |
776 | eacc3249 | j_mayer | stq_phys(sr_base, tmp64); |
777 | eacc3249 | j_mayer | /* XXX: given the fact that segment size is 256 MB or 1TB,
|
778 | eacc3249 | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask)
|
779 | eacc3249 | j_mayer | * in Qemu, we just invalidate all TLBs
|
780 | eacc3249 | j_mayer | */
|
781 | eacc3249 | j_mayer | tlb_flush(env, 1);
|
782 | eacc3249 | j_mayer | } |
783 | eacc3249 | j_mayer | } |
784 | eacc3249 | j_mayer | } |
785 | eacc3249 | j_mayer | |
786 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
|
787 | 12de9a39 | j_mayer | { |
788 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
789 | 12de9a39 | j_mayer | target_ulong rt; |
790 | 12de9a39 | j_mayer | uint64_t tmp64; |
791 | 12de9a39 | j_mayer | uint32_t tmp; |
792 | 12de9a39 | j_mayer | |
793 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
794 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
795 | 12de9a39 | j_mayer | tmp64 = ldq_phys(sr_base); |
796 | 12de9a39 | j_mayer | tmp = ldl_phys(sr_base + 8);
|
797 | 12de9a39 | j_mayer | if (tmp64 & 0x0000000008000000ULL) { |
798 | 12de9a39 | j_mayer | /* SLB entry is valid */
|
799 | 12de9a39 | j_mayer | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
|
800 | 12de9a39 | j_mayer | rt = tmp >> 8; /* 65:88 => 40:63 */ |
801 | 12de9a39 | j_mayer | rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ |
802 | 12de9a39 | j_mayer | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
|
803 | 12de9a39 | j_mayer | rt |= ((tmp >> 4) & 0xF) << 27; |
804 | 12de9a39 | j_mayer | } else {
|
805 | 12de9a39 | j_mayer | rt = 0;
|
806 | 12de9a39 | j_mayer | } |
807 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
808 | 12de9a39 | j_mayer | if (loglevel != 0) { |
809 | 12de9a39 | j_mayer | fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d " |
810 | 12de9a39 | j_mayer | ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
|
811 | 12de9a39 | j_mayer | } |
812 | 12de9a39 | j_mayer | #endif
|
813 | 12de9a39 | j_mayer | |
814 | 12de9a39 | j_mayer | return rt;
|
815 | 12de9a39 | j_mayer | } |
816 | 12de9a39 | j_mayer | |
817 | 12de9a39 | j_mayer | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs) |
818 | 12de9a39 | j_mayer | { |
819 | 12de9a39 | j_mayer | target_phys_addr_t sr_base; |
820 | 12de9a39 | j_mayer | uint64_t tmp64; |
821 | 12de9a39 | j_mayer | uint32_t tmp; |
822 | 12de9a39 | j_mayer | |
823 | 12de9a39 | j_mayer | sr_base = env->spr[SPR_ASR]; |
824 | 12de9a39 | j_mayer | sr_base += 12 * slb_nr;
|
825 | 12de9a39 | j_mayer | /* Copy Rs bits 37:63 to SLB 62:88 */
|
826 | 12de9a39 | j_mayer | tmp = rs << 8;
|
827 | 12de9a39 | j_mayer | tmp64 = (rs >> 24) & 0x7; |
828 | 12de9a39 | j_mayer | /* Copy Rs bits 33:36 to SLB 89:92 */
|
829 | 12de9a39 | j_mayer | tmp |= ((rs >> 27) & 0xF) << 4; |
830 | 12de9a39 | j_mayer | /* Set the valid bit */
|
831 | 12de9a39 | j_mayer | tmp64 |= 1 << 27; |
832 | 12de9a39 | j_mayer | /* Set ESID */
|
833 | 12de9a39 | j_mayer | tmp64 |= (uint32_t)slb_nr << 28;
|
834 | 12de9a39 | j_mayer | #if defined(DEBUG_SLB)
|
835 | 12de9a39 | j_mayer | if (loglevel != 0) { |
836 | 12de9a39 | j_mayer | fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08" |
837 | 12de9a39 | j_mayer | PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
|
838 | 12de9a39 | j_mayer | } |
839 | 12de9a39 | j_mayer | #endif
|
840 | 12de9a39 | j_mayer | /* Write SLB entry to memory */
|
841 | 12de9a39 | j_mayer | stq_phys(sr_base, tmp64); |
842 | 12de9a39 | j_mayer | stl_phys(sr_base + 8, tmp);
|
843 | 12de9a39 | j_mayer | } |
844 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
845 | 79aceca5 | bellard | |
846 | 9a64fbe4 | bellard | /* Perform segment based translation */
|
847 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
|
848 | b068d6a7 | j_mayer | int sdr_sh,
|
849 | b068d6a7 | j_mayer | target_phys_addr_t hash, |
850 | b068d6a7 | j_mayer | target_phys_addr_t mask) |
851 | 12de9a39 | j_mayer | { |
852 | 12de9a39 | j_mayer | return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask); |
853 | 12de9a39 | j_mayer | } |
854 | 12de9a39 | j_mayer | |
855 | a11b8151 | j_mayer | static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, |
856 | a11b8151 | j_mayer | target_ulong eaddr, int rw, int type) |
857 | 79aceca5 | bellard | { |
858 | 12de9a39 | j_mayer | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
859 | caa4039c | j_mayer | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
860 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
861 | caa4039c | j_mayer | int attr;
|
862 | 9a64fbe4 | bellard | #endif
|
863 | 0411a972 | j_mayer | int ds, vsid_sh, sdr_sh, pr;
|
864 | caa4039c | j_mayer | int ret, ret2;
|
865 | caa4039c | j_mayer | |
866 | 0411a972 | j_mayer | pr = msr_pr; |
867 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
868 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
869 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
870 | 12de9a39 | j_mayer | if (loglevel != 0) { |
871 | 12de9a39 | j_mayer | fprintf(logfile, "Check SLBs\n");
|
872 | 12de9a39 | j_mayer | } |
873 | 12de9a39 | j_mayer | #endif
|
874 | caa4039c | j_mayer | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr); |
875 | caa4039c | j_mayer | if (ret < 0) |
876 | caa4039c | j_mayer | return ret;
|
877 | 0411a972 | j_mayer | ctx->key = ((attr & 0x40) && (pr != 0)) || |
878 | 0411a972 | j_mayer | ((attr & 0x80) && (pr == 0)) ? 1 : 0; |
879 | caa4039c | j_mayer | ds = 0;
|
880 | b227a8e9 | j_mayer | ctx->nx = attr & 0x20 ? 1 : 0; |
881 | caa4039c | j_mayer | vsid_mask = 0x00003FFFFFFFFF80ULL;
|
882 | caa4039c | j_mayer | vsid_sh = 7;
|
883 | caa4039c | j_mayer | sdr_sh = 18;
|
884 | caa4039c | j_mayer | sdr_mask = 0x3FF80;
|
885 | caa4039c | j_mayer | } else
|
886 | caa4039c | j_mayer | #endif /* defined(TARGET_PPC64) */ |
887 | caa4039c | j_mayer | { |
888 | caa4039c | j_mayer | sr = env->sr[eaddr >> 28];
|
889 | caa4039c | j_mayer | page_mask = 0x0FFFFFFF;
|
890 | 0411a972 | j_mayer | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
891 | 0411a972 | j_mayer | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
892 | caa4039c | j_mayer | ds = sr & 0x80000000 ? 1 : 0; |
893 | b227a8e9 | j_mayer | ctx->nx = sr & 0x10000000 ? 1 : 0; |
894 | caa4039c | j_mayer | vsid = sr & 0x00FFFFFF;
|
895 | caa4039c | j_mayer | vsid_mask = 0x01FFFFC0;
|
896 | caa4039c | j_mayer | vsid_sh = 6;
|
897 | caa4039c | j_mayer | sdr_sh = 16;
|
898 | caa4039c | j_mayer | sdr_mask = 0xFFC0;
|
899 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
900 | caa4039c | j_mayer | if (loglevel != 0) { |
901 | caa4039c | j_mayer | fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX |
902 | caa4039c | j_mayer | " nip=0x" ADDRX " lr=0x" ADDRX |
903 | caa4039c | j_mayer | " ir=%d dr=%d pr=%d %d t=%d\n",
|
904 | caa4039c | j_mayer | eaddr, (int)(eaddr >> 28), sr, env->nip, |
905 | 0411a972 | j_mayer | env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, |
906 | 0411a972 | j_mayer | rw, type); |
907 | caa4039c | j_mayer | } |
908 | 9a64fbe4 | bellard | #endif
|
909 | caa4039c | j_mayer | } |
910 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
911 | 12de9a39 | j_mayer | if (loglevel != 0) { |
912 | 12de9a39 | j_mayer | fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", |
913 | b227a8e9 | j_mayer | ctx->key, ds, ctx->nx, vsid); |
914 | 12de9a39 | j_mayer | } |
915 | 12de9a39 | j_mayer | #endif
|
916 | caa4039c | j_mayer | ret = -1;
|
917 | caa4039c | j_mayer | if (!ds) {
|
918 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
|
919 | b227a8e9 | j_mayer | if (type != ACCESS_CODE || ctx->nx == 0) { |
920 | 9a64fbe4 | bellard | /* Page address translation */
|
921 | 76a66253 | j_mayer | /* Primary table address */
|
922 | 76a66253 | j_mayer | sdr = env->sdr1; |
923 | 12de9a39 | j_mayer | pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS; |
924 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
925 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
926 | 12de9a39 | j_mayer | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
927 | 12de9a39 | j_mayer | /* XXX: this is false for 1 TB segments */
|
928 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
929 | 12de9a39 | j_mayer | } else
|
930 | 12de9a39 | j_mayer | #endif
|
931 | 12de9a39 | j_mayer | { |
932 | 12de9a39 | j_mayer | htab_mask = sdr & 0x000001FF;
|
933 | 12de9a39 | j_mayer | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
934 | 12de9a39 | j_mayer | } |
935 | 12de9a39 | j_mayer | mask = (htab_mask << sdr_sh) | sdr_mask; |
936 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
937 | 12de9a39 | j_mayer | if (loglevel != 0) { |
938 | 12de9a39 | j_mayer | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask " |
939 | 12de9a39 | j_mayer | PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask, |
940 | 12de9a39 | j_mayer | page_mask); |
941 | 12de9a39 | j_mayer | } |
942 | 12de9a39 | j_mayer | #endif
|
943 | caa4039c | j_mayer | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
944 | 76a66253 | j_mayer | /* Secondary table address */
|
945 | caa4039c | j_mayer | hash = (~hash) & vsid_mask; |
946 | 12de9a39 | j_mayer | #if defined (DEBUG_MMU)
|
947 | 12de9a39 | j_mayer | if (loglevel != 0) { |
948 | 12de9a39 | j_mayer | fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask " |
949 | 12de9a39 | j_mayer | PADDRX "\n", sdr, sdr_sh, hash, mask);
|
950 | 12de9a39 | j_mayer | } |
951 | 12de9a39 | j_mayer | #endif
|
952 | caa4039c | j_mayer | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
953 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
954 | 12de9a39 | j_mayer | if (env->mmu_model == POWERPC_MMU_64B) {
|
955 | caa4039c | j_mayer | /* Only 5 bits of the page index are used in the AVPN */
|
956 | caa4039c | j_mayer | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
957 | caa4039c | j_mayer | } else
|
958 | caa4039c | j_mayer | #endif
|
959 | caa4039c | j_mayer | { |
960 | caa4039c | j_mayer | ctx->ptem = (vsid << 7) | (pgidx >> 10); |
961 | caa4039c | j_mayer | } |
962 | 76a66253 | j_mayer | /* Initialize real address with an invalid value */
|
963 | 76a66253 | j_mayer | ctx->raddr = (target_ulong)-1;
|
964 | 7dbe11ac | j_mayer | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
965 | 7dbe11ac | j_mayer | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { |
966 | 76a66253 | j_mayer | /* Software TLB search */
|
967 | 76a66253 | j_mayer | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
968 | 76a66253 | j_mayer | } else {
|
969 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
970 | 4a057712 | j_mayer | if (loglevel != 0) { |
971 | 4a057712 | j_mayer | fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x " |
972 | 4a057712 | j_mayer | "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n", |
973 | 4a057712 | j_mayer | sdr, (uint32_t)vsid, (uint32_t)pgidx, |
974 | 4a057712 | j_mayer | (uint32_t)hash, ctx->pg_addr[0]);
|
975 | 76a66253 | j_mayer | } |
976 | 9a64fbe4 | bellard | #endif
|
977 | 76a66253 | j_mayer | /* Primary table lookup */
|
978 | b227a8e9 | j_mayer | ret = find_pte(env, ctx, 0, rw, type);
|
979 | 76a66253 | j_mayer | if (ret < 0) { |
980 | 76a66253 | j_mayer | /* Secondary table lookup */
|
981 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
982 | 4a057712 | j_mayer | if (eaddr != 0xEFFFFFFF && loglevel != 0) { |
983 | 76a66253 | j_mayer | fprintf(logfile, |
984 | 4a057712 | j_mayer | "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x " |
985 | 4a057712 | j_mayer | "hash=0x%05x pg_addr=0x" PADDRX "\n", |
986 | 4a057712 | j_mayer | sdr, (uint32_t)vsid, (uint32_t)pgidx, |
987 | 4a057712 | j_mayer | (uint32_t)hash, ctx->pg_addr[1]);
|
988 | 76a66253 | j_mayer | } |
989 | 9a64fbe4 | bellard | #endif
|
990 | b227a8e9 | j_mayer | ret2 = find_pte(env, ctx, 1, rw, type);
|
991 | 76a66253 | j_mayer | if (ret2 != -1) |
992 | 76a66253 | j_mayer | ret = ret2; |
993 | 76a66253 | j_mayer | } |
994 | 9a64fbe4 | bellard | } |
995 | 0411a972 | j_mayer | #if defined (DUMP_PAGE_TABLES)
|
996 | b33c17e1 | j_mayer | if (loglevel != 0) { |
997 | b33c17e1 | j_mayer | target_phys_addr_t curaddr; |
998 | b33c17e1 | j_mayer | uint32_t a0, a1, a2, a3; |
999 | b33c17e1 | j_mayer | fprintf(logfile, |
1000 | b33c17e1 | j_mayer | "Page table: " PADDRX " len " PADDRX "\n", |
1001 | b33c17e1 | j_mayer | sdr, mask + 0x80);
|
1002 | b33c17e1 | j_mayer | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
1003 | b33c17e1 | j_mayer | curaddr += 16) {
|
1004 | b33c17e1 | j_mayer | a0 = ldl_phys(curaddr); |
1005 | b33c17e1 | j_mayer | a1 = ldl_phys(curaddr + 4);
|
1006 | b33c17e1 | j_mayer | a2 = ldl_phys(curaddr + 8);
|
1007 | b33c17e1 | j_mayer | a3 = ldl_phys(curaddr + 12);
|
1008 | b33c17e1 | j_mayer | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
1009 | 12de9a39 | j_mayer | fprintf(logfile, |
1010 | b33c17e1 | j_mayer | PADDRX ": %08x %08x %08x %08x\n",
|
1011 | b33c17e1 | j_mayer | curaddr, a0, a1, a2, a3); |
1012 | 12de9a39 | j_mayer | } |
1013 | b33c17e1 | j_mayer | } |
1014 | b33c17e1 | j_mayer | } |
1015 | 12de9a39 | j_mayer | #endif
|
1016 | 9a64fbe4 | bellard | } else {
|
1017 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1018 | 4a057712 | j_mayer | if (loglevel != 0) |
1019 | 76a66253 | j_mayer | fprintf(logfile, "No access allowed\n");
|
1020 | 9a64fbe4 | bellard | #endif
|
1021 | 76a66253 | j_mayer | ret = -3;
|
1022 | 9a64fbe4 | bellard | } |
1023 | 9a64fbe4 | bellard | } else {
|
1024 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1025 | 4a057712 | j_mayer | if (loglevel != 0) |
1026 | 76a66253 | j_mayer | fprintf(logfile, "direct store...\n");
|
1027 | 9a64fbe4 | bellard | #endif
|
1028 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
|
1029 | 9a64fbe4 | bellard | switch (type) {
|
1030 | 9a64fbe4 | bellard | case ACCESS_INT:
|
1031 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
|
1032 | 9a64fbe4 | bellard | break;
|
1033 | 9a64fbe4 | bellard | case ACCESS_CODE:
|
1034 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1035 | 9a64fbe4 | bellard | return -4; |
1036 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1037 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1038 | 9a64fbe4 | bellard | return -4; |
1039 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1040 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
1041 | 9a64fbe4 | bellard | return -4; |
1042 | 9a64fbe4 | bellard | case ACCESS_CACHE:
|
1043 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
1044 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
|
1045 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
|
1046 | 9a64fbe4 | bellard | */
|
1047 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1048 | 9a64fbe4 | bellard | return 0; |
1049 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1050 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1051 | 9a64fbe4 | bellard | return -4; |
1052 | 9a64fbe4 | bellard | default:
|
1053 | 9a64fbe4 | bellard | if (logfile) {
|
1054 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
1055 | 9a64fbe4 | bellard | "address translation\n");
|
1056 | 9a64fbe4 | bellard | } |
1057 | 9a64fbe4 | bellard | return -4; |
1058 | 9a64fbe4 | bellard | } |
1059 | 76a66253 | j_mayer | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1060 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1061 | 9a64fbe4 | bellard | ret = 2;
|
1062 | 9a64fbe4 | bellard | } else {
|
1063 | 9a64fbe4 | bellard | ret = -2;
|
1064 | 9a64fbe4 | bellard | } |
1065 | 79aceca5 | bellard | } |
1066 | 9a64fbe4 | bellard | |
1067 | 9a64fbe4 | bellard | return ret;
|
1068 | 79aceca5 | bellard | } |
1069 | 79aceca5 | bellard | |
1070 | c294fc58 | j_mayer | /* Generic TLB check function for embedded PowerPC implementations */
|
1071 | a11b8151 | j_mayer | static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1072 | a11b8151 | j_mayer | target_phys_addr_t *raddrp, |
1073 | a11b8151 | j_mayer | target_ulong address, |
1074 | a11b8151 | j_mayer | uint32_t pid, int ext, int i) |
1075 | c294fc58 | j_mayer | { |
1076 | c294fc58 | j_mayer | target_ulong mask; |
1077 | c294fc58 | j_mayer | |
1078 | c294fc58 | j_mayer | /* Check valid flag */
|
1079 | c294fc58 | j_mayer | if (!(tlb->prot & PAGE_VALID)) {
|
1080 | c294fc58 | j_mayer | if (loglevel != 0) |
1081 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
1082 | c294fc58 | j_mayer | return -1; |
1083 | c294fc58 | j_mayer | } |
1084 | c294fc58 | j_mayer | mask = ~(tlb->size - 1);
|
1085 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1086 | c294fc58 | j_mayer | if (loglevel != 0) { |
1087 | c294fc58 | j_mayer | fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> " |
1088 | c294fc58 | j_mayer | ADDRX " " ADDRX " %d\n", |
1089 | 36081602 | j_mayer | __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
|
1090 | c294fc58 | j_mayer | } |
1091 | daf4f96e | j_mayer | #endif
|
1092 | c294fc58 | j_mayer | /* Check PID */
|
1093 | 36081602 | j_mayer | if (tlb->PID != 0 && tlb->PID != pid) |
1094 | c294fc58 | j_mayer | return -1; |
1095 | c294fc58 | j_mayer | /* Check effective address */
|
1096 | c294fc58 | j_mayer | if ((address & mask) != tlb->EPN)
|
1097 | c294fc58 | j_mayer | return -1; |
1098 | c294fc58 | j_mayer | *raddrp = (tlb->RPN & mask) | (address & ~mask); |
1099 | 9706285b | j_mayer | #if (TARGET_PHYS_ADDR_BITS >= 36) |
1100 | 36081602 | j_mayer | if (ext) {
|
1101 | 36081602 | j_mayer | /* Extend the physical address to 36 bits */
|
1102 | 36081602 | j_mayer | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
1103 | 36081602 | j_mayer | } |
1104 | 9706285b | j_mayer | #endif
|
1105 | c294fc58 | j_mayer | |
1106 | c294fc58 | j_mayer | return 0; |
1107 | c294fc58 | j_mayer | } |
1108 | c294fc58 | j_mayer | |
1109 | c294fc58 | j_mayer | /* Generic TLB search function for PowerPC embedded implementations */
|
1110 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
1111 | c294fc58 | j_mayer | { |
1112 | c294fc58 | j_mayer | ppcemb_tlb_t *tlb; |
1113 | c294fc58 | j_mayer | target_phys_addr_t raddr; |
1114 | c294fc58 | j_mayer | int i, ret;
|
1115 | c294fc58 | j_mayer | |
1116 | c294fc58 | j_mayer | /* Default return value is no match */
|
1117 | c294fc58 | j_mayer | ret = -1;
|
1118 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1119 | c294fc58 | j_mayer | tlb = &env->tlb[i].tlbe; |
1120 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
1121 | c294fc58 | j_mayer | ret = i; |
1122 | c294fc58 | j_mayer | break;
|
1123 | c294fc58 | j_mayer | } |
1124 | c294fc58 | j_mayer | } |
1125 | c294fc58 | j_mayer | |
1126 | c294fc58 | j_mayer | return ret;
|
1127 | c294fc58 | j_mayer | } |
1128 | c294fc58 | j_mayer | |
1129 | daf4f96e | j_mayer | /* Helpers specific to PowerPC 40x implementations */
|
1130 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) |
1131 | a750fc0b | j_mayer | { |
1132 | a750fc0b | j_mayer | ppcemb_tlb_t *tlb; |
1133 | a750fc0b | j_mayer | int i;
|
1134 | a750fc0b | j_mayer | |
1135 | a750fc0b | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1136 | a750fc0b | j_mayer | tlb = &env->tlb[i].tlbe; |
1137 | daf4f96e | j_mayer | tlb->prot &= ~PAGE_VALID; |
1138 | a750fc0b | j_mayer | } |
1139 | daf4f96e | j_mayer | tlb_flush(env, 1);
|
1140 | a750fc0b | j_mayer | } |
1141 | a750fc0b | j_mayer | |
1142 | a11b8151 | j_mayer | static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
1143 | a11b8151 | j_mayer | target_ulong eaddr, |
1144 | a11b8151 | j_mayer | uint32_t pid) |
1145 | 0a032cbe | j_mayer | { |
1146 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1147 | 0a032cbe | j_mayer | ppcemb_tlb_t *tlb; |
1148 | daf4f96e | j_mayer | target_phys_addr_t raddr; |
1149 | daf4f96e | j_mayer | target_ulong page, end; |
1150 | 0a032cbe | j_mayer | int i;
|
1151 | 0a032cbe | j_mayer | |
1152 | 0a032cbe | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1153 | 0a032cbe | j_mayer | tlb = &env->tlb[i].tlbe; |
1154 | daf4f96e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
1155 | 0a032cbe | j_mayer | end = tlb->EPN + tlb->size; |
1156 | 0a032cbe | j_mayer | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
1157 | 0a032cbe | j_mayer | tlb_flush_page(env, page); |
1158 | 0a032cbe | j_mayer | tlb->prot &= ~PAGE_VALID; |
1159 | daf4f96e | j_mayer | break;
|
1160 | 0a032cbe | j_mayer | } |
1161 | 0a032cbe | j_mayer | } |
1162 | daf4f96e | j_mayer | #else
|
1163 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1164 | daf4f96e | j_mayer | #endif
|
1165 | 0a032cbe | j_mayer | } |
1166 | 0a032cbe | j_mayer | |
1167 | 36081602 | j_mayer | int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1168 | e96efcfc | j_mayer | target_ulong address, int rw, int access_type) |
1169 | a8dea12f | j_mayer | { |
1170 | a8dea12f | j_mayer | ppcemb_tlb_t *tlb; |
1171 | a8dea12f | j_mayer | target_phys_addr_t raddr; |
1172 | 0411a972 | j_mayer | int i, ret, zsel, zpr, pr;
|
1173 | 3b46e624 | ths | |
1174 | c55e9aef | j_mayer | ret = -1;
|
1175 | c55e9aef | j_mayer | raddr = -1;
|
1176 | 0411a972 | j_mayer | pr = msr_pr; |
1177 | a8dea12f | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1178 | a8dea12f | j_mayer | tlb = &env->tlb[i].tlbe; |
1179 | 36081602 | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1180 | 36081602 | j_mayer | env->spr[SPR_40x_PID], 0, i) < 0) |
1181 | a8dea12f | j_mayer | continue;
|
1182 | a8dea12f | j_mayer | zsel = (tlb->attr >> 4) & 0xF; |
1183 | a8dea12f | j_mayer | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; |
1184 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1185 | 4a057712 | j_mayer | if (loglevel != 0) { |
1186 | a8dea12f | j_mayer | fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
1187 | a8dea12f | j_mayer | __func__, i, zsel, zpr, rw, tlb->attr); |
1188 | a8dea12f | j_mayer | } |
1189 | daf4f96e | j_mayer | #endif
|
1190 | b227a8e9 | j_mayer | /* Check execute enable bit */
|
1191 | b227a8e9 | j_mayer | switch (zpr) {
|
1192 | b227a8e9 | j_mayer | case 0x2: |
1193 | 0411a972 | j_mayer | if (pr != 0) |
1194 | b227a8e9 | j_mayer | goto check_perms;
|
1195 | b227a8e9 | j_mayer | /* No break here */
|
1196 | b227a8e9 | j_mayer | case 0x3: |
1197 | b227a8e9 | j_mayer | /* All accesses granted */
|
1198 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
1199 | b227a8e9 | j_mayer | ret = 0;
|
1200 | b227a8e9 | j_mayer | break;
|
1201 | b227a8e9 | j_mayer | case 0x0: |
1202 | 0411a972 | j_mayer | if (pr != 0) { |
1203 | b227a8e9 | j_mayer | ctx->prot = 0;
|
1204 | b227a8e9 | j_mayer | ret = -2;
|
1205 | a8dea12f | j_mayer | break;
|
1206 | a8dea12f | j_mayer | } |
1207 | b227a8e9 | j_mayer | /* No break here */
|
1208 | b227a8e9 | j_mayer | case 0x1: |
1209 | b227a8e9 | j_mayer | check_perms:
|
1210 | b227a8e9 | j_mayer | /* Check from TLB entry */
|
1211 | b227a8e9 | j_mayer | /* XXX: there is a problem here or in the TLB fill code... */
|
1212 | b227a8e9 | j_mayer | ctx->prot = tlb->prot; |
1213 | b227a8e9 | j_mayer | ctx->prot |= PAGE_EXEC; |
1214 | b227a8e9 | j_mayer | ret = check_prot(ctx->prot, rw, access_type); |
1215 | b227a8e9 | j_mayer | break;
|
1216 | a8dea12f | j_mayer | } |
1217 | a8dea12f | j_mayer | if (ret >= 0) { |
1218 | a8dea12f | j_mayer | ctx->raddr = raddr; |
1219 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1220 | 4a057712 | j_mayer | if (loglevel != 0) { |
1221 | a8dea12f | j_mayer | fprintf(logfile, "%s: access granted " ADDRX " => " REGX |
1222 | c55e9aef | j_mayer | " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
1223 | c55e9aef | j_mayer | ret); |
1224 | a8dea12f | j_mayer | } |
1225 | daf4f96e | j_mayer | #endif
|
1226 | c55e9aef | j_mayer | return 0; |
1227 | a8dea12f | j_mayer | } |
1228 | a8dea12f | j_mayer | } |
1229 | daf4f96e | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
1230 | 4a057712 | j_mayer | if (loglevel != 0) { |
1231 | c55e9aef | j_mayer | fprintf(logfile, "%s: access refused " ADDRX " => " REGX |
1232 | c55e9aef | j_mayer | " %d %d\n", __func__, address, raddr, ctx->prot,
|
1233 | c55e9aef | j_mayer | ret); |
1234 | c55e9aef | j_mayer | } |
1235 | daf4f96e | j_mayer | #endif
|
1236 | 3b46e624 | ths | |
1237 | a8dea12f | j_mayer | return ret;
|
1238 | a8dea12f | j_mayer | } |
1239 | a8dea12f | j_mayer | |
1240 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val)
|
1241 | c294fc58 | j_mayer | { |
1242 | c294fc58 | j_mayer | /* XXX: TO BE FIXED */
|
1243 | c294fc58 | j_mayer | if (val != 0x00000000) { |
1244 | c294fc58 | j_mayer | cpu_abort(env, "Little-endian regions are not supported by now\n");
|
1245 | c294fc58 | j_mayer | } |
1246 | c294fc58 | j_mayer | env->spr[SPR_405_SLER] = val; |
1247 | c294fc58 | j_mayer | } |
1248 | c294fc58 | j_mayer | |
1249 | 5eb7995e | j_mayer | int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
1250 | 5eb7995e | j_mayer | target_ulong address, int rw,
|
1251 | 5eb7995e | j_mayer | int access_type)
|
1252 | 5eb7995e | j_mayer | { |
1253 | 5eb7995e | j_mayer | ppcemb_tlb_t *tlb; |
1254 | 5eb7995e | j_mayer | target_phys_addr_t raddr; |
1255 | 5eb7995e | j_mayer | int i, prot, ret;
|
1256 | 5eb7995e | j_mayer | |
1257 | 5eb7995e | j_mayer | ret = -1;
|
1258 | 5eb7995e | j_mayer | raddr = -1;
|
1259 | 5eb7995e | j_mayer | for (i = 0; i < env->nb_tlb; i++) { |
1260 | 5eb7995e | j_mayer | tlb = &env->tlb[i].tlbe; |
1261 | 5eb7995e | j_mayer | if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
1262 | 5eb7995e | j_mayer | env->spr[SPR_BOOKE_PID], 1, i) < 0) |
1263 | 5eb7995e | j_mayer | continue;
|
1264 | 0411a972 | j_mayer | if (msr_pr != 0) |
1265 | 5eb7995e | j_mayer | prot = tlb->prot & 0xF;
|
1266 | 5eb7995e | j_mayer | else
|
1267 | 5eb7995e | j_mayer | prot = (tlb->prot >> 4) & 0xF; |
1268 | 5eb7995e | j_mayer | /* Check the address space */
|
1269 | 5eb7995e | j_mayer | if (access_type == ACCESS_CODE) {
|
1270 | d26bfc9a | j_mayer | if (msr_ir != (tlb->attr & 1)) |
1271 | 5eb7995e | j_mayer | continue;
|
1272 | 5eb7995e | j_mayer | ctx->prot = prot; |
1273 | 5eb7995e | j_mayer | if (prot & PAGE_EXEC) {
|
1274 | 5eb7995e | j_mayer | ret = 0;
|
1275 | 5eb7995e | j_mayer | break;
|
1276 | 5eb7995e | j_mayer | } |
1277 | 5eb7995e | j_mayer | ret = -3;
|
1278 | 5eb7995e | j_mayer | } else {
|
1279 | d26bfc9a | j_mayer | if (msr_dr != (tlb->attr & 1)) |
1280 | 5eb7995e | j_mayer | continue;
|
1281 | 5eb7995e | j_mayer | ctx->prot = prot; |
1282 | 5eb7995e | j_mayer | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
1283 | 5eb7995e | j_mayer | ret = 0;
|
1284 | 5eb7995e | j_mayer | break;
|
1285 | 5eb7995e | j_mayer | } |
1286 | 5eb7995e | j_mayer | ret = -2;
|
1287 | 5eb7995e | j_mayer | } |
1288 | 5eb7995e | j_mayer | } |
1289 | 5eb7995e | j_mayer | if (ret >= 0) |
1290 | 5eb7995e | j_mayer | ctx->raddr = raddr; |
1291 | 5eb7995e | j_mayer | |
1292 | 5eb7995e | j_mayer | return ret;
|
1293 | 5eb7995e | j_mayer | } |
1294 | 5eb7995e | j_mayer | |
1295 | a11b8151 | j_mayer | static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1296 | a11b8151 | j_mayer | target_ulong eaddr, int rw)
|
1297 | 76a66253 | j_mayer | { |
1298 | 76a66253 | j_mayer | int in_plb, ret;
|
1299 | 3b46e624 | ths | |
1300 | 76a66253 | j_mayer | ctx->raddr = eaddr; |
1301 | b227a8e9 | j_mayer | ctx->prot = PAGE_READ | PAGE_EXEC; |
1302 | 76a66253 | j_mayer | ret = 0;
|
1303 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1304 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1305 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1306 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1307 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1308 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1309 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1310 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1311 | caa4039c | j_mayer | break;
|
1312 | caa4039c | j_mayer | #if defined(TARGET_PPC64)
|
1313 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1314 | caa4039c | j_mayer | /* Real address are 60 bits long */
|
1315 | a750fc0b | j_mayer | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
1316 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1317 | caa4039c | j_mayer | break;
|
1318 | 9706285b | j_mayer | #endif
|
1319 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1320 | caa4039c | j_mayer | if (unlikely(msr_pe != 0)) { |
1321 | caa4039c | j_mayer | /* 403 family add some particular protections,
|
1322 | caa4039c | j_mayer | * using PBL/PBU registers for accesses with no translation.
|
1323 | caa4039c | j_mayer | */
|
1324 | caa4039c | j_mayer | in_plb = |
1325 | caa4039c | j_mayer | /* Check PLB validity */
|
1326 | caa4039c | j_mayer | (env->pb[0] < env->pb[1] && |
1327 | caa4039c | j_mayer | /* and address in plb area */
|
1328 | caa4039c | j_mayer | eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
1329 | caa4039c | j_mayer | (env->pb[2] < env->pb[3] && |
1330 | caa4039c | j_mayer | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
1331 | caa4039c | j_mayer | if (in_plb ^ msr_px) {
|
1332 | caa4039c | j_mayer | /* Access in protected area */
|
1333 | caa4039c | j_mayer | if (rw == 1) { |
1334 | caa4039c | j_mayer | /* Access is not allowed */
|
1335 | caa4039c | j_mayer | ret = -2;
|
1336 | caa4039c | j_mayer | } |
1337 | caa4039c | j_mayer | } else {
|
1338 | caa4039c | j_mayer | /* Read-write access is allowed */
|
1339 | caa4039c | j_mayer | ctx->prot |= PAGE_WRITE; |
1340 | 76a66253 | j_mayer | } |
1341 | 76a66253 | j_mayer | } |
1342 | e1833e1f | j_mayer | break;
|
1343 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1344 | caa4039c | j_mayer | /* XXX: TODO */
|
1345 | caa4039c | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1346 | caa4039c | j_mayer | break;
|
1347 | caa4039c | j_mayer | default:
|
1348 | caa4039c | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1349 | caa4039c | j_mayer | return -1; |
1350 | 76a66253 | j_mayer | } |
1351 | 76a66253 | j_mayer | |
1352 | 76a66253 | j_mayer | return ret;
|
1353 | 76a66253 | j_mayer | } |
1354 | 76a66253 | j_mayer | |
1355 | 76a66253 | j_mayer | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
1356 | 76a66253 | j_mayer | int rw, int access_type, int check_BATs) |
1357 | 9a64fbe4 | bellard | { |
1358 | 9a64fbe4 | bellard | int ret;
|
1359 | 0411a972 | j_mayer | |
1360 | 514fb8c1 | bellard | #if 0
|
1361 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1362 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
1363 | 9a64fbe4 | bellard | }
|
1364 | d9bce9d9 | j_mayer | #endif
|
1365 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1366 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
1367 | 9a64fbe4 | bellard | /* No address translation */
|
1368 | 76a66253 | j_mayer | ret = check_physical(env, ctx, eaddr, rw); |
1369 | 9a64fbe4 | bellard | } else {
|
1370 | c55e9aef | j_mayer | ret = -1;
|
1371 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1372 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1373 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1374 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1375 | a8dea12f | j_mayer | /* Try to find a BAT */
|
1376 | a8dea12f | j_mayer | if (check_BATs)
|
1377 | a8dea12f | j_mayer | ret = get_bat(env, ctx, eaddr, rw, access_type); |
1378 | c55e9aef | j_mayer | /* No break here */
|
1379 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1380 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1381 | c55e9aef | j_mayer | #endif
|
1382 | a8dea12f | j_mayer | if (ret < 0) { |
1383 | c55e9aef | j_mayer | /* We didn't match any BAT entry or don't have BATs */
|
1384 | a8dea12f | j_mayer | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1385 | a8dea12f | j_mayer | } |
1386 | a8dea12f | j_mayer | break;
|
1387 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1388 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1389 | 36081602 | j_mayer | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
1390 | a8dea12f | j_mayer | rw, access_type); |
1391 | a8dea12f | j_mayer | break;
|
1392 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1393 | 5eb7995e | j_mayer | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1394 | 5eb7995e | j_mayer | rw, access_type); |
1395 | 5eb7995e | j_mayer | break;
|
1396 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1397 | c55e9aef | j_mayer | /* XXX: TODO */
|
1398 | c55e9aef | j_mayer | cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
1399 | c55e9aef | j_mayer | return -1; |
1400 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1401 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 does not do any translation\n");
|
1402 | 2662a059 | j_mayer | return -1; |
1403 | c55e9aef | j_mayer | default:
|
1404 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1405 | a8dea12f | j_mayer | return -1; |
1406 | 9a64fbe4 | bellard | } |
1407 | 9a64fbe4 | bellard | } |
1408 | 514fb8c1 | bellard | #if 0
|
1409 | 4a057712 | j_mayer | if (loglevel != 0) {
|
1410 | 4a057712 | j_mayer | fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
1411 | c55e9aef | j_mayer | __func__, eaddr, ret, ctx->raddr);
|
1412 | a541f297 | bellard | }
|
1413 | 76a66253 | j_mayer | #endif
|
1414 | d9bce9d9 | j_mayer | |
1415 | 9a64fbe4 | bellard | return ret;
|
1416 | 9a64fbe4 | bellard | } |
1417 | 9a64fbe4 | bellard | |
1418 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
1419 | a6b025d3 | bellard | { |
1420 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1421 | a6b025d3 | bellard | |
1422 | 76a66253 | j_mayer | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0)) |
1423 | a6b025d3 | bellard | return -1; |
1424 | 76a66253 | j_mayer | |
1425 | 76a66253 | j_mayer | return ctx.raddr & TARGET_PAGE_MASK;
|
1426 | a6b025d3 | bellard | } |
1427 | 9a64fbe4 | bellard | |
1428 | 9a64fbe4 | bellard | /* Perform address translation */
|
1429 | e96efcfc | j_mayer | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
1430 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
1431 | 9a64fbe4 | bellard | { |
1432 | 76a66253 | j_mayer | mmu_ctx_t ctx; |
1433 | a541f297 | bellard | int access_type;
|
1434 | 9a64fbe4 | bellard | int ret = 0; |
1435 | d9bce9d9 | j_mayer | |
1436 | b769d8fe | bellard | if (rw == 2) { |
1437 | b769d8fe | bellard | /* code access */
|
1438 | b769d8fe | bellard | rw = 0;
|
1439 | b769d8fe | bellard | access_type = ACCESS_CODE; |
1440 | b769d8fe | bellard | } else {
|
1441 | b769d8fe | bellard | /* data access */
|
1442 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
1443 | b769d8fe | bellard | correctly */
|
1444 | b769d8fe | bellard | access_type = ACCESS_INT; |
1445 | b769d8fe | bellard | // access_type = env->access_type;
|
1446 | b769d8fe | bellard | } |
1447 | 76a66253 | j_mayer | ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
|
1448 | 9a64fbe4 | bellard | if (ret == 0) { |
1449 | b227a8e9 | j_mayer | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1450 | b227a8e9 | j_mayer | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
1451 | b227a8e9 | j_mayer | mmu_idx, is_softmmu); |
1452 | 9a64fbe4 | bellard | } else if (ret < 0) { |
1453 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
1454 | 4a057712 | j_mayer | if (loglevel != 0) |
1455 | 76a66253 | j_mayer | cpu_dump_state(env, logfile, fprintf, 0);
|
1456 | 9a64fbe4 | bellard | #endif
|
1457 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
1458 | 9a64fbe4 | bellard | switch (ret) {
|
1459 | 9a64fbe4 | bellard | case -1: |
1460 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1461 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1462 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1463 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1464 | 8f793433 | j_mayer | env->error_code = 1 << 18; |
1465 | 76a66253 | j_mayer | env->spr[SPR_IMISS] = address; |
1466 | 76a66253 | j_mayer | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
1467 | 76a66253 | j_mayer | goto tlb_miss;
|
1468 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1469 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_IFTLB; |
1470 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
1471 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1472 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1473 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ITLB; |
1474 | 8f793433 | j_mayer | env->error_code = 0;
|
1475 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1476 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1477 | c55e9aef | j_mayer | break;
|
1478 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1479 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1480 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1481 | c55e9aef | j_mayer | #endif
|
1482 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1483 | 8f793433 | j_mayer | env->error_code = 0x40000000;
|
1484 | 8f793433 | j_mayer | break;
|
1485 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1486 | c55e9aef | j_mayer | /* XXX: TODO */
|
1487 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1488 | c55e9aef | j_mayer | return -1; |
1489 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1490 | c55e9aef | j_mayer | /* XXX: TODO */
|
1491 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1492 | c55e9aef | j_mayer | return -1; |
1493 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1494 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1495 | 2662a059 | j_mayer | "exceptions\n");
|
1496 | 2662a059 | j_mayer | return -1; |
1497 | c55e9aef | j_mayer | default:
|
1498 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1499 | c55e9aef | j_mayer | return -1; |
1500 | 76a66253 | j_mayer | } |
1501 | 9a64fbe4 | bellard | break;
|
1502 | 9a64fbe4 | bellard | case -2: |
1503 | 9a64fbe4 | bellard | /* Access rights violation */
|
1504 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1505 | 8f793433 | j_mayer | env->error_code = 0x08000000;
|
1506 | 9a64fbe4 | bellard | break;
|
1507 | 9a64fbe4 | bellard | case -3: |
1508 | 76a66253 | j_mayer | /* No execute protection violation */
|
1509 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1510 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1511 | 9a64fbe4 | bellard | break;
|
1512 | 9a64fbe4 | bellard | case -4: |
1513 | 9a64fbe4 | bellard | /* Direct store exception */
|
1514 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
1515 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISI; |
1516 | 8f793433 | j_mayer | env->error_code = 0x10000000;
|
1517 | 2be0071f | bellard | break;
|
1518 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1519 | 2be0071f | bellard | case -5: |
1520 | 2be0071f | bellard | /* No match in segment table */
|
1521 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ISEG; |
1522 | 8f793433 | j_mayer | env->error_code = 0;
|
1523 | 9a64fbe4 | bellard | break;
|
1524 | e1833e1f | j_mayer | #endif
|
1525 | 9a64fbe4 | bellard | } |
1526 | 9a64fbe4 | bellard | } else {
|
1527 | 9a64fbe4 | bellard | switch (ret) {
|
1528 | 9a64fbe4 | bellard | case -1: |
1529 | 76a66253 | j_mayer | /* No matches in page tables or TLB */
|
1530 | a750fc0b | j_mayer | switch (env->mmu_model) {
|
1531 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1532 | 76a66253 | j_mayer | if (rw == 1) { |
1533 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1534 | 8f793433 | j_mayer | env->error_code = 1 << 16; |
1535 | 76a66253 | j_mayer | } else {
|
1536 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1537 | 8f793433 | j_mayer | env->error_code = 0;
|
1538 | 76a66253 | j_mayer | } |
1539 | 76a66253 | j_mayer | env->spr[SPR_DMISS] = address; |
1540 | 76a66253 | j_mayer | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
1541 | 76a66253 | j_mayer | tlb_miss:
|
1542 | 8f793433 | j_mayer | env->error_code |= ctx.key << 19;
|
1543 | 76a66253 | j_mayer | env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
1544 | 76a66253 | j_mayer | env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
1545 | 8f793433 | j_mayer | break;
|
1546 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1547 | 7dbe11ac | j_mayer | if (rw == 1) { |
1548 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSTLB; |
1549 | 7dbe11ac | j_mayer | } else {
|
1550 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DLTLB; |
1551 | 7dbe11ac | j_mayer | } |
1552 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
1553 | 7dbe11ac | j_mayer | /* Implement LRU algorithm */
|
1554 | 8f793433 | j_mayer | env->error_code = ctx.key << 19;
|
1555 | 7dbe11ac | j_mayer | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
1556 | 7dbe11ac | j_mayer | ((env->last_way + 1) & (env->nb_ways - 1)); |
1557 | 7dbe11ac | j_mayer | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
1558 | 7dbe11ac | j_mayer | break;
|
1559 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1560 | a750fc0b | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1561 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DTLB; |
1562 | 8f793433 | j_mayer | env->error_code = 0;
|
1563 | a8dea12f | j_mayer | env->spr[SPR_40x_DEAR] = address; |
1564 | a8dea12f | j_mayer | if (rw)
|
1565 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00800000;
|
1566 | a8dea12f | j_mayer | else
|
1567 | a8dea12f | j_mayer | env->spr[SPR_40x_ESR] = 0x00000000;
|
1568 | c55e9aef | j_mayer | break;
|
1569 | a750fc0b | j_mayer | case POWERPC_MMU_32B:
|
1570 | c55e9aef | j_mayer | #if defined(TARGET_PPC64)
|
1571 | a750fc0b | j_mayer | case POWERPC_MMU_64B:
|
1572 | c55e9aef | j_mayer | #endif
|
1573 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1574 | 8f793433 | j_mayer | env->error_code = 0;
|
1575 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1576 | 8f793433 | j_mayer | if (rw == 1) |
1577 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x42000000;
|
1578 | 8f793433 | j_mayer | else
|
1579 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x40000000;
|
1580 | 8f793433 | j_mayer | break;
|
1581 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE:
|
1582 | c55e9aef | j_mayer | /* XXX: TODO */
|
1583 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1584 | c55e9aef | j_mayer | return -1; |
1585 | a750fc0b | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1586 | c55e9aef | j_mayer | /* XXX: TODO */
|
1587 | c55e9aef | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1588 | c55e9aef | j_mayer | return -1; |
1589 | a750fc0b | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1590 | 2662a059 | j_mayer | cpu_abort(env, "PowerPC 401 should never raise any MMU "
|
1591 | 2662a059 | j_mayer | "exceptions\n");
|
1592 | 2662a059 | j_mayer | return -1; |
1593 | c55e9aef | j_mayer | default:
|
1594 | c55e9aef | j_mayer | cpu_abort(env, "Unknown or invalid MMU model\n");
|
1595 | c55e9aef | j_mayer | return -1; |
1596 | 76a66253 | j_mayer | } |
1597 | 9a64fbe4 | bellard | break;
|
1598 | 9a64fbe4 | bellard | case -2: |
1599 | 9a64fbe4 | bellard | /* Access rights violation */
|
1600 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1601 | 8f793433 | j_mayer | env->error_code = 0;
|
1602 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1603 | 8f793433 | j_mayer | if (rw == 1) |
1604 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x0A000000;
|
1605 | 8f793433 | j_mayer | else
|
1606 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x08000000;
|
1607 | 9a64fbe4 | bellard | break;
|
1608 | 9a64fbe4 | bellard | case -4: |
1609 | 9a64fbe4 | bellard | /* Direct store exception */
|
1610 | 9a64fbe4 | bellard | switch (access_type) {
|
1611 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
1612 | 9a64fbe4 | bellard | /* Floating point load/store */
|
1613 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_ALIGN; |
1614 | 8f793433 | j_mayer | env->error_code = POWERPC_EXCP_ALIGN_FP; |
1615 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1616 | 9a64fbe4 | bellard | break;
|
1617 | 9a64fbe4 | bellard | case ACCESS_RES:
|
1618 | 8f793433 | j_mayer | /* lwarx, ldarx or stwcx. */
|
1619 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1620 | 8f793433 | j_mayer | env->error_code = 0;
|
1621 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1622 | 8f793433 | j_mayer | if (rw == 1) |
1623 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06000000;
|
1624 | 8f793433 | j_mayer | else
|
1625 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04000000;
|
1626 | 9a64fbe4 | bellard | break;
|
1627 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
1628 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
1629 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSI; |
1630 | 8f793433 | j_mayer | env->error_code = 0;
|
1631 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1632 | 8f793433 | j_mayer | if (rw == 1) |
1633 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x06100000;
|
1634 | 8f793433 | j_mayer | else
|
1635 | 8f793433 | j_mayer | env->spr[SPR_DSISR] = 0x04100000;
|
1636 | 9a64fbe4 | bellard | break;
|
1637 | 9a64fbe4 | bellard | default:
|
1638 | 76a66253 | j_mayer | printf("DSI: invalid exception (%d)\n", ret);
|
1639 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_PROGRAM; |
1640 | 8f793433 | j_mayer | env->error_code = |
1641 | 8f793433 | j_mayer | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
1642 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1643 | 9a64fbe4 | bellard | break;
|
1644 | 9a64fbe4 | bellard | } |
1645 | fdabc366 | bellard | break;
|
1646 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
1647 | 2be0071f | bellard | case -5: |
1648 | 2be0071f | bellard | /* No match in segment table */
|
1649 | 8f793433 | j_mayer | env->exception_index = POWERPC_EXCP_DSEG; |
1650 | 8f793433 | j_mayer | env->error_code = 0;
|
1651 | 8f793433 | j_mayer | env->spr[SPR_DAR] = address; |
1652 | 2be0071f | bellard | break;
|
1653 | e1833e1f | j_mayer | #endif
|
1654 | 9a64fbe4 | bellard | } |
1655 | 9a64fbe4 | bellard | } |
1656 | 9a64fbe4 | bellard | #if 0
|
1657 | 8f793433 | j_mayer | printf("%s: set exception to %d %02x\n", __func__,
|
1658 | 8f793433 | j_mayer | env->exception, env->error_code);
|
1659 | 9a64fbe4 | bellard | #endif
|
1660 | 9a64fbe4 | bellard | ret = 1;
|
1661 | 9a64fbe4 | bellard | } |
1662 | 76a66253 | j_mayer | |
1663 | 9a64fbe4 | bellard | return ret;
|
1664 | 9a64fbe4 | bellard | } |
1665 | 9a64fbe4 | bellard | |
1666 | 3fc6c082 | bellard | /*****************************************************************************/
|
1667 | 3fc6c082 | bellard | /* BATs management */
|
1668 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1669 | b068d6a7 | j_mayer | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1670 | b068d6a7 | j_mayer | target_ulong BATu, |
1671 | b068d6a7 | j_mayer | target_ulong mask) |
1672 | 3fc6c082 | bellard | { |
1673 | 3fc6c082 | bellard | target_ulong base, end, page; |
1674 | 76a66253 | j_mayer | |
1675 | 3fc6c082 | bellard | base = BATu & ~0x0001FFFF;
|
1676 | 3fc6c082 | bellard | end = base + mask + 0x00020000;
|
1677 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1678 | 76a66253 | j_mayer | if (loglevel != 0) { |
1679 | 1b9eb036 | j_mayer | fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
1680 | 76a66253 | j_mayer | base, end, mask); |
1681 | 76a66253 | j_mayer | } |
1682 | 3fc6c082 | bellard | #endif
|
1683 | 3fc6c082 | bellard | for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
1684 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1685 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1686 | 3fc6c082 | bellard | if (loglevel != 0) |
1687 | 3fc6c082 | bellard | fprintf(logfile, "Flush done\n");
|
1688 | 3fc6c082 | bellard | #endif
|
1689 | 3fc6c082 | bellard | } |
1690 | 3fc6c082 | bellard | #endif
|
1691 | 3fc6c082 | bellard | |
1692 | b068d6a7 | j_mayer | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1693 | b068d6a7 | j_mayer | int ul, int nr, target_ulong value) |
1694 | 3fc6c082 | bellard | { |
1695 | 3fc6c082 | bellard | #if defined (DEBUG_BATS)
|
1696 | 3fc6c082 | bellard | if (loglevel != 0) { |
1697 | 1b9eb036 | j_mayer | fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
1698 | 1b9eb036 | j_mayer | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
1699 | 3fc6c082 | bellard | } |
1700 | 3fc6c082 | bellard | #endif
|
1701 | 3fc6c082 | bellard | } |
1702 | 3fc6c082 | bellard | |
1703 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr)
|
1704 | 3fc6c082 | bellard | { |
1705 | 3fc6c082 | bellard | return env->IBAT[0][nr]; |
1706 | 3fc6c082 | bellard | } |
1707 | 3fc6c082 | bellard | |
1708 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr)
|
1709 | 3fc6c082 | bellard | { |
1710 | 3fc6c082 | bellard | return env->IBAT[1][nr]; |
1711 | 3fc6c082 | bellard | } |
1712 | 3fc6c082 | bellard | |
1713 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
1714 | 3fc6c082 | bellard | { |
1715 | 3fc6c082 | bellard | target_ulong mask; |
1716 | 3fc6c082 | bellard | |
1717 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 0, nr, value); |
1718 | 3fc6c082 | bellard | if (env->IBAT[0][nr] != value) { |
1719 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1720 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1721 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1722 | 3fc6c082 | bellard | #endif
|
1723 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1724 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1725 | 3fc6c082 | bellard | */
|
1726 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1727 | 3fc6c082 | bellard | env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
1728 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1729 | 3fc6c082 | bellard | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
1730 | 3fc6c082 | bellard | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
1731 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1732 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
1733 | 76a66253 | j_mayer | #else
|
1734 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1735 | 3fc6c082 | bellard | #endif
|
1736 | 3fc6c082 | bellard | } |
1737 | 3fc6c082 | bellard | } |
1738 | 3fc6c082 | bellard | |
1739 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
1740 | 3fc6c082 | bellard | { |
1741 | 3fc6c082 | bellard | dump_store_bat(env, 'I', 1, nr, value); |
1742 | 3fc6c082 | bellard | env->IBAT[1][nr] = value;
|
1743 | 3fc6c082 | bellard | } |
1744 | 3fc6c082 | bellard | |
1745 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr)
|
1746 | 3fc6c082 | bellard | { |
1747 | 3fc6c082 | bellard | return env->DBAT[0][nr]; |
1748 | 3fc6c082 | bellard | } |
1749 | 3fc6c082 | bellard | |
1750 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr)
|
1751 | 3fc6c082 | bellard | { |
1752 | 3fc6c082 | bellard | return env->DBAT[1][nr]; |
1753 | 3fc6c082 | bellard | } |
1754 | 3fc6c082 | bellard | |
1755 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
1756 | 3fc6c082 | bellard | { |
1757 | 3fc6c082 | bellard | target_ulong mask; |
1758 | 3fc6c082 | bellard | |
1759 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 0, nr, value); |
1760 | 3fc6c082 | bellard | if (env->DBAT[0][nr] != value) { |
1761 | 3fc6c082 | bellard | /* When storing valid upper BAT, mask BEPI and BRPN
|
1762 | 3fc6c082 | bellard | * and invalidate all TLBs covered by this BAT
|
1763 | 3fc6c082 | bellard | */
|
1764 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1765 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1766 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1767 | 3fc6c082 | bellard | #endif
|
1768 | 3fc6c082 | bellard | mask = (value << 15) & 0x0FFE0000UL; |
1769 | 3fc6c082 | bellard | env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
1770 | 3fc6c082 | bellard | (value & ~0x0001FFFFUL & ~mask);
|
1771 | 3fc6c082 | bellard | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
1772 | 3fc6c082 | bellard | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
1773 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS)
|
1774 | 3fc6c082 | bellard | do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
1775 | 3fc6c082 | bellard | #else
|
1776 | 3fc6c082 | bellard | tlb_flush(env, 1);
|
1777 | 3fc6c082 | bellard | #endif
|
1778 | 3fc6c082 | bellard | } |
1779 | 3fc6c082 | bellard | } |
1780 | 3fc6c082 | bellard | |
1781 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
1782 | 3fc6c082 | bellard | { |
1783 | 3fc6c082 | bellard | dump_store_bat(env, 'D', 1, nr, value); |
1784 | 3fc6c082 | bellard | env->DBAT[1][nr] = value;
|
1785 | 3fc6c082 | bellard | } |
1786 | 3fc6c082 | bellard | |
1787 | 0a032cbe | j_mayer | /*****************************************************************************/
|
1788 | 0a032cbe | j_mayer | /* TLB management */
|
1789 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env)
|
1790 | 0a032cbe | j_mayer | { |
1791 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1792 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1793 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1794 | 0a032cbe | j_mayer | ppc6xx_tlb_invalidate_all(env); |
1795 | daf4f96e | j_mayer | break;
|
1796 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1797 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1798 | 0a032cbe | j_mayer | ppc4xx_tlb_invalidate_all(env); |
1799 | daf4f96e | j_mayer | break;
|
1800 | 7dbe11ac | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1801 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1802 | 7dbe11ac | j_mayer | break;
|
1803 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1804 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1805 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1806 | 7dbe11ac | j_mayer | break;
|
1807 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1808 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1809 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1810 | 7dbe11ac | j_mayer | break;
|
1811 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1812 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1813 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1814 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1815 | 0a032cbe | j_mayer | tlb_flush(env, 1);
|
1816 | daf4f96e | j_mayer | break;
|
1817 | 00af685f | j_mayer | default:
|
1818 | 00af685f | j_mayer | /* XXX: TODO */
|
1819 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1820 | 00af685f | j_mayer | break;
|
1821 | 0a032cbe | j_mayer | } |
1822 | 0a032cbe | j_mayer | } |
1823 | 0a032cbe | j_mayer | |
1824 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
1825 | daf4f96e | j_mayer | { |
1826 | daf4f96e | j_mayer | #if !defined(FLUSH_ALL_TLBS)
|
1827 | daf4f96e | j_mayer | addr &= TARGET_PAGE_MASK; |
1828 | daf4f96e | j_mayer | switch (env->mmu_model) {
|
1829 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_6xx:
|
1830 | 7dbe11ac | j_mayer | case POWERPC_MMU_SOFT_74xx:
|
1831 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
1832 | daf4f96e | j_mayer | if (env->id_tlbs == 1) |
1833 | daf4f96e | j_mayer | ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
1834 | daf4f96e | j_mayer | break;
|
1835 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx:
|
1836 | daf4f96e | j_mayer | case POWERPC_MMU_SOFT_4xx_Z:
|
1837 | daf4f96e | j_mayer | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
1838 | daf4f96e | j_mayer | break;
|
1839 | 7dbe11ac | j_mayer | case POWERPC_MMU_REAL_4xx:
|
1840 | 7dbe11ac | j_mayer | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
1841 | 7dbe11ac | j_mayer | break;
|
1842 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE:
|
1843 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1844 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1845 | 7dbe11ac | j_mayer | break;
|
1846 | 7dbe11ac | j_mayer | case POWERPC_MMU_BOOKE_FSL:
|
1847 | 7dbe11ac | j_mayer | /* XXX: TODO */
|
1848 | 7dbe11ac | j_mayer | cpu_abort(env, "MMU model not implemented\n");
|
1849 | 7dbe11ac | j_mayer | break;
|
1850 | 7dbe11ac | j_mayer | case POWERPC_MMU_32B:
|
1851 | daf4f96e | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1852 | daf4f96e | j_mayer | addr &= ~((target_ulong)-1 << 28); |
1853 | daf4f96e | j_mayer | /* XXX: this case should be optimized,
|
1854 | daf4f96e | j_mayer | * giving a mask to tlb_flush_page
|
1855 | daf4f96e | j_mayer | */
|
1856 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x0 << 28)); |
1857 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x1 << 28)); |
1858 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x2 << 28)); |
1859 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x3 << 28)); |
1860 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x4 << 28)); |
1861 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x5 << 28)); |
1862 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x6 << 28)); |
1863 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x7 << 28)); |
1864 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x8 << 28)); |
1865 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0x9 << 28)); |
1866 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xA << 28)); |
1867 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xB << 28)); |
1868 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xC << 28)); |
1869 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xD << 28)); |
1870 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xE << 28)); |
1871 | daf4f96e | j_mayer | tlb_flush_page(env, addr | (0xF << 28)); |
1872 | 7dbe11ac | j_mayer | break;
|
1873 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1874 | 7dbe11ac | j_mayer | case POWERPC_MMU_64B:
|
1875 | 7dbe11ac | j_mayer | /* tlbie invalidate TLBs for all segments */
|
1876 | 7dbe11ac | j_mayer | /* XXX: given the fact that there are too many segments to invalidate,
|
1877 | 00af685f | j_mayer | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
1878 | 7dbe11ac | j_mayer | * we just invalidate all TLBs
|
1879 | 7dbe11ac | j_mayer | */
|
1880 | 7dbe11ac | j_mayer | tlb_flush(env, 1);
|
1881 | 7dbe11ac | j_mayer | break;
|
1882 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
1883 | 00af685f | j_mayer | default:
|
1884 | 00af685f | j_mayer | /* XXX: TODO */
|
1885 | 12de9a39 | j_mayer | cpu_abort(env, "Unknown MMU model\n");
|
1886 | 00af685f | j_mayer | break;
|
1887 | daf4f96e | j_mayer | } |
1888 | daf4f96e | j_mayer | #else
|
1889 | daf4f96e | j_mayer | ppc_tlb_invalidate_all(env); |
1890 | daf4f96e | j_mayer | #endif
|
1891 | daf4f96e | j_mayer | } |
1892 | daf4f96e | j_mayer | |
1893 | 3fc6c082 | bellard | /*****************************************************************************/
|
1894 | 3fc6c082 | bellard | /* Special registers manipulation */
|
1895 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1896 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env) |
1897 | d9bce9d9 | j_mayer | { |
1898 | d9bce9d9 | j_mayer | return env->asr;
|
1899 | d9bce9d9 | j_mayer | } |
1900 | d9bce9d9 | j_mayer | |
1901 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
1902 | d9bce9d9 | j_mayer | { |
1903 | d9bce9d9 | j_mayer | if (env->asr != value) {
|
1904 | d9bce9d9 | j_mayer | env->asr = value; |
1905 | d9bce9d9 | j_mayer | tlb_flush(env, 1);
|
1906 | d9bce9d9 | j_mayer | } |
1907 | d9bce9d9 | j_mayer | } |
1908 | d9bce9d9 | j_mayer | #endif
|
1909 | d9bce9d9 | j_mayer | |
1910 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env) |
1911 | 3fc6c082 | bellard | { |
1912 | 3fc6c082 | bellard | return env->sdr1;
|
1913 | 3fc6c082 | bellard | } |
1914 | 3fc6c082 | bellard | |
1915 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value)
|
1916 | 3fc6c082 | bellard | { |
1917 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
1918 | 3fc6c082 | bellard | if (loglevel != 0) { |
1919 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
1920 | 3fc6c082 | bellard | } |
1921 | 3fc6c082 | bellard | #endif
|
1922 | 3fc6c082 | bellard | if (env->sdr1 != value) {
|
1923 | 12de9a39 | j_mayer | /* XXX: for PowerPC 64, should check that the HTABSIZE value
|
1924 | 12de9a39 | j_mayer | * is <= 28
|
1925 | 12de9a39 | j_mayer | */
|
1926 | 3fc6c082 | bellard | env->sdr1 = value; |
1927 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1928 | 3fc6c082 | bellard | } |
1929 | 3fc6c082 | bellard | } |
1930 | 3fc6c082 | bellard | |
1931 | 12de9a39 | j_mayer | #if 0 // Unused
|
1932 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum)
|
1933 | 3fc6c082 | bellard | {
|
1934 | 3fc6c082 | bellard | return env->sr[srnum];
|
1935 | 3fc6c082 | bellard | }
|
1936 | 12de9a39 | j_mayer | #endif
|
1937 | 3fc6c082 | bellard | |
1938 | 3fc6c082 | bellard | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
1939 | 3fc6c082 | bellard | { |
1940 | 3fc6c082 | bellard | #if defined (DEBUG_MMU)
|
1941 | 3fc6c082 | bellard | if (loglevel != 0) { |
1942 | 1b9eb036 | j_mayer | fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
1943 | 1b9eb036 | j_mayer | __func__, srnum, value, env->sr[srnum]); |
1944 | 3fc6c082 | bellard | } |
1945 | 3fc6c082 | bellard | #endif
|
1946 | 3fc6c082 | bellard | if (env->sr[srnum] != value) {
|
1947 | 3fc6c082 | bellard | env->sr[srnum] = value; |
1948 | 3fc6c082 | bellard | #if !defined(FLUSH_ALL_TLBS) && 0 |
1949 | 3fc6c082 | bellard | { |
1950 | 3fc6c082 | bellard | target_ulong page, end; |
1951 | 3fc6c082 | bellard | /* Invalidate 256 MB of virtual memory */
|
1952 | 3fc6c082 | bellard | page = (16 << 20) * srnum; |
1953 | 3fc6c082 | bellard | end = page + (16 << 20); |
1954 | 3fc6c082 | bellard | for (; page != end; page += TARGET_PAGE_SIZE)
|
1955 | 3fc6c082 | bellard | tlb_flush_page(env, page); |
1956 | 3fc6c082 | bellard | } |
1957 | 3fc6c082 | bellard | #else
|
1958 | 76a66253 | j_mayer | tlb_flush(env, 1);
|
1959 | 3fc6c082 | bellard | #endif
|
1960 | 3fc6c082 | bellard | } |
1961 | 3fc6c082 | bellard | } |
1962 | 76a66253 | j_mayer | #endif /* !defined (CONFIG_USER_ONLY) */ |
1963 | 3fc6c082 | bellard | |
1964 | bfa1e5cf | j_mayer | target_ulong ppc_load_xer (CPUPPCState *env) |
1965 | 79aceca5 | bellard | { |
1966 | 0411a972 | j_mayer | return hreg_load_xer(env);
|
1967 | 79aceca5 | bellard | } |
1968 | 79aceca5 | bellard | |
1969 | bfa1e5cf | j_mayer | void ppc_store_xer (CPUPPCState *env, target_ulong value)
|
1970 | 79aceca5 | bellard | { |
1971 | 0411a972 | j_mayer | hreg_store_xer(env, value); |
1972 | 79aceca5 | bellard | } |
1973 | 79aceca5 | bellard | |
1974 | 76a66253 | j_mayer | /* GDBstub can read and write MSR... */
|
1975 | 0411a972 | j_mayer | void ppc_store_msr (CPUPPCState *env, target_ulong value)
|
1976 | 3fc6c082 | bellard | { |
1977 | 0411a972 | j_mayer | hreg_store_msr(env, value); |
1978 | 3fc6c082 | bellard | } |
1979 | 3fc6c082 | bellard | |
1980 | 3fc6c082 | bellard | /*****************************************************************************/
|
1981 | 3fc6c082 | bellard | /* Exception processing */
|
1982 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
1983 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
1984 | 79aceca5 | bellard | { |
1985 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
1986 | e1833e1f | j_mayer | env->error_code = 0;
|
1987 | 18fba28c | bellard | } |
1988 | 47103572 | j_mayer | |
1989 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUState *env)
|
1990 | 47103572 | j_mayer | { |
1991 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
1992 | e1833e1f | j_mayer | env->error_code = 0;
|
1993 | 47103572 | j_mayer | } |
1994 | 76a66253 | j_mayer | #else /* defined (CONFIG_USER_ONLY) */ |
1995 | a11b8151 | j_mayer | static always_inline void dump_syscall (CPUState *env) |
1996 | d094807b | bellard | { |
1997 | d9bce9d9 | j_mayer | fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
1998 | 1b9eb036 | j_mayer | " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
1999 | d094807b | bellard | env->gpr[0], env->gpr[3], env->gpr[4], |
2000 | d094807b | bellard | env->gpr[5], env->gpr[6], env->nip); |
2001 | d094807b | bellard | } |
2002 | d094807b | bellard | |
2003 | e1833e1f | j_mayer | /* Note that this function should be greatly optimized
|
2004 | e1833e1f | j_mayer | * when called with a constant excp, from ppc_hw_interrupt
|
2005 | e1833e1f | j_mayer | */
|
2006 | e1833e1f | j_mayer | static always_inline void powerpc_excp (CPUState *env, |
2007 | e1833e1f | j_mayer | int excp_model, int excp) |
2008 | 18fba28c | bellard | { |
2009 | 0411a972 | j_mayer | target_ulong msr, new_msr, vector; |
2010 | e1833e1f | j_mayer | int srr0, srr1, asrr0, asrr1;
|
2011 | f9fdea6b | j_mayer | #if defined(TARGET_PPC64H)
|
2012 | f9fdea6b | j_mayer | int lpes0, lpes1, lev;
|
2013 | f9fdea6b | j_mayer | |
2014 | f9fdea6b | j_mayer | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; |
2015 | f9fdea6b | j_mayer | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; |
2016 | f9fdea6b | j_mayer | #endif
|
2017 | 79aceca5 | bellard | |
2018 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2019 | 1b9eb036 | j_mayer | fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
2020 | 1b9eb036 | j_mayer | env->nip, excp, env->error_code); |
2021 | b769d8fe | bellard | } |
2022 | 0411a972 | j_mayer | msr = env->msr; |
2023 | 0411a972 | j_mayer | new_msr = msr; |
2024 | e1833e1f | j_mayer | srr0 = SPR_SRR0; |
2025 | e1833e1f | j_mayer | srr1 = SPR_SRR1; |
2026 | e1833e1f | j_mayer | asrr0 = -1;
|
2027 | e1833e1f | j_mayer | asrr1 = -1;
|
2028 | e1833e1f | j_mayer | msr &= ~((target_ulong)0x783F0000);
|
2029 | 9a64fbe4 | bellard | switch (excp) {
|
2030 | e1833e1f | j_mayer | case POWERPC_EXCP_NONE:
|
2031 | e1833e1f | j_mayer | /* Should never happen */
|
2032 | e1833e1f | j_mayer | return;
|
2033 | e1833e1f | j_mayer | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
2034 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2035 | e1833e1f | j_mayer | switch (excp_model) {
|
2036 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2037 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2038 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2039 | c62db105 | j_mayer | break;
|
2040 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2041 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2042 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2043 | c62db105 | j_mayer | break;
|
2044 | e1833e1f | j_mayer | case POWERPC_EXCP_G2:
|
2045 | c62db105 | j_mayer | break;
|
2046 | e1833e1f | j_mayer | default:
|
2047 | e1833e1f | j_mayer | goto excp_invalid;
|
2048 | 2be0071f | bellard | } |
2049 | 9a64fbe4 | bellard | goto store_next;
|
2050 | e1833e1f | j_mayer | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2051 | e1833e1f | j_mayer | if (msr_me == 0) { |
2052 | e63ecc6f | j_mayer | /* Machine check exception is not enabled.
|
2053 | e63ecc6f | j_mayer | * Enter checkstop state.
|
2054 | e63ecc6f | j_mayer | */
|
2055 | e63ecc6f | j_mayer | if (loglevel != 0) { |
2056 | e63ecc6f | j_mayer | fprintf(logfile, "Machine check while not allowed. "
|
2057 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2058 | e63ecc6f | j_mayer | } else {
|
2059 | e63ecc6f | j_mayer | fprintf(stderr, "Machine check while not allowed. "
|
2060 | e63ecc6f | j_mayer | "Entering checkstop state\n");
|
2061 | e63ecc6f | j_mayer | } |
2062 | e63ecc6f | j_mayer | env->halted = 1;
|
2063 | e63ecc6f | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
2064 | e1833e1f | j_mayer | } |
2065 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2066 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_ME);
|
2067 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2068 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2069 | e1833e1f | j_mayer | #endif
|
2070 | e1833e1f | j_mayer | /* XXX: should also have something loaded in DAR / DSISR */
|
2071 | e1833e1f | j_mayer | switch (excp_model) {
|
2072 | a750fc0b | j_mayer | case POWERPC_EXCP_40x:
|
2073 | e1833e1f | j_mayer | srr0 = SPR_40x_SRR2; |
2074 | e1833e1f | j_mayer | srr1 = SPR_40x_SRR3; |
2075 | c62db105 | j_mayer | break;
|
2076 | a750fc0b | j_mayer | case POWERPC_EXCP_BOOKE:
|
2077 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_MCSRR0; |
2078 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_MCSRR1; |
2079 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2080 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2081 | c62db105 | j_mayer | break;
|
2082 | c62db105 | j_mayer | default:
|
2083 | c62db105 | j_mayer | break;
|
2084 | 2be0071f | bellard | } |
2085 | e1833e1f | j_mayer | goto store_next;
|
2086 | e1833e1f | j_mayer | case POWERPC_EXCP_DSI: /* Data storage exception */ |
2087 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2088 | 4a057712 | j_mayer | if (loglevel != 0) { |
2089 | 1b9eb036 | j_mayer | fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
2090 | 1b9eb036 | j_mayer | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
2091 | 76a66253 | j_mayer | } |
2092 | a541f297 | bellard | #endif
|
2093 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2094 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2095 | e1833e1f | j_mayer | if (lpes1 == 0) |
2096 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2097 | e1833e1f | j_mayer | #endif
|
2098 | a541f297 | bellard | goto store_next;
|
2099 | e1833e1f | j_mayer | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
2100 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2101 | 76a66253 | j_mayer | if (loglevel != 0) { |
2102 | 1b9eb036 | j_mayer | fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
2103 | 1b9eb036 | j_mayer | "\n", msr, env->nip);
|
2104 | 76a66253 | j_mayer | } |
2105 | a541f297 | bellard | #endif
|
2106 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2107 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2108 | e1833e1f | j_mayer | if (lpes1 == 0) |
2109 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2110 | e1833e1f | j_mayer | #endif
|
2111 | e1833e1f | j_mayer | msr |= env->error_code; |
2112 | 9a64fbe4 | bellard | goto store_next;
|
2113 | e1833e1f | j_mayer | case POWERPC_EXCP_EXTERNAL: /* External input */ |
2114 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2115 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2116 | e1833e1f | j_mayer | if (lpes0 == 1) |
2117 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2118 | e1833e1f | j_mayer | #endif
|
2119 | 9a64fbe4 | bellard | goto store_next;
|
2120 | e1833e1f | j_mayer | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
2121 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2122 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2123 | e1833e1f | j_mayer | if (lpes1 == 0) |
2124 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2125 | e1833e1f | j_mayer | #endif
|
2126 | e1833e1f | j_mayer | /* XXX: this is false */
|
2127 | e1833e1f | j_mayer | /* Get rS/rD and rA from faulting opcode */
|
2128 | e1833e1f | j_mayer | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
2129 | 9a64fbe4 | bellard | goto store_current;
|
2130 | e1833e1f | j_mayer | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
2131 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
2132 | e1833e1f | j_mayer | case POWERPC_EXCP_FP:
|
2133 | e1833e1f | j_mayer | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
2134 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
2135 | 4a057712 | j_mayer | if (loglevel != 0) { |
2136 | a496775f | j_mayer | fprintf(logfile, "Ignore floating point exception\n");
|
2137 | a496775f | j_mayer | } |
2138 | 9a64fbe4 | bellard | #endif
|
2139 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2140 | 7c58044c | j_mayer | env->error_code = 0;
|
2141 | 9a64fbe4 | bellard | return;
|
2142 | 76a66253 | j_mayer | } |
2143 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2144 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2145 | e1833e1f | j_mayer | if (lpes1 == 0) |
2146 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2147 | e1833e1f | j_mayer | #endif
|
2148 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
2149 | 5b52b991 | j_mayer | if (msr_fe0 == msr_fe1)
|
2150 | 5b52b991 | j_mayer | goto store_next;
|
2151 | 5b52b991 | j_mayer | msr |= 0x00010000;
|
2152 | 76a66253 | j_mayer | break;
|
2153 | e1833e1f | j_mayer | case POWERPC_EXCP_INVAL:
|
2154 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2155 | 4a057712 | j_mayer | if (loglevel != 0) { |
2156 | a496775f | j_mayer | fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n", |
2157 | a496775f | j_mayer | env->nip); |
2158 | a496775f | j_mayer | } |
2159 | a496775f | j_mayer | #endif
|
2160 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2161 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2162 | e1833e1f | j_mayer | if (lpes1 == 0) |
2163 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2164 | e1833e1f | j_mayer | #endif
|
2165 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
2166 | 76a66253 | j_mayer | break;
|
2167 | e1833e1f | j_mayer | case POWERPC_EXCP_PRIV:
|
2168 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2169 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2170 | e1833e1f | j_mayer | if (lpes1 == 0) |
2171 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2172 | e1833e1f | j_mayer | #endif
|
2173 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
2174 | 76a66253 | j_mayer | break;
|
2175 | e1833e1f | j_mayer | case POWERPC_EXCP_TRAP:
|
2176 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2177 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2178 | e1833e1f | j_mayer | if (lpes1 == 0) |
2179 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2180 | e1833e1f | j_mayer | #endif
|
2181 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
2182 | 9a64fbe4 | bellard | break;
|
2183 | 9a64fbe4 | bellard | default:
|
2184 | 9a64fbe4 | bellard | /* Should never occur */
|
2185 | e1833e1f | j_mayer | cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
2186 | e1833e1f | j_mayer | env->error_code); |
2187 | 76a66253 | j_mayer | break;
|
2188 | 76a66253 | j_mayer | } |
2189 | 5b52b991 | j_mayer | goto store_current;
|
2190 | e1833e1f | j_mayer | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
2191 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2192 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2193 | e1833e1f | j_mayer | if (lpes1 == 0) |
2194 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2195 | e1833e1f | j_mayer | #endif
|
2196 | e1833e1f | j_mayer | goto store_current;
|
2197 | e1833e1f | j_mayer | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
2198 | d094807b | bellard | /* NOTE: this is a temporary hack to support graphics OSI
|
2199 | d094807b | bellard | calls from the MOL driver */
|
2200 | e1833e1f | j_mayer | /* XXX: To be removed */
|
2201 | d094807b | bellard | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2202 | d094807b | bellard | env->osi_call) { |
2203 | 7c58044c | j_mayer | if (env->osi_call(env) != 0) { |
2204 | 7c58044c | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2205 | 7c58044c | j_mayer | env->error_code = 0;
|
2206 | d094807b | bellard | return;
|
2207 | 7c58044c | j_mayer | } |
2208 | d094807b | bellard | } |
2209 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
2210 | d094807b | bellard | dump_syscall(env); |
2211 | b769d8fe | bellard | } |
2212 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2213 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2214 | f9fdea6b | j_mayer | lev = env->error_code; |
2215 | e1833e1f | j_mayer | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
2216 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2217 | e1833e1f | j_mayer | #endif
|
2218 | e1833e1f | j_mayer | goto store_next;
|
2219 | e1833e1f | j_mayer | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
2220 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2221 | e1833e1f | j_mayer | goto store_current;
|
2222 | e1833e1f | j_mayer | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
2223 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2224 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2225 | e1833e1f | j_mayer | if (lpes1 == 0) |
2226 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2227 | e1833e1f | j_mayer | #endif
|
2228 | e1833e1f | j_mayer | goto store_next;
|
2229 | e1833e1f | j_mayer | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
2230 | e1833e1f | j_mayer | /* FIT on 4xx */
|
2231 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2232 | e1833e1f | j_mayer | if (loglevel != 0) |
2233 | e1833e1f | j_mayer | fprintf(logfile, "FIT exception\n");
|
2234 | e1833e1f | j_mayer | #endif
|
2235 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2236 | 9a64fbe4 | bellard | goto store_next;
|
2237 | e1833e1f | j_mayer | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
2238 | e1833e1f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2239 | e1833e1f | j_mayer | if (loglevel != 0) |
2240 | e1833e1f | j_mayer | fprintf(logfile, "WDT exception\n");
|
2241 | e1833e1f | j_mayer | #endif
|
2242 | e1833e1f | j_mayer | switch (excp_model) {
|
2243 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2244 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2245 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2246 | e1833e1f | j_mayer | break;
|
2247 | e1833e1f | j_mayer | default:
|
2248 | e1833e1f | j_mayer | break;
|
2249 | e1833e1f | j_mayer | } |
2250 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2251 | 2be0071f | bellard | goto store_next;
|
2252 | e1833e1f | j_mayer | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
2253 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2254 | e1833e1f | j_mayer | goto store_next;
|
2255 | e1833e1f | j_mayer | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
2256 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2257 | e1833e1f | j_mayer | goto store_next;
|
2258 | e1833e1f | j_mayer | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
2259 | e1833e1f | j_mayer | switch (excp_model) {
|
2260 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2261 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_DSRR0; |
2262 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_DSRR1; |
2263 | e1833e1f | j_mayer | asrr0 = SPR_BOOKE_CSRR0; |
2264 | e1833e1f | j_mayer | asrr1 = SPR_BOOKE_CSRR1; |
2265 | e1833e1f | j_mayer | break;
|
2266 | e1833e1f | j_mayer | default:
|
2267 | e1833e1f | j_mayer | break;
|
2268 | e1833e1f | j_mayer | } |
2269 | 2be0071f | bellard | /* XXX: TODO */
|
2270 | e1833e1f | j_mayer | cpu_abort(env, "Debug exception is not implemented yet !\n");
|
2271 | 2be0071f | bellard | goto store_next;
|
2272 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2273 | e1833e1f | j_mayer | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
2274 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2275 | e1833e1f | j_mayer | goto store_current;
|
2276 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
2277 | 2be0071f | bellard | /* XXX: TODO */
|
2278 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point data exception "
|
2279 | 2be0071f | bellard | "is not implemented yet !\n");
|
2280 | 2be0071f | bellard | goto store_next;
|
2281 | e1833e1f | j_mayer | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2282 | 2be0071f | bellard | /* XXX: TODO */
|
2283 | e1833e1f | j_mayer | cpu_abort(env, "Embedded floating point round exception "
|
2284 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2285 | 9a64fbe4 | bellard | goto store_next;
|
2286 | e1833e1f | j_mayer | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
2287 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2288 | 2be0071f | bellard | /* XXX: TODO */
|
2289 | 2be0071f | bellard | cpu_abort(env, |
2290 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2291 | 9a64fbe4 | bellard | goto store_next;
|
2292 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
2293 | 76a66253 | j_mayer | /* XXX: TODO */
|
2294 | e1833e1f | j_mayer | cpu_abort(env, |
2295 | e1833e1f | j_mayer | "Embedded doorbell interrupt is not implemented yet !\n");
|
2296 | 2be0071f | bellard | goto store_next;
|
2297 | e1833e1f | j_mayer | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2298 | e1833e1f | j_mayer | switch (excp_model) {
|
2299 | e1833e1f | j_mayer | case POWERPC_EXCP_BOOKE:
|
2300 | e1833e1f | j_mayer | srr0 = SPR_BOOKE_CSRR0; |
2301 | e1833e1f | j_mayer | srr1 = SPR_BOOKE_CSRR1; |
2302 | a750fc0b | j_mayer | break;
|
2303 | 2be0071f | bellard | default:
|
2304 | 2be0071f | bellard | break;
|
2305 | 2be0071f | bellard | } |
2306 | e1833e1f | j_mayer | /* XXX: TODO */
|
2307 | e1833e1f | j_mayer | cpu_abort(env, "Embedded doorbell critical interrupt "
|
2308 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2309 | e1833e1f | j_mayer | goto store_next;
|
2310 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPCEMB) */ |
2311 | e1833e1f | j_mayer | case POWERPC_EXCP_RESET: /* System reset exception */ |
2312 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2313 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2314 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2315 | e1833e1f | j_mayer | #endif
|
2316 | e1833e1f | j_mayer | goto store_next;
|
2317 | e1833e1f | j_mayer | #if defined(TARGET_PPC64)
|
2318 | e1833e1f | j_mayer | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
2319 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2320 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2321 | e1833e1f | j_mayer | if (lpes1 == 0) |
2322 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2323 | e1833e1f | j_mayer | #endif
|
2324 | e1833e1f | j_mayer | goto store_next;
|
2325 | e1833e1f | j_mayer | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
2326 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2327 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2328 | e1833e1f | j_mayer | if (lpes1 == 0) |
2329 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2330 | e1833e1f | j_mayer | #endif
|
2331 | e1833e1f | j_mayer | goto store_next;
|
2332 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
2333 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2334 | e1833e1f | j_mayer | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2335 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2336 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2337 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2338 | e1833e1f | j_mayer | goto store_next;
|
2339 | e1833e1f | j_mayer | #endif
|
2340 | e1833e1f | j_mayer | case POWERPC_EXCP_TRACE: /* Trace exception */ |
2341 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2342 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2343 | e1833e1f | j_mayer | if (lpes1 == 0) |
2344 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2345 | e1833e1f | j_mayer | #endif
|
2346 | e1833e1f | j_mayer | goto store_next;
|
2347 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2348 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2349 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2350 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2351 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2352 | e1833e1f | j_mayer | goto store_next;
|
2353 | e1833e1f | j_mayer | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
2354 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2355 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2356 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2357 | e1833e1f | j_mayer | goto store_next;
|
2358 | e1833e1f | j_mayer | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
2359 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2360 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2361 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2362 | e1833e1f | j_mayer | goto store_next;
|
2363 | e1833e1f | j_mayer | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
2364 | e1833e1f | j_mayer | srr0 = SPR_HSRR0; |
2365 | f9fdea6b | j_mayer | srr1 = SPR_HSRR1; |
2366 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2367 | e1833e1f | j_mayer | goto store_next;
|
2368 | e1833e1f | j_mayer | #endif /* defined(TARGET_PPC64H) */ |
2369 | e1833e1f | j_mayer | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
2370 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2371 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2372 | e1833e1f | j_mayer | if (lpes1 == 0) |
2373 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2374 | e1833e1f | j_mayer | #endif
|
2375 | e1833e1f | j_mayer | goto store_current;
|
2376 | e1833e1f | j_mayer | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
2377 | a496775f | j_mayer | #if defined (DEBUG_EXCEPTIONS)
|
2378 | e1833e1f | j_mayer | if (loglevel != 0) |
2379 | e1833e1f | j_mayer | fprintf(logfile, "PIT exception\n");
|
2380 | e1833e1f | j_mayer | #endif
|
2381 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2382 | e1833e1f | j_mayer | goto store_next;
|
2383 | e1833e1f | j_mayer | case POWERPC_EXCP_IO: /* IO error exception */ |
2384 | e1833e1f | j_mayer | /* XXX: TODO */
|
2385 | e1833e1f | j_mayer | cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
2386 | e1833e1f | j_mayer | goto store_next;
|
2387 | e1833e1f | j_mayer | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
2388 | e1833e1f | j_mayer | /* XXX: TODO */
|
2389 | e1833e1f | j_mayer | cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
2390 | e1833e1f | j_mayer | goto store_next;
|
2391 | e1833e1f | j_mayer | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
2392 | e1833e1f | j_mayer | /* XXX: TODO */
|
2393 | e1833e1f | j_mayer | cpu_abort(env, "602 emulation trap exception "
|
2394 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2395 | e1833e1f | j_mayer | goto store_next;
|
2396 | e1833e1f | j_mayer | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
2397 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2398 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2399 | e1833e1f | j_mayer | if (lpes1 == 0) |
2400 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2401 | a496775f | j_mayer | #endif
|
2402 | e1833e1f | j_mayer | switch (excp_model) {
|
2403 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2404 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2405 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2406 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2407 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2408 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2409 | 76a66253 | j_mayer | goto tlb_miss;
|
2410 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2411 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2412 | 2be0071f | bellard | default:
|
2413 | e1833e1f | j_mayer | cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
2414 | 2be0071f | bellard | break;
|
2415 | 2be0071f | bellard | } |
2416 | e1833e1f | j_mayer | break;
|
2417 | e1833e1f | j_mayer | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
2418 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2419 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2420 | e1833e1f | j_mayer | if (lpes1 == 0) |
2421 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2422 | a496775f | j_mayer | #endif
|
2423 | e1833e1f | j_mayer | switch (excp_model) {
|
2424 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2425 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2426 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2427 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2428 | e1833e1f | j_mayer | goto tlb_miss_tgpr;
|
2429 | a750fc0b | j_mayer | case POWERPC_EXCP_7x5:
|
2430 | 76a66253 | j_mayer | goto tlb_miss;
|
2431 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2432 | 7dbe11ac | j_mayer | goto tlb_miss_74xx;
|
2433 | 2be0071f | bellard | default:
|
2434 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data load TLB miss exception\n");
|
2435 | 2be0071f | bellard | break;
|
2436 | 2be0071f | bellard | } |
2437 | e1833e1f | j_mayer | break;
|
2438 | e1833e1f | j_mayer | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
2439 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2440 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H) /* XXX: check this */ |
2441 | e1833e1f | j_mayer | if (lpes1 == 0) |
2442 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2443 | e1833e1f | j_mayer | #endif
|
2444 | e1833e1f | j_mayer | switch (excp_model) {
|
2445 | a750fc0b | j_mayer | case POWERPC_EXCP_602:
|
2446 | a750fc0b | j_mayer | case POWERPC_EXCP_603:
|
2447 | a750fc0b | j_mayer | case POWERPC_EXCP_603E:
|
2448 | a750fc0b | j_mayer | case POWERPC_EXCP_G2:
|
2449 | e1833e1f | j_mayer | tlb_miss_tgpr:
|
2450 | 76a66253 | j_mayer | /* Swap temporary saved registers with GPRs */
|
2451 | 0411a972 | j_mayer | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2452 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_TGPR;
|
2453 | 0411a972 | j_mayer | hreg_swap_gpr_tgpr(env); |
2454 | 0411a972 | j_mayer | } |
2455 | e1833e1f | j_mayer | goto tlb_miss;
|
2456 | e1833e1f | j_mayer | case POWERPC_EXCP_7x5:
|
2457 | e1833e1f | j_mayer | tlb_miss:
|
2458 | 2be0071f | bellard | #if defined (DEBUG_SOFTWARE_TLB)
|
2459 | 2be0071f | bellard | if (loglevel != 0) { |
2460 | 76a66253 | j_mayer | const unsigned char *es; |
2461 | 76a66253 | j_mayer | target_ulong *miss, *cmp; |
2462 | 76a66253 | j_mayer | int en;
|
2463 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2464 | 76a66253 | j_mayer | es = "I";
|
2465 | 76a66253 | j_mayer | en = 'I';
|
2466 | 76a66253 | j_mayer | miss = &env->spr[SPR_IMISS]; |
2467 | 76a66253 | j_mayer | cmp = &env->spr[SPR_ICMP]; |
2468 | 76a66253 | j_mayer | } else {
|
2469 | 1e6784f9 | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2470 | 76a66253 | j_mayer | es = "DL";
|
2471 | 76a66253 | j_mayer | else
|
2472 | 76a66253 | j_mayer | es = "DS";
|
2473 | 76a66253 | j_mayer | en = 'D';
|
2474 | 76a66253 | j_mayer | miss = &env->spr[SPR_DMISS]; |
2475 | 76a66253 | j_mayer | cmp = &env->spr[SPR_DCMP]; |
2476 | 76a66253 | j_mayer | } |
2477 | 1b9eb036 | j_mayer | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2478 | 4a057712 | j_mayer | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
2479 | 1b9eb036 | j_mayer | es, en, *miss, en, *cmp, |
2480 | 76a66253 | j_mayer | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2481 | 2be0071f | bellard | env->error_code); |
2482 | 2be0071f | bellard | } |
2483 | 9a64fbe4 | bellard | #endif
|
2484 | 2be0071f | bellard | msr |= env->crf[0] << 28; |
2485 | 2be0071f | bellard | msr |= env->error_code; /* key, D/I, S/L bits */
|
2486 | 2be0071f | bellard | /* Set way using a LRU mechanism */
|
2487 | 76a66253 | j_mayer | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
2488 | c62db105 | j_mayer | break;
|
2489 | 7dbe11ac | j_mayer | case POWERPC_EXCP_74xx:
|
2490 | 7dbe11ac | j_mayer | tlb_miss_74xx:
|
2491 | 7dbe11ac | j_mayer | #if defined (DEBUG_SOFTWARE_TLB)
|
2492 | 7dbe11ac | j_mayer | if (loglevel != 0) { |
2493 | 7dbe11ac | j_mayer | const unsigned char *es; |
2494 | 7dbe11ac | j_mayer | target_ulong *miss, *cmp; |
2495 | 7dbe11ac | j_mayer | int en;
|
2496 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_IFTLB) {
|
2497 | 7dbe11ac | j_mayer | es = "I";
|
2498 | 7dbe11ac | j_mayer | en = 'I';
|
2499 | 0411a972 | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2500 | 0411a972 | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2501 | 7dbe11ac | j_mayer | } else {
|
2502 | 7dbe11ac | j_mayer | if (excp == POWERPC_EXCP_DLTLB)
|
2503 | 7dbe11ac | j_mayer | es = "DL";
|
2504 | 7dbe11ac | j_mayer | else
|
2505 | 7dbe11ac | j_mayer | es = "DS";
|
2506 | 7dbe11ac | j_mayer | en = 'D';
|
2507 | 7dbe11ac | j_mayer | miss = &env->spr[SPR_TLBMISS]; |
2508 | 7dbe11ac | j_mayer | cmp = &env->spr[SPR_PTEHI]; |
2509 | 7dbe11ac | j_mayer | } |
2510 | 7dbe11ac | j_mayer | fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
2511 | 7dbe11ac | j_mayer | " %08x\n",
|
2512 | 7dbe11ac | j_mayer | es, en, *miss, en, *cmp, env->error_code); |
2513 | 7dbe11ac | j_mayer | } |
2514 | 7dbe11ac | j_mayer | #endif
|
2515 | 7dbe11ac | j_mayer | msr |= env->error_code; /* key bit */
|
2516 | 7dbe11ac | j_mayer | break;
|
2517 | 2be0071f | bellard | default:
|
2518 | e1833e1f | j_mayer | cpu_abort(env, "Invalid data store TLB miss exception\n");
|
2519 | 2be0071f | bellard | break;
|
2520 | 2be0071f | bellard | } |
2521 | e1833e1f | j_mayer | goto store_next;
|
2522 | e1833e1f | j_mayer | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
2523 | e1833e1f | j_mayer | /* XXX: TODO */
|
2524 | e1833e1f | j_mayer | cpu_abort(env, "Floating point assist exception "
|
2525 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2526 | e1833e1f | j_mayer | goto store_next;
|
2527 | e1833e1f | j_mayer | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2528 | e1833e1f | j_mayer | /* XXX: TODO */
|
2529 | e1833e1f | j_mayer | cpu_abort(env, "IABR exception is not implemented yet !\n");
|
2530 | e1833e1f | j_mayer | goto store_next;
|
2531 | e1833e1f | j_mayer | case POWERPC_EXCP_SMI: /* System management interrupt */ |
2532 | e1833e1f | j_mayer | /* XXX: TODO */
|
2533 | e1833e1f | j_mayer | cpu_abort(env, "SMI exception is not implemented yet !\n");
|
2534 | e1833e1f | j_mayer | goto store_next;
|
2535 | e1833e1f | j_mayer | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
2536 | e1833e1f | j_mayer | /* XXX: TODO */
|
2537 | e1833e1f | j_mayer | cpu_abort(env, "Thermal management exception "
|
2538 | e1833e1f | j_mayer | "is not implemented yet !\n");
|
2539 | e1833e1f | j_mayer | goto store_next;
|
2540 | e1833e1f | j_mayer | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
2541 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_RI);
|
2542 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2543 | e1833e1f | j_mayer | if (lpes1 == 0) |
2544 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_HV;
|
2545 | e1833e1f | j_mayer | #endif
|
2546 | e1833e1f | j_mayer | /* XXX: TODO */
|
2547 | e1833e1f | j_mayer | cpu_abort(env, |
2548 | e1833e1f | j_mayer | "Performance counter exception is not implemented yet !\n");
|
2549 | e1833e1f | j_mayer | goto store_next;
|
2550 | e1833e1f | j_mayer | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
2551 | e1833e1f | j_mayer | /* XXX: TODO */
|
2552 | e1833e1f | j_mayer | cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
2553 | e1833e1f | j_mayer | goto store_next;
|
2554 | e1833e1f | j_mayer | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
2555 | e1833e1f | j_mayer | /* XXX: TODO */
|
2556 | e1833e1f | j_mayer | cpu_abort(env, |
2557 | e1833e1f | j_mayer | "970 soft-patch exception is not implemented yet !\n");
|
2558 | e1833e1f | j_mayer | goto store_next;
|
2559 | e1833e1f | j_mayer | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
2560 | e1833e1f | j_mayer | /* XXX: TODO */
|
2561 | e1833e1f | j_mayer | cpu_abort(env, |
2562 | e1833e1f | j_mayer | "970 maintenance exception is not implemented yet !\n");
|
2563 | e1833e1f | j_mayer | goto store_next;
|
2564 | 2be0071f | bellard | default:
|
2565 | e1833e1f | j_mayer | excp_invalid:
|
2566 | e1833e1f | j_mayer | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
2567 | e1833e1f | j_mayer | break;
|
2568 | 9a64fbe4 | bellard | store_current:
|
2569 | 2be0071f | bellard | /* save current instruction location */
|
2570 | e1833e1f | j_mayer | env->spr[srr0] = env->nip - 4;
|
2571 | 9a64fbe4 | bellard | break;
|
2572 | 9a64fbe4 | bellard | store_next:
|
2573 | 2be0071f | bellard | /* save next instruction location */
|
2574 | e1833e1f | j_mayer | env->spr[srr0] = env->nip; |
2575 | 9a64fbe4 | bellard | break;
|
2576 | 9a64fbe4 | bellard | } |
2577 | e1833e1f | j_mayer | /* Save MSR */
|
2578 | e1833e1f | j_mayer | env->spr[srr1] = msr; |
2579 | e1833e1f | j_mayer | /* If any alternate SRR register are defined, duplicate saved values */
|
2580 | e1833e1f | j_mayer | if (asrr0 != -1) |
2581 | e1833e1f | j_mayer | env->spr[asrr0] = env->spr[srr0]; |
2582 | e1833e1f | j_mayer | if (asrr1 != -1) |
2583 | e1833e1f | j_mayer | env->spr[asrr1] = env->spr[srr1]; |
2584 | 2be0071f | bellard | /* If we disactivated any translation, flush TLBs */
|
2585 | 0411a972 | j_mayer | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2586 | 2be0071f | bellard | tlb_flush(env, 1);
|
2587 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
2588 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_EE);
|
2589 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PR);
|
2590 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FP);
|
2591 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE0);
|
2592 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SE);
|
2593 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_BE);
|
2594 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_FE1);
|
2595 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_IR);
|
2596 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_DR);
|
2597 | e1833e1f | j_mayer | #if 0 /* Fix this: not on all targets */
|
2598 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_PMM);
|
2599 | e1833e1f | j_mayer | #endif
|
2600 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2601 | 0411a972 | j_mayer | if (msr_ile)
|
2602 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_LE;
|
2603 | 0411a972 | j_mayer | else
|
2604 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_LE);
|
2605 | e1833e1f | j_mayer | /* Jump to handler */
|
2606 | e1833e1f | j_mayer | vector = env->excp_vectors[excp]; |
2607 | e1833e1f | j_mayer | if (vector == (target_ulong)-1) { |
2608 | e1833e1f | j_mayer | cpu_abort(env, "Raised an exception without defined vector %d\n",
|
2609 | e1833e1f | j_mayer | excp); |
2610 | e1833e1f | j_mayer | } |
2611 | e1833e1f | j_mayer | vector |= env->excp_prefix; |
2612 | c62db105 | j_mayer | #if defined(TARGET_PPC64)
|
2613 | e1833e1f | j_mayer | if (excp_model == POWERPC_EXCP_BOOKE) {
|
2614 | 0411a972 | j_mayer | if (!msr_icm) {
|
2615 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_CM);
|
2616 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2617 | 0411a972 | j_mayer | } else {
|
2618 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_CM;
|
2619 | 0411a972 | j_mayer | } |
2620 | c62db105 | j_mayer | } else {
|
2621 | 0411a972 | j_mayer | if (!msr_isf) {
|
2622 | 0411a972 | j_mayer | new_msr &= ~((target_ulong)1 << MSR_SF);
|
2623 | e1833e1f | j_mayer | vector = (uint32_t)vector; |
2624 | 0411a972 | j_mayer | } else {
|
2625 | 0411a972 | j_mayer | new_msr |= (target_ulong)1 << MSR_SF;
|
2626 | 0411a972 | j_mayer | } |
2627 | c62db105 | j_mayer | } |
2628 | e1833e1f | j_mayer | #endif
|
2629 | 0411a972 | j_mayer | /* XXX: we don't use hreg_store_msr here as already have treated
|
2630 | 0411a972 | j_mayer | * any special case that could occur. Just store MSR and update hflags
|
2631 | 0411a972 | j_mayer | */
|
2632 | 0411a972 | j_mayer | env->msr = new_msr; |
2633 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2634 | e1833e1f | j_mayer | env->nip = vector; |
2635 | e1833e1f | j_mayer | /* Reset exception state */
|
2636 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2637 | e1833e1f | j_mayer | env->error_code = 0;
|
2638 | fb0eaffc | bellard | } |
2639 | 47103572 | j_mayer | |
2640 | e1833e1f | j_mayer | void do_interrupt (CPUState *env)
|
2641 | 47103572 | j_mayer | { |
2642 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, env->exception_index); |
2643 | e1833e1f | j_mayer | } |
2644 | 47103572 | j_mayer | |
2645 | e1833e1f | j_mayer | void ppc_hw_interrupt (CPUPPCState *env)
|
2646 | e1833e1f | j_mayer | { |
2647 | f9fdea6b | j_mayer | #if defined(TARGET_PPC64H)
|
2648 | f9fdea6b | j_mayer | int hdice;
|
2649 | f9fdea6b | j_mayer | #endif
|
2650 | f9fdea6b | j_mayer | |
2651 | 0411a972 | j_mayer | #if 0
|
2652 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
2653 | a496775f | j_mayer | fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
|
2654 | a496775f | j_mayer | __func__, env, env->pending_interrupts,
|
2655 | 0411a972 | j_mayer | env->interrupt_request, (int)msr_me, (int)msr_ee);
|
2656 | a496775f | j_mayer | }
|
2657 | 47103572 | j_mayer | #endif
|
2658 | e1833e1f | j_mayer | /* External reset */
|
2659 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
2660 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
2661 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2662 | e1833e1f | j_mayer | return;
|
2663 | e1833e1f | j_mayer | } |
2664 | e1833e1f | j_mayer | /* Machine check exception */
|
2665 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
2666 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
2667 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
2668 | e1833e1f | j_mayer | return;
|
2669 | 47103572 | j_mayer | } |
2670 | e1833e1f | j_mayer | #if 0 /* TODO */
|
2671 | e1833e1f | j_mayer | /* External debug exception */
|
2672 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
2673 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
2674 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
2675 | e1833e1f | j_mayer | return;
|
2676 | e1833e1f | j_mayer | }
|
2677 | e1833e1f | j_mayer | #endif
|
2678 | e1833e1f | j_mayer | #if defined(TARGET_PPC64H)
|
2679 | f9fdea6b | j_mayer | hdice = env->spr[SPR_LPCR] & 1;
|
2680 | f9fdea6b | j_mayer | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
2681 | 47103572 | j_mayer | /* Hypervisor decrementer exception */
|
2682 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
2683 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
2684 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2685 | e1833e1f | j_mayer | return;
|
2686 | e1833e1f | j_mayer | } |
2687 | e1833e1f | j_mayer | } |
2688 | e1833e1f | j_mayer | #endif
|
2689 | e1833e1f | j_mayer | if (msr_ce != 0) { |
2690 | e1833e1f | j_mayer | /* External critical interrupt */
|
2691 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
2692 | e1833e1f | j_mayer | /* Taking a critical external interrupt does not clear the external
|
2693 | e1833e1f | j_mayer | * critical interrupt status
|
2694 | e1833e1f | j_mayer | */
|
2695 | e1833e1f | j_mayer | #if 0
|
2696 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
2697 | 47103572 | j_mayer | #endif
|
2698 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2699 | e1833e1f | j_mayer | return;
|
2700 | e1833e1f | j_mayer | } |
2701 | e1833e1f | j_mayer | } |
2702 | e1833e1f | j_mayer | if (msr_ee != 0) { |
2703 | e1833e1f | j_mayer | /* Watchdog timer on embedded PowerPC */
|
2704 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
2705 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
2706 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
2707 | e1833e1f | j_mayer | return;
|
2708 | e1833e1f | j_mayer | } |
2709 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2710 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2711 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
2712 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
2713 | e1833e1f | j_mayer | return;
|
2714 | e1833e1f | j_mayer | } |
2715 | e1833e1f | j_mayer | #endif
|
2716 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2717 | e1833e1f | j_mayer | /* External interrupt */
|
2718 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2719 | e1833e1f | j_mayer | /* Taking an external interrupt does not clear the external
|
2720 | e1833e1f | j_mayer | * interrupt status
|
2721 | e1833e1f | j_mayer | */
|
2722 | e1833e1f | j_mayer | #if 0
|
2723 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2724 | e1833e1f | j_mayer | #endif
|
2725 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2726 | e1833e1f | j_mayer | return;
|
2727 | e1833e1f | j_mayer | } |
2728 | e1833e1f | j_mayer | #endif
|
2729 | e1833e1f | j_mayer | /* Fixed interval timer on embedded PowerPC */
|
2730 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
2731 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
2732 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
2733 | e1833e1f | j_mayer | return;
|
2734 | e1833e1f | j_mayer | } |
2735 | e1833e1f | j_mayer | /* Programmable interval timer on embedded PowerPC */
|
2736 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
2737 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
2738 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
2739 | e1833e1f | j_mayer | return;
|
2740 | e1833e1f | j_mayer | } |
2741 | 47103572 | j_mayer | /* Decrementer exception */
|
2742 | 47103572 | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
2743 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
2744 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2745 | e1833e1f | j_mayer | return;
|
2746 | e1833e1f | j_mayer | } |
2747 | e1833e1f | j_mayer | #if !defined(TARGET_PPCEMB)
|
2748 | 47103572 | j_mayer | /* External interrupt */
|
2749 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
2750 | e9df014c | j_mayer | /* Taking an external interrupt does not clear the external
|
2751 | e9df014c | j_mayer | * interrupt status
|
2752 | e9df014c | j_mayer | */
|
2753 | e9df014c | j_mayer | #if 0
|
2754 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
2755 | e9df014c | j_mayer | #endif
|
2756 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2757 | e1833e1f | j_mayer | return;
|
2758 | e1833e1f | j_mayer | } |
2759 | d0dfae6e | j_mayer | #endif
|
2760 | e1833e1f | j_mayer | #if defined(TARGET_PPCEMB)
|
2761 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2762 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
2763 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
2764 | e1833e1f | j_mayer | return;
|
2765 | 47103572 | j_mayer | } |
2766 | 47103572 | j_mayer | #endif
|
2767 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2768 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
2769 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
2770 | e1833e1f | j_mayer | return;
|
2771 | e1833e1f | j_mayer | } |
2772 | e1833e1f | j_mayer | /* Thermal interrupt */
|
2773 | e1833e1f | j_mayer | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
2774 | e1833e1f | j_mayer | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
2775 | e1833e1f | j_mayer | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
2776 | e1833e1f | j_mayer | return;
|
2777 | e1833e1f | j_mayer | } |
2778 | 47103572 | j_mayer | } |
2779 | 47103572 | j_mayer | } |
2780 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |
2781 | a496775f | j_mayer | |
2782 | a496775f | j_mayer | void cpu_dump_EA (target_ulong EA)
|
2783 | a496775f | j_mayer | { |
2784 | a496775f | j_mayer | FILE *f; |
2785 | a496775f | j_mayer | |
2786 | a496775f | j_mayer | if (logfile) {
|
2787 | a496775f | j_mayer | f = logfile; |
2788 | a496775f | j_mayer | } else {
|
2789 | a496775f | j_mayer | f = stdout; |
2790 | a496775f | j_mayer | return;
|
2791 | a496775f | j_mayer | } |
2792 | 4a057712 | j_mayer | fprintf(f, "Memory access at address " ADDRX "\n", EA); |
2793 | 4a057712 | j_mayer | } |
2794 | 4a057712 | j_mayer | |
2795 | 4a057712 | j_mayer | void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
2796 | 4a057712 | j_mayer | { |
2797 | 4a057712 | j_mayer | FILE *f; |
2798 | 4a057712 | j_mayer | |
2799 | 4a057712 | j_mayer | if (logfile) {
|
2800 | 4a057712 | j_mayer | f = logfile; |
2801 | 4a057712 | j_mayer | } else {
|
2802 | 4a057712 | j_mayer | f = stdout; |
2803 | 4a057712 | j_mayer | return;
|
2804 | 4a057712 | j_mayer | } |
2805 | 4a057712 | j_mayer | fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n", |
2806 | 4a057712 | j_mayer | RA, msr); |
2807 | a496775f | j_mayer | } |
2808 | a496775f | j_mayer | |
2809 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque) |
2810 | 0a032cbe | j_mayer | { |
2811 | 0a032cbe | j_mayer | CPUPPCState *env; |
2812 | 0411a972 | j_mayer | target_ulong msr; |
2813 | 0a032cbe | j_mayer | |
2814 | 0a032cbe | j_mayer | env = opaque; |
2815 | 0411a972 | j_mayer | msr = (target_ulong)0;
|
2816 | 5eb7995e | j_mayer | #if defined(TARGET_PPC64)
|
2817 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_HV; /* Should be 1... */ |
2818 | 5eb7995e | j_mayer | #endif
|
2819 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2820 | 0411a972 | j_mayer | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
2821 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_EP;
|
2822 | 0a032cbe | j_mayer | #if defined (DO_SINGLE_STEP) && 0 |
2823 | 0a032cbe | j_mayer | /* Single step trace mode */
|
2824 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_SE;
|
2825 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_BE;
|
2826 | 0a032cbe | j_mayer | #endif
|
2827 | 0a032cbe | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2828 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
2829 | 0411a972 | j_mayer | msr |= (target_ulong)1 << MSR_PR;
|
2830 | 0a032cbe | j_mayer | #else
|
2831 | 1c27f8fb | j_mayer | env->nip = env->hreset_vector | env->excp_prefix; |
2832 | 141c8ae2 | j_mayer | if (env->mmu_model != POWERPC_MMU_REAL_4xx)
|
2833 | 141c8ae2 | j_mayer | ppc_tlb_invalidate_all(env); |
2834 | 0a032cbe | j_mayer | #endif
|
2835 | 0411a972 | j_mayer | env->msr = msr; |
2836 | 0411a972 | j_mayer | hreg_compute_hflags(env); |
2837 | 0a032cbe | j_mayer | env->reserve = -1;
|
2838 | 5eb7995e | j_mayer | /* Be sure no exception or interrupt is pending */
|
2839 | 5eb7995e | j_mayer | env->pending_interrupts = 0;
|
2840 | e1833e1f | j_mayer | env->exception_index = POWERPC_EXCP_NONE; |
2841 | e1833e1f | j_mayer | env->error_code = 0;
|
2842 | 5eb7995e | j_mayer | /* Flush all TLBs */
|
2843 | 5eb7995e | j_mayer | tlb_flush(env, 1);
|
2844 | 0a032cbe | j_mayer | } |
2845 | 0a032cbe | j_mayer | |
2846 | 0a032cbe | j_mayer | CPUPPCState *cpu_ppc_init (void)
|
2847 | 0a032cbe | j_mayer | { |
2848 | 0a032cbe | j_mayer | CPUPPCState *env; |
2849 | 0a032cbe | j_mayer | |
2850 | 0a032cbe | j_mayer | env = qemu_mallocz(sizeof(CPUPPCState));
|
2851 | 0a032cbe | j_mayer | if (!env)
|
2852 | 0a032cbe | j_mayer | return NULL; |
2853 | 0a032cbe | j_mayer | cpu_exec_init(env); |
2854 | 0a032cbe | j_mayer | |
2855 | 0a032cbe | j_mayer | return env;
|
2856 | 0a032cbe | j_mayer | } |
2857 | 0a032cbe | j_mayer | |
2858 | 0a032cbe | j_mayer | void cpu_ppc_close (CPUPPCState *env)
|
2859 | 0a032cbe | j_mayer | { |
2860 | 0a032cbe | j_mayer | /* Should also remove all opcode tables... */
|
2861 | 0a032cbe | j_mayer | free(env); |
2862 | 0a032cbe | j_mayer | } |