Revision 5b7141a1
| b/target-sh4/helper.h | ||
|---|---|---|
| 35 | 35 |
DEF_HELPER_2(fdiv_DT, i64, i64, i64) |
| 36 | 36 |
DEF_HELPER_1(float_FT, i32, i32) |
| 37 | 37 |
DEF_HELPER_1(float_DT, i64, i32) |
| 38 |
DEF_HELPER_3(fmac_FT, i32, i32, i32, i32) |
|
| 38 | 39 |
DEF_HELPER_2(fmul_FT, i32, i32, i32) |
| 39 | 40 |
DEF_HELPER_2(fmul_DT, i64, i64, i64) |
| 40 | 41 |
DEF_HELPER_1(fneg_T, i32, i32) |
| b/target-sh4/op_helper.c | ||
|---|---|---|
| 531 | 531 |
return d.ll; |
| 532 | 532 |
} |
| 533 | 533 |
|
| 534 |
uint32_t helper_fmac_FT(uint32_t t0, uint32_t t1, uint32_t t2) |
|
| 535 |
{
|
|
| 536 |
CPU_FloatU f0, f1, f2; |
|
| 537 |
f0.l = t0; |
|
| 538 |
f1.l = t1; |
|
| 539 |
f2.l = t2; |
|
| 540 |
f0.f = float32_mul(f0.f, f1.f, &env->fp_status); |
|
| 541 |
f0.f = float32_add(f0.f, f2.f, &env->fp_status); |
|
| 542 |
return f0.l; |
|
| 543 |
} |
|
| 544 |
|
|
| 534 | 545 |
uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1) |
| 535 | 546 |
{
|
| 536 | 547 |
CPU_FloatU f0, f1; |
| b/target-sh4/translate.c | ||
|---|---|---|
| 1176 | 1176 |
} |
| 1177 | 1177 |
} |
| 1178 | 1178 |
return; |
| 1179 |
case 0xf00e: /* fmac FR0,RM,Rn */ |
|
| 1180 |
{
|
|
| 1181 |
CHECK_FPU_ENABLED |
|
| 1182 |
if (ctx->fpscr & FPSCR_PR) {
|
|
| 1183 |
break; /* illegal instruction */ |
|
| 1184 |
} else {
|
|
| 1185 |
gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], |
|
| 1186 |
cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]); |
|
| 1187 |
return; |
|
| 1188 |
} |
|
| 1189 |
} |
|
| 1179 | 1190 |
} |
| 1180 | 1191 |
|
| 1181 | 1192 |
switch (ctx->opcode & 0xff00) {
|
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