Archipelago » qemu

#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */

/* Floppy disk drive emulation */

    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */

    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */

    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */

    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */

    FDRIVE_DISK_NONE  = 0x05, /* No disk                */

    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */

    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */

    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */

    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */

    FDISK_DBL_SIDES  = 0x01,

    DriveInfo *dinfo;

    BlockDriverState *bs;

    /* Drive status */

    uint8_t perpendicular;    /* 2.88 MB access mode    */

    /* Position */

    uint8_t head;

    uint8_t track;

    uint8_t sect;

    /* Media */

    uint8_t last_sect;        /* Nb sector per track    */

    uint8_t max_track;        /* Nb of tracks           */

    uint16_t bps;             /* Bytes per sector       */

    uint8_t ro;               /* Is read-only           */

{

    /* Drive */

    drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;

}

/* Returns current position, in sectors, for given drive */

{

    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);

}

 * returns 3 if sector is invalid

 * returns 4 if seek is disabled

 */

{

    uint32_t sector;

    int ret;

}

/* Set drive back to track 0 */

{

    FLOPPY_DPRINTF("recalibrate\n");

    drv->head = 0;

}

/* Recognize floppy formats */

    uint8_t last_sect;

    uint8_t max_track;

    uint8_t max_head;

    const char *str;

    /* First entry is default format */

    /* 1.44 MB 3"1/2 floppy disks */

    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },

};

/* Revalidate a disk drive after a disk change */

{

    uint64_t nb_sectors, size;

    int i, first_match, match;

    int nb_heads, max_track, last_sect, ro;

/********************************************************/

/* Intel 82078 floppy disk controller emulation          */

static int fdctrl_transfer_handler (void *opaque, int nchan,

                                    int dma_pos, int dma_len);

enum {

    FD_DIR_WRITE   = 0,

#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)

#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)

    /* Controller's identification */

    uint8_t version;

    /* HW */

    int sun4m;

    /* Floppy drives */

    uint8_t num_floppies;

    int reset_sensei;

};

    SysBusDevice busdev;

    ISADevice busdev;

static uint32_t fdctrl_read (void *opaque, uint32_t reg)

{

    uint32_t retval;

    switch (reg) {

static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)

{

    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_END_OF_LIST()

    }

};

static void fdc_pre_save(void *opaque)

{

    s->dor_vmstate = s->dor | GET_CUR_DRV(s);

}

static int fdc_post_load(void *opaque, int version_id)

{

    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);

    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;

    .post_load = fdc_post_load,

    .fields      = (VMStateField []) {

        /* Controller State */

        /* Command FIFO */

        /* States kept only to be returned back */

        VMSTATE_END_OF_LIST()

    }

};

static void fdctrl_external_reset_sysbus(DeviceState *d)

{

    fdctrl_reset(s, 0);

}

static void fdctrl_external_reset_isa(DeviceState *d)

{

    fdctrl_reset(s, 0);

}

static void fdctrl_handle_tc(void *opaque, int irq, int level)

{

    if (level) {

        // XXX

}

/* XXX: may change if moved to bdrv */

{

    return fdctrl->drives[drive_num].drive;

}

/* Change IRQ state */

{

    if (!(fdctrl->sra & FD_SRA_INTPEND))

        return;

    fdctrl->sra &= ~FD_SRA_INTPEND;

}

{

    /* Sparc mutation */

    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {

}

/* Reset controller */

{

    int i;

    }

}

{

    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];

}

{

    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))

        return &fdctrl->drives[1];

}

#if MAX_FD == 4

{

    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))

        return &fdctrl->drives[2];

        return &fdctrl->drives[1];

}

{

    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))

        return &fdctrl->drives[3];

}

#endif

{

    switch (fdctrl->cur_drv) {

        case 0: return drv0(fdctrl);

}

/* Status A register : 0x00 (read-only) */

{

    uint32_t retval = fdctrl->sra;

}

/* Status B register : 0x01 (read-only) */

{

    uint32_t retval = fdctrl->srb;

}

/* Digital output register : 0x02 */

{

    uint32_t retval = fdctrl->dor;

    return retval;

}

{

    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);

}

/* Tape drive register : 0x03 */

{

    uint32_t retval = fdctrl->tdr;

    return retval;

}

{

    /* Reset mode */

    if (!(fdctrl->dor & FD_DOR_nRESET)) {

}

/* Main status register : 0x04 (read) */

{

    uint32_t retval = fdctrl->msr;

}

/* Data select rate register : 0x04 (write) */

{

    /* Reset mode */

    if (!(fdctrl->dor & FD_DOR_nRESET)) {

    fdctrl->dsr = value;

}

{

    int ret;

}

/* Digital input register : 0x07 (read-only) */

{

    uint32_t retval = 0;

}

/* FIFO state control */

{

    fdctrl->data_dir = FD_DIR_WRITE;

    fdctrl->data_pos = 0;

}

/* Set FIFO status for the host to read */

{

    fdctrl->data_dir = FD_DIR_READ;

    fdctrl->data_len = fifo_len;

}

/* Set an error: unimplemented/unknown command */

{

    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);

    fdctrl->fifo[0] = FD_SR0_INVCMD;

}

/* Seek to next sector */

{

    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",

                   cur_drv->head, cur_drv->track, cur_drv->sect,

}

/* Callback for transfer end (stop or abort) */

{

    cur_drv = get_cur_drv(fdctrl);

    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",

}

/* Prepare a data transfer (either DMA or FIFO) */

{

    uint8_t kh, kt, ks;

    int did_seek = 0;

}

/* Prepare a transfer of deleted data */

{

    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");

static int fdctrl_transfer_handler (void *opaque, int nchan,

                                    int dma_pos, int dma_len)

{

    int len, start_pos, rel_pos;

    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;

}

/* Data register : 0x05 */

{

    uint32_t retval = 0;

    int pos;

    return retval;

}

{

    uint8_t kh, kt, ks;

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    }

}

{

    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;

    fdctrl->fifo[0] = fdctrl->lock << 4;

    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);

}

{

    /* Drives position */

    fdctrl->fifo[0] = drv0(fdctrl)->track;

    fdctrl_set_fifo(fdctrl, 10, 0);

}

{

    /* Controller's version */

    fdctrl->fifo[0] = fdctrl->version;

    fdctrl_set_fifo(fdctrl, 1, 1);

}

{

    fdctrl->fifo[0] = 0x41; /* Stepping 1 */

    fdctrl_set_fifo(fdctrl, 1, 0);

}

{

    /* Drives position */

    drv0(fdctrl)->track = fdctrl->fifo[3];

    fdctrl_reset_fifo(fdctrl);

}

{

    fdctrl->fifo[0] = 0;

    fdctrl->fifo[1] = 0;

    fdctrl_set_fifo(fdctrl, 15, 1);

}

{

    /* XXX: should set main status register to busy */

    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;

                   qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));

}

{

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    cur_drv = get_cur_drv(fdctrl);

    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);

}

{

    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;

    fdctrl->timer1 = fdctrl->fifo[2] >> 1;

    fdctrl_reset_fifo(fdctrl);

}

{

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    cur_drv = get_cur_drv(fdctrl);

    fdctrl_set_fifo(fdctrl, 1, 0);

}

{

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    cur_drv = get_cur_drv(fdctrl);

    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);

}

{

    if(fdctrl->reset_sensei > 0) {

        fdctrl->fifo[0] =

    fdctrl->status0 = FD_SR0_RDYCHG;

}

{

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    cur_drv = get_cur_drv(fdctrl);

    }

}

{

    if (fdctrl->fifo[1] & 0x80)

        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;

    fdctrl_reset_fifo(fdctrl);

}

{

    fdctrl->config = fdctrl->fifo[2];

    fdctrl->precomp_trk =  fdctrl->fifo[3];

    fdctrl_reset_fifo(fdctrl);

}

{

    fdctrl->pwrd = fdctrl->fifo[1];

    fdctrl->fifo[0] = fdctrl->fifo[1];

    fdctrl_set_fifo(fdctrl, 1, 1);

}

{

    /* No result back */

    fdctrl_reset_fifo(fdctrl);

}

{

    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {

        /* Command parameters done */

    }

}

{

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    cur_drv = get_cur_drv(fdctrl);

    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);

}

{

    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);

    cur_drv = get_cur_drv(fdctrl);

    uint8_t mask;

    const char* name;

    int parameters;

    int direction;

} handlers[] = {

    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },

/* Associate command to an index in the 'handlers' array */

static uint8_t command_to_handler[256];

{

    int pos;

    /* Reset mode */

static void fdctrl_result_timer(void *opaque)

{

    /* Pretend we are spinning.

     * This is needed for Coherent, which uses READ ID to check for

}

/* Init functions */

{

    unsigned int i;

    }

}

{

    ISADevice *dev;

    qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);

    if (qdev_init(&dev->qdev) < 0)

        return NULL;

}

{

    DeviceState *dev;

    dev = qdev_create(NULL, "sysbus-fdc");

    fdctrl = &sys->state;

    fdctrl->dma_chann = dma_chann; /* FIXME */

    qdev_prop_set_drive(dev, "driveA", fds[0]);

    return fdctrl;

}

{

    DeviceState *dev;

    dev = qdev_create(NULL, "SUNW,fdtwo");

    qdev_prop_set_drive(dev, "drive", fds[0]);

    qdev_init_nofail(dev);

    fdctrl = &sys->state;

    sysbus_connect_irq(&sys->busdev, 0, irq);

    sysbus_mmio_map(&sys->busdev, 0, io_base);

    return fdctrl;

}

{

    int i, j;

    static int command_tables_inited = 0;

static int isabus_fdc_init1(ISADevice *dev)

{

    int iobase = 0x3f0;

    int isairq = 6;

    int dma_chann = 2;

static int sysbus_fdc_init1(SysBusDevice *dev)

{

    int io;

    int ret;

static int sun4m_fdc_init1(SysBusDevice *dev)

{

    int io;

    io = cpu_register_io_memory(fdctrl_mem_read_strict,

static ISADeviceInfo isa_fdc_info = {

    .init = isabus_fdc_init1,

    .qdev.name  = "isa-fdc",

    .qdev.no_user = 1,

    .qdev.reset = fdctrl_external_reset_isa,

    .qdev.props = (Property[]) {

        DEFINE_PROP_END_OF_LIST(),

    },

};

static SysBusDeviceInfo sysbus_fdc_info = {

    .init = sysbus_fdc_init1,

    .qdev.name  = "sysbus-fdc",

    .qdev.reset = fdctrl_external_reset_sysbus,

    .qdev.props = (Property[]) {

        DEFINE_PROP_END_OF_LIST(),

    },

};

static SysBusDeviceInfo sun4m_fdc_info = {

    .init = sun4m_fdc_init1,

    .qdev.name  = "SUNW,fdtwo",

    .qdev.reset = fdctrl_external_reset_sysbus,

    .qdev.props = (Property[]) {

        DEFINE_PROP_END_OF_LIST(),

    },

};

#include "sysemu.h"

#define MAX_FD 2

    ISADevice *isa_dev;

    CPUState *env;

    RTCState *rtc_state;

    MaltaFPGAState *malta_fpga;

    qemu_irq *i8259;

    int piix4_devfn;

#define MAX_IDE_BUS 2

static RTCState *rtc_state;

static PITState *pit;

static PCII440FXState *i440fx_state;