Revision 5c130f65 hw/ppc405.h

b/hw/ppc405.h
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                         target_phys_addr_t offset, qemu_irq irq,
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                         CharDriverState *chr);
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/* On Chip Memory */
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void ppc405_ocm_init (CPUState *env, unsigned long offset);
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void ppc405_ocm_init (CPUState *env);
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/* I2C controller */
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void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                      target_phys_addr_t offset, qemu_irq irq);
......
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CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
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                         target_phys_addr_t ram_sizes[4],
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                         uint32_t sysclk, qemu_irq **picp,
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                         ram_addr_t *offsetp, int do_init);
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                         int do_init);
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CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
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                         target_phys_addr_t ram_sizes[2],
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                         uint32_t sysclk, qemu_irq **picp,
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                         ram_addr_t *offsetp, int do_init);
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                         int do_init);
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/* IBM STBxxx microcontrollers */
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CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
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                           target_phys_addr_t ram_sizes[2],

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