Revision 5c130f65 hw/ppc405_uc.c
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 51 | 51 |
bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
| 52 | 52 |
else |
| 53 | 53 |
bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
| 54 |
stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
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|
| 55 |
stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
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|
| 56 |
stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
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|
| 57 |
stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
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|
| 58 |
stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
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|
| 59 |
stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
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|
| 60 |
stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
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|
| 61 |
stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
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|
| 62 |
stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
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|
| 54 |
stl_phys(bdloc + 0x00, bd->bi_memstart);
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|
| 55 |
stl_phys(bdloc + 0x04, bd->bi_memsize);
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| 56 |
stl_phys(bdloc + 0x08, bd->bi_flashstart);
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|
| 57 |
stl_phys(bdloc + 0x0C, bd->bi_flashsize);
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| 58 |
stl_phys(bdloc + 0x10, bd->bi_flashoffset);
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|
| 59 |
stl_phys(bdloc + 0x14, bd->bi_sramstart);
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|
| 60 |
stl_phys(bdloc + 0x18, bd->bi_sramsize);
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|
| 61 |
stl_phys(bdloc + 0x1C, bd->bi_bootflags);
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|
| 62 |
stl_phys(bdloc + 0x20, bd->bi_ipaddr);
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|
| 63 | 63 |
for (i = 0; i < 6; i++) |
| 64 |
stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
|
|
| 65 |
stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
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|
| 66 |
stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
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|
| 67 |
stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
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|
| 68 |
stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
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|
| 64 |
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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| 65 |
stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
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| 66 |
stl_phys(bdloc + 0x2C, bd->bi_intfreq);
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| 67 |
stl_phys(bdloc + 0x30, bd->bi_busfreq);
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| 68 |
stl_phys(bdloc + 0x34, bd->bi_baudrate);
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| 69 | 69 |
for (i = 0; i < 4; i++) |
| 70 |
stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
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|
| 70 |
stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
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|
| 71 | 71 |
for (i = 0; i < 32; i++) |
| 72 |
stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
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|
| 73 |
stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
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|
| 74 |
stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
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| 72 |
stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
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| 73 |
stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
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| 74 |
stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
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| 75 | 75 |
for (i = 0; i < 6; i++) |
| 76 |
stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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|
| 76 |
stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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|
| 77 | 77 |
n = 0x6A; |
| 78 | 78 |
if (flags & 0x00000001) {
|
| 79 | 79 |
for (i = 0; i < 6; i++) |
| 80 |
stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
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|
| 80 |
stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
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|
| 81 | 81 |
} |
| 82 |
stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
|
|
| 82 |
stl_phys(bdloc + n, bd->bi_opbfreq);
|
|
| 83 | 83 |
n += 4; |
| 84 | 84 |
for (i = 0; i < 2; i++) {
|
| 85 |
stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
|
|
| 85 |
stl_phys(bdloc + n, bd->bi_iic_fast[i]);
|
|
| 86 | 86 |
n += 4; |
| 87 | 87 |
} |
| 88 | 88 |
|
| ... | ... | |
| 1021 | 1021 |
ocm->dsacntl = dsacntl; |
| 1022 | 1022 |
} |
| 1023 | 1023 |
|
| 1024 |
void ppc405_ocm_init (CPUState *env, unsigned long offset)
|
|
| 1024 |
void ppc405_ocm_init (CPUState *env) |
|
| 1025 | 1025 |
{
|
| 1026 | 1026 |
ppc405_ocm_t *ocm; |
| 1027 | 1027 |
|
| 1028 | 1028 |
ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); |
| 1029 |
ocm->offset = offset;
|
|
| 1029 |
ocm->offset = qemu_ram_alloc(4096);
|
|
| 1030 | 1030 |
ocm_reset(ocm); |
| 1031 | 1031 |
qemu_register_reset(&ocm_reset, ocm); |
| 1032 | 1032 |
ppc_dcr_register(env, OCM0_ISARC, |
| ... | ... | |
| 2178 | 2178 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
| 2179 | 2179 |
target_phys_addr_t ram_sizes[4], |
| 2180 | 2180 |
uint32_t sysclk, qemu_irq **picp, |
| 2181 |
ram_addr_t *offsetp, int do_init)
|
|
| 2181 |
int do_init) |
|
| 2182 | 2182 |
{
|
| 2183 | 2183 |
clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
| 2184 | 2184 |
qemu_irq dma_irqs[4]; |
| 2185 | 2185 |
CPUState *env; |
| 2186 | 2186 |
ppc4xx_mmio_t *mmio; |
| 2187 | 2187 |
qemu_irq *pic, *irqs; |
| 2188 |
ram_addr_t offset; |
|
| 2189 |
int i; |
|
| 2190 | 2188 |
|
| 2191 | 2189 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 2192 | 2190 |
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
| ... | ... | |
| 2209 | 2207 |
*picp = pic; |
| 2210 | 2208 |
/* SDRAM controller */ |
| 2211 | 2209 |
ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
| 2212 |
offset = 0; |
|
| 2213 |
for (i = 0; i < 4; i++) |
|
| 2214 |
offset += ram_sizes[i]; |
|
| 2215 | 2210 |
/* External bus controller */ |
| 2216 | 2211 |
ppc405_ebc_init(env); |
| 2217 | 2212 |
/* DMA controller */ |
| ... | ... | |
| 2233 | 2228 |
ppc405_gpio_init(env, mmio, 0x700); |
| 2234 | 2229 |
/* CPU control */ |
| 2235 | 2230 |
ppc405cr_cpc_init(env, clk_setup, sysclk); |
| 2236 |
*offsetp = offset; |
|
| 2237 | 2231 |
|
| 2238 | 2232 |
return env; |
| 2239 | 2233 |
} |
| ... | ... | |
| 2529 | 2523 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
| 2530 | 2524 |
target_phys_addr_t ram_sizes[2], |
| 2531 | 2525 |
uint32_t sysclk, qemu_irq **picp, |
| 2532 |
ram_addr_t *offsetp, int do_init)
|
|
| 2526 |
int do_init) |
|
| 2533 | 2527 |
{
|
| 2534 | 2528 |
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
| 2535 | 2529 |
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
| 2536 | 2530 |
CPUState *env; |
| 2537 | 2531 |
ppc4xx_mmio_t *mmio; |
| 2538 | 2532 |
qemu_irq *pic, *irqs; |
| 2539 |
ram_addr_t offset; |
|
| 2540 |
int i; |
|
| 2541 | 2533 |
|
| 2542 | 2534 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 2543 | 2535 |
/* init CPUs */ |
| ... | ... | |
| 2565 | 2557 |
/* SDRAM controller */ |
| 2566 | 2558 |
/* XXX 405EP has no ECC interrupt */ |
| 2567 | 2559 |
ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
| 2568 |
offset = 0; |
|
| 2569 |
for (i = 0; i < 2; i++) |
|
| 2570 |
offset += ram_sizes[i]; |
|
| 2571 | 2560 |
/* External bus controller */ |
| 2572 | 2561 |
ppc405_ebc_init(env); |
| 2573 | 2562 |
/* DMA controller */ |
| ... | ... | |
| 2588 | 2577 |
ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
| 2589 | 2578 |
} |
| 2590 | 2579 |
/* OCM */ |
| 2591 |
ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); |
|
| 2592 |
offset += 4096; |
|
| 2580 |
ppc405_ocm_init(env); |
|
| 2593 | 2581 |
/* GPT */ |
| 2594 | 2582 |
gpt_irqs[0] = pic[19]; |
| 2595 | 2583 |
gpt_irqs[1] = pic[20]; |
| ... | ... | |
| 2609 | 2597 |
/* Uses pic[9], pic[15], pic[17] */ |
| 2610 | 2598 |
/* CPU control */ |
| 2611 | 2599 |
ppc405ep_cpc_init(env, clk_setup, sysclk); |
| 2612 |
*offsetp = offset; |
|
| 2613 | 2600 |
|
| 2614 | 2601 |
return env; |
| 2615 | 2602 |
} |
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