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1 | 2f062c72 | ths | /*
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2 | 2f062c72 | ths | * QEMU SCI/SCIF serial port emulation
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3 | 2f062c72 | ths | *
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4 | 2f062c72 | ths | * Copyright (c) 2007 Magnus Damm
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5 | 2f062c72 | ths | *
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6 | 2f062c72 | ths | * Based on serial.c - QEMU 16450 UART emulation
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7 | 2f062c72 | ths | * Copyright (c) 2003-2004 Fabrice Bellard
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8 | 2f062c72 | ths | *
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9 | 2f062c72 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 2f062c72 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | 2f062c72 | ths | * in the Software without restriction, including without limitation the rights
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12 | 2f062c72 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 2f062c72 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | 2f062c72 | ths | * furnished to do so, subject to the following conditions:
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15 | 2f062c72 | ths | *
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16 | 2f062c72 | ths | * The above copyright notice and this permission notice shall be included in
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17 | 2f062c72 | ths | * all copies or substantial portions of the Software.
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18 | 2f062c72 | ths | *
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19 | 2f062c72 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 2f062c72 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 2f062c72 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 2f062c72 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 2f062c72 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 2f062c72 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 2f062c72 | ths | * THE SOFTWARE.
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26 | 2f062c72 | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "sh.h" |
29 | 87ecb68b | pbrook | #include "qemu-char.h" |
30 | 2f062c72 | ths | #include <assert.h> |
31 | 2f062c72 | ths | |
32 | 2f062c72 | ths | //#define DEBUG_SERIAL
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33 | 2f062c72 | ths | |
34 | 2f062c72 | ths | #define SH_SERIAL_FLAG_TEND (1 << 0) |
35 | 2f062c72 | ths | #define SH_SERIAL_FLAG_TDE (1 << 1) |
36 | 2f062c72 | ths | #define SH_SERIAL_FLAG_RDF (1 << 2) |
37 | 2f062c72 | ths | #define SH_SERIAL_FLAG_BRK (1 << 3) |
38 | 2f062c72 | ths | #define SH_SERIAL_FLAG_DR (1 << 4) |
39 | 2f062c72 | ths | |
40 | 63242a00 | aurel32 | #define SH_RX_FIFO_LENGTH (16) |
41 | 63242a00 | aurel32 | |
42 | 2f062c72 | ths | typedef struct { |
43 | 2f062c72 | ths | uint8_t smr; |
44 | 2f062c72 | ths | uint8_t brr; |
45 | 2f062c72 | ths | uint8_t scr; |
46 | 2f062c72 | ths | uint8_t dr; /* ftdr / tdr */
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47 | 2f062c72 | ths | uint8_t sr; /* fsr / ssr */
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48 | 2f062c72 | ths | uint16_t fcr; |
49 | 2f062c72 | ths | uint8_t sptr; |
50 | 2f062c72 | ths | |
51 | 63242a00 | aurel32 | uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
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52 | 2f062c72 | ths | uint8_t rx_cnt; |
53 | 63242a00 | aurel32 | uint8_t rx_tail; |
54 | 63242a00 | aurel32 | uint8_t rx_head; |
55 | 2f062c72 | ths | |
56 | 2f062c72 | ths | int freq;
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57 | 2f062c72 | ths | int feat;
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58 | 2f062c72 | ths | int flags;
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59 | 63242a00 | aurel32 | int rtrg;
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60 | 2f062c72 | ths | |
61 | 2f062c72 | ths | CharDriverState *chr; |
62 | bf5b7423 | aurel32 | |
63 | 4e7ed2d1 | aurel32 | qemu_irq eri; |
64 | 4e7ed2d1 | aurel32 | qemu_irq rxi; |
65 | 4e7ed2d1 | aurel32 | qemu_irq txi; |
66 | 4e7ed2d1 | aurel32 | qemu_irq tei; |
67 | 4e7ed2d1 | aurel32 | qemu_irq bri; |
68 | 2f062c72 | ths | } sh_serial_state; |
69 | 2f062c72 | ths | |
70 | 63242a00 | aurel32 | static void sh_serial_clear_fifo(sh_serial_state * s) |
71 | 63242a00 | aurel32 | { |
72 | 63242a00 | aurel32 | memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
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73 | 63242a00 | aurel32 | s->rx_cnt = 0;
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74 | 63242a00 | aurel32 | s->rx_head = 0;
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75 | 63242a00 | aurel32 | s->rx_tail = 0;
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76 | 63242a00 | aurel32 | } |
77 | 63242a00 | aurel32 | |
78 | 2f062c72 | ths | static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val) |
79 | 2f062c72 | ths | { |
80 | 2f062c72 | ths | sh_serial_state *s = opaque; |
81 | 2f062c72 | ths | unsigned char ch; |
82 | 2f062c72 | ths | |
83 | 2f062c72 | ths | #ifdef DEBUG_SERIAL
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84 | 8da3ff18 | pbrook | printf("sh_serial: write offs=0x%02x val=0x%02x\n",
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85 | 8da3ff18 | pbrook | offs, val); |
86 | 2f062c72 | ths | #endif
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87 | 2f062c72 | ths | switch(offs) {
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88 | 2f062c72 | ths | case 0x00: /* SMR */ |
89 | 2f062c72 | ths | s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); |
90 | 2f062c72 | ths | return;
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91 | 2f062c72 | ths | case 0x04: /* BRR */ |
92 | 2f062c72 | ths | s->brr = val; |
93 | 2f062c72 | ths | return;
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94 | 2f062c72 | ths | case 0x08: /* SCR */ |
95 | 63242a00 | aurel32 | /* TODO : For SH7751, SCIF mask should be 0xfb. */
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96 | bf5b7423 | aurel32 | s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); |
97 | 2f062c72 | ths | if (!(val & (1 << 5))) |
98 | 2f062c72 | ths | s->flags |= SH_SERIAL_FLAG_TEND; |
99 | bf5b7423 | aurel32 | if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
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100 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->txi, val & (1 << 7)); |
101 | bf5b7423 | aurel32 | } |
102 | 4e7ed2d1 | aurel32 | if (!(val & (1 << 6))) { |
103 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->rxi, 0);
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104 | 63242a00 | aurel32 | } |
105 | 2f062c72 | ths | return;
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106 | 2f062c72 | ths | case 0x0c: /* FTDR / TDR */ |
107 | 2f062c72 | ths | if (s->chr) {
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108 | 2f062c72 | ths | ch = val; |
109 | 2f062c72 | ths | qemu_chr_write(s->chr, &ch, 1);
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110 | 2f062c72 | ths | } |
111 | 2f062c72 | ths | s->dr = val; |
112 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TDE; |
113 | 2f062c72 | ths | return;
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114 | 2f062c72 | ths | #if 0
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115 | 2f062c72 | ths | case 0x14: /* FRDR / RDR */
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116 | 2f062c72 | ths | ret = 0;
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117 | 2f062c72 | ths | break;
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118 | 2f062c72 | ths | #endif
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119 | 2f062c72 | ths | } |
120 | 2f062c72 | ths | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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121 | 2f062c72 | ths | switch(offs) {
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122 | 2f062c72 | ths | case 0x10: /* FSR */ |
123 | 2f062c72 | ths | if (!(val & (1 << 6))) |
124 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TEND; |
125 | 2f062c72 | ths | if (!(val & (1 << 5))) |
126 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TDE; |
127 | 2f062c72 | ths | if (!(val & (1 << 4))) |
128 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_BRK; |
129 | 2f062c72 | ths | if (!(val & (1 << 1))) |
130 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_RDF; |
131 | 2f062c72 | ths | if (!(val & (1 << 0))) |
132 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_DR; |
133 | 63242a00 | aurel32 | |
134 | 63242a00 | aurel32 | if (!(val & (1 << 1)) || !(val & (1 << 0))) { |
135 | 4e7ed2d1 | aurel32 | if (s->rxi) {
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136 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->rxi, 0);
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137 | 63242a00 | aurel32 | } |
138 | 63242a00 | aurel32 | } |
139 | 2f062c72 | ths | return;
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140 | 2f062c72 | ths | case 0x18: /* FCR */ |
141 | 2f062c72 | ths | s->fcr = val; |
142 | 63242a00 | aurel32 | switch ((val >> 6) & 3) { |
143 | 63242a00 | aurel32 | case 0: |
144 | 63242a00 | aurel32 | s->rtrg = 1;
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145 | 63242a00 | aurel32 | break;
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146 | 63242a00 | aurel32 | case 1: |
147 | 63242a00 | aurel32 | s->rtrg = 4;
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148 | 63242a00 | aurel32 | break;
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149 | 63242a00 | aurel32 | case 2: |
150 | 63242a00 | aurel32 | s->rtrg = 8;
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151 | 63242a00 | aurel32 | break;
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152 | 63242a00 | aurel32 | case 3: |
153 | 63242a00 | aurel32 | s->rtrg = 14;
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154 | 63242a00 | aurel32 | break;
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155 | 63242a00 | aurel32 | } |
156 | 63242a00 | aurel32 | if (val & (1 << 1)) { |
157 | 63242a00 | aurel32 | sh_serial_clear_fifo(s); |
158 | 63242a00 | aurel32 | s->sr &= ~(1 << 1); |
159 | 63242a00 | aurel32 | } |
160 | 63242a00 | aurel32 | |
161 | 2f062c72 | ths | return;
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162 | 2f062c72 | ths | case 0x20: /* SPTR */ |
163 | 63242a00 | aurel32 | s->sptr = val & 0xf3;
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164 | 2f062c72 | ths | return;
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165 | 2f062c72 | ths | case 0x24: /* LSR */ |
166 | 2f062c72 | ths | return;
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167 | 2f062c72 | ths | } |
168 | 2f062c72 | ths | } |
169 | 2f062c72 | ths | else {
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170 | 2f062c72 | ths | #if 0
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171 | 2f062c72 | ths | switch(offs) {
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172 | 2f062c72 | ths | case 0x0c:
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173 | 2f062c72 | ths | ret = s->dr;
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174 | 2f062c72 | ths | break;
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175 | 2f062c72 | ths | case 0x10:
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176 | 2f062c72 | ths | ret = 0;
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177 | 2f062c72 | ths | break;
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178 | 2f062c72 | ths | case 0x1c:
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179 | 2f062c72 | ths | ret = s->sptr;
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180 | 2f062c72 | ths | break;
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181 | 2f062c72 | ths | }
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182 | 2f062c72 | ths | #endif
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183 | 2f062c72 | ths | } |
184 | 2f062c72 | ths | |
185 | 2f062c72 | ths | fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
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186 | 2f062c72 | ths | assert(0);
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187 | 2f062c72 | ths | } |
188 | 2f062c72 | ths | |
189 | 2f062c72 | ths | static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs) |
190 | 2f062c72 | ths | { |
191 | 2f062c72 | ths | sh_serial_state *s = opaque; |
192 | 2f062c72 | ths | uint32_t ret = ~0;
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193 | 2f062c72 | ths | |
194 | 2f062c72 | ths | #if 0
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195 | 2f062c72 | ths | switch(offs) {
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196 | 2f062c72 | ths | case 0x00:
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197 | 2f062c72 | ths | ret = s->smr;
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198 | 2f062c72 | ths | break;
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199 | 2f062c72 | ths | case 0x04:
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200 | 2f062c72 | ths | ret = s->brr;
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201 | 2f062c72 | ths | break;
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202 | 2f062c72 | ths | case 0x08:
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203 | 2f062c72 | ths | ret = s->scr;
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204 | 2f062c72 | ths | break;
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205 | 2f062c72 | ths | case 0x14:
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206 | 2f062c72 | ths | ret = 0;
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207 | 2f062c72 | ths | break;
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208 | 2f062c72 | ths | }
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209 | 2f062c72 | ths | #endif
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210 | 2f062c72 | ths | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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211 | 2f062c72 | ths | switch(offs) {
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212 | bf5b7423 | aurel32 | case 0x00: /* SMR */ |
213 | bf5b7423 | aurel32 | ret = s->smr; |
214 | bf5b7423 | aurel32 | break;
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215 | bf5b7423 | aurel32 | case 0x08: /* SCR */ |
216 | bf5b7423 | aurel32 | ret = s->scr; |
217 | bf5b7423 | aurel32 | break;
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218 | 2f062c72 | ths | case 0x10: /* FSR */ |
219 | 2f062c72 | ths | ret = 0;
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220 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_TEND)
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221 | 2f062c72 | ths | ret |= (1 << 6); |
222 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_TDE)
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223 | 2f062c72 | ths | ret |= (1 << 5); |
224 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_BRK)
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225 | 2f062c72 | ths | ret |= (1 << 4); |
226 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_RDF)
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227 | 2f062c72 | ths | ret |= (1 << 1); |
228 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_DR)
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229 | 2f062c72 | ths | ret |= (1 << 0); |
230 | 2f062c72 | ths | |
231 | 63242a00 | aurel32 | if (s->scr & (1 << 5)) |
232 | 2f062c72 | ths | s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; |
233 | 2f062c72 | ths | |
234 | 2f062c72 | ths | break;
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235 | 63242a00 | aurel32 | case 0x14: |
236 | 63242a00 | aurel32 | if (s->rx_cnt > 0) { |
237 | 63242a00 | aurel32 | ret = s->rx_fifo[s->rx_tail++]; |
238 | 63242a00 | aurel32 | s->rx_cnt--; |
239 | 63242a00 | aurel32 | if (s->rx_tail == SH_RX_FIFO_LENGTH)
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240 | 63242a00 | aurel32 | s->rx_tail = 0;
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241 | 63242a00 | aurel32 | if (s->rx_cnt < s->rtrg)
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242 | 63242a00 | aurel32 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
243 | 63242a00 | aurel32 | } |
244 | 63242a00 | aurel32 | break;
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245 | 2f062c72 | ths | #if 0
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246 | 2f062c72 | ths | case 0x18:
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247 | 2f062c72 | ths | ret = s->fcr;
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248 | 2f062c72 | ths | break;
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249 | 2f062c72 | ths | #endif
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250 | 2f062c72 | ths | case 0x1c: |
251 | 2f062c72 | ths | ret = s->rx_cnt; |
252 | 2f062c72 | ths | break;
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253 | 2f062c72 | ths | case 0x20: |
254 | 2f062c72 | ths | ret = s->sptr; |
255 | 2f062c72 | ths | break;
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256 | 2f062c72 | ths | case 0x24: |
257 | 2f062c72 | ths | ret = 0;
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258 | 2f062c72 | ths | break;
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259 | 2f062c72 | ths | } |
260 | 2f062c72 | ths | } |
261 | 2f062c72 | ths | else {
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262 | 2f062c72 | ths | #if 0
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263 | 2f062c72 | ths | switch(offs) {
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264 | 2f062c72 | ths | case 0x0c:
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265 | 2f062c72 | ths | ret = s->dr;
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266 | 2f062c72 | ths | break;
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267 | 2f062c72 | ths | case 0x10:
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268 | 2f062c72 | ths | ret = 0;
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269 | 2f062c72 | ths | break;
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270 | 63242a00 | aurel32 | case 0x14:
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271 | 63242a00 | aurel32 | ret = s->rx_fifo[0];
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272 | 63242a00 | aurel32 | break;
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273 | 2f062c72 | ths | case 0x1c:
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274 | 2f062c72 | ths | ret = s->sptr;
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275 | 2f062c72 | ths | break;
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276 | 2f062c72 | ths | }
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277 | 2f062c72 | ths | #endif
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278 | 2f062c72 | ths | } |
279 | 2f062c72 | ths | #ifdef DEBUG_SERIAL
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280 | 8da3ff18 | pbrook | printf("sh_serial: read offs=0x%02x val=0x%x\n",
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281 | 8da3ff18 | pbrook | offs, ret); |
282 | 2f062c72 | ths | #endif
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283 | 2f062c72 | ths | |
284 | 2f062c72 | ths | if (ret & ~((1 << 16) - 1)) { |
285 | 2f062c72 | ths | fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
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286 | 2f062c72 | ths | assert(0);
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287 | 2f062c72 | ths | } |
288 | 2f062c72 | ths | |
289 | 2f062c72 | ths | return ret;
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290 | 2f062c72 | ths | } |
291 | 2f062c72 | ths | |
292 | 2f062c72 | ths | static int sh_serial_can_receive(sh_serial_state *s) |
293 | 2f062c72 | ths | { |
294 | 63242a00 | aurel32 | return s->scr & (1 << 4); |
295 | 2f062c72 | ths | } |
296 | 2f062c72 | ths | |
297 | 2f062c72 | ths | static void sh_serial_receive_byte(sh_serial_state *s, int ch) |
298 | 2f062c72 | ths | { |
299 | 63242a00 | aurel32 | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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300 | 63242a00 | aurel32 | if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
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301 | 63242a00 | aurel32 | s->rx_fifo[s->rx_head++] = ch; |
302 | 63242a00 | aurel32 | if (s->rx_head == SH_RX_FIFO_LENGTH)
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303 | 63242a00 | aurel32 | s->rx_head = 0;
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304 | 63242a00 | aurel32 | s->rx_cnt++; |
305 | 63242a00 | aurel32 | if (s->rx_cnt >= s->rtrg) {
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306 | 63242a00 | aurel32 | s->flags |= SH_SERIAL_FLAG_RDF; |
307 | 63242a00 | aurel32 | if (s->scr & (1 << 6) && s->rxi) { |
308 | 4e7ed2d1 | aurel32 | qemu_set_irq(s->rxi, 1);
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309 | 63242a00 | aurel32 | } |
310 | 63242a00 | aurel32 | } |
311 | 63242a00 | aurel32 | } |
312 | 63242a00 | aurel32 | } else {
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313 | 63242a00 | aurel32 | s->rx_fifo[0] = ch;
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314 | 63242a00 | aurel32 | } |
315 | 2f062c72 | ths | } |
316 | 2f062c72 | ths | |
317 | 2f062c72 | ths | static void sh_serial_receive_break(sh_serial_state *s) |
318 | 2f062c72 | ths | { |
319 | 63242a00 | aurel32 | if (s->feat & SH_SERIAL_FEAT_SCIF)
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320 | 63242a00 | aurel32 | s->sr |= (1 << 4); |
321 | 2f062c72 | ths | } |
322 | 2f062c72 | ths | |
323 | 2f062c72 | ths | static int sh_serial_can_receive1(void *opaque) |
324 | 2f062c72 | ths | { |
325 | 2f062c72 | ths | sh_serial_state *s = opaque; |
326 | 2f062c72 | ths | return sh_serial_can_receive(s);
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327 | 2f062c72 | ths | } |
328 | 2f062c72 | ths | |
329 | 2f062c72 | ths | static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) |
330 | 2f062c72 | ths | { |
331 | 2f062c72 | ths | sh_serial_state *s = opaque; |
332 | 2f062c72 | ths | sh_serial_receive_byte(s, buf[0]);
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333 | 2f062c72 | ths | } |
334 | 2f062c72 | ths | |
335 | 2f062c72 | ths | static void sh_serial_event(void *opaque, int event) |
336 | 2f062c72 | ths | { |
337 | 2f062c72 | ths | sh_serial_state *s = opaque; |
338 | 2f062c72 | ths | if (event == CHR_EVENT_BREAK)
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339 | 2f062c72 | ths | sh_serial_receive_break(s); |
340 | 2f062c72 | ths | } |
341 | 2f062c72 | ths | |
342 | 9596ebb7 | pbrook | static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr) |
343 | 2f062c72 | ths | { |
344 | 2f062c72 | ths | sh_serial_state *s = opaque; |
345 | 8da3ff18 | pbrook | return sh_serial_ioport_read(s, addr);
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346 | 2f062c72 | ths | } |
347 | 2f062c72 | ths | |
348 | 9596ebb7 | pbrook | static void sh_serial_write (void *opaque, |
349 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
350 | 2f062c72 | ths | { |
351 | 2f062c72 | ths | sh_serial_state *s = opaque; |
352 | 8da3ff18 | pbrook | sh_serial_ioport_write(s, addr, value); |
353 | 2f062c72 | ths | } |
354 | 2f062c72 | ths | |
355 | 2f062c72 | ths | static CPUReadMemoryFunc *sh_serial_readfn[] = {
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356 | 2f062c72 | ths | &sh_serial_read, |
357 | 2f062c72 | ths | &sh_serial_read, |
358 | 2f062c72 | ths | &sh_serial_read, |
359 | 2f062c72 | ths | }; |
360 | 2f062c72 | ths | |
361 | 2f062c72 | ths | static CPUWriteMemoryFunc *sh_serial_writefn[] = {
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362 | 2f062c72 | ths | &sh_serial_write, |
363 | 2f062c72 | ths | &sh_serial_write, |
364 | 2f062c72 | ths | &sh_serial_write, |
365 | 2f062c72 | ths | }; |
366 | 2f062c72 | ths | |
367 | 2f062c72 | ths | void sh_serial_init (target_phys_addr_t base, int feat, |
368 | bf5b7423 | aurel32 | uint32_t freq, CharDriverState *chr, |
369 | 4e7ed2d1 | aurel32 | qemu_irq eri_source, |
370 | 4e7ed2d1 | aurel32 | qemu_irq rxi_source, |
371 | 4e7ed2d1 | aurel32 | qemu_irq txi_source, |
372 | 4e7ed2d1 | aurel32 | qemu_irq tei_source, |
373 | 4e7ed2d1 | aurel32 | qemu_irq bri_source) |
374 | 2f062c72 | ths | { |
375 | 2f062c72 | ths | sh_serial_state *s; |
376 | 2f062c72 | ths | int s_io_memory;
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377 | 2f062c72 | ths | |
378 | 2f062c72 | ths | s = qemu_mallocz(sizeof(sh_serial_state));
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379 | 2f062c72 | ths | if (!s)
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380 | 2f062c72 | ths | return;
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381 | 2f062c72 | ths | |
382 | 2f062c72 | ths | s->feat = feat; |
383 | 2f062c72 | ths | s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; |
384 | 63242a00 | aurel32 | s->rtrg = 1;
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385 | 2f062c72 | ths | |
386 | 2f062c72 | ths | s->smr = 0;
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387 | 2f062c72 | ths | s->brr = 0xff;
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388 | b7d35e65 | balrog | s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ |
389 | 2f062c72 | ths | s->sptr = 0;
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390 | 2f062c72 | ths | |
391 | 2f062c72 | ths | if (feat & SH_SERIAL_FEAT_SCIF) {
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392 | 2f062c72 | ths | s->fcr = 0;
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393 | 2f062c72 | ths | } |
394 | 2f062c72 | ths | else {
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395 | 2f062c72 | ths | s->dr = 0xff;
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396 | 2f062c72 | ths | } |
397 | 2f062c72 | ths | |
398 | 63242a00 | aurel32 | sh_serial_clear_fifo(s); |
399 | 2f062c72 | ths | |
400 | 2f062c72 | ths | s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
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401 | 2f062c72 | ths | sh_serial_writefn, s); |
402 | 5c16736a | balrog | cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
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403 | 5c16736a | balrog | cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
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404 | 2f062c72 | ths | |
405 | 2f062c72 | ths | s->chr = chr; |
406 | 2f062c72 | ths | |
407 | 2f062c72 | ths | if (chr)
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408 | 2f062c72 | ths | qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1, |
409 | 2f062c72 | ths | sh_serial_event, s); |
410 | bf5b7423 | aurel32 | |
411 | bf5b7423 | aurel32 | s->eri = eri_source; |
412 | bf5b7423 | aurel32 | s->rxi = rxi_source; |
413 | bf5b7423 | aurel32 | s->txi = txi_source; |
414 | bf5b7423 | aurel32 | s->tei = tei_source; |
415 | bf5b7423 | aurel32 | s->bri = bri_source; |
416 | 2f062c72 | ths | } |