Revision 5c16736a
| b/hw/sh.h | ||
|---|---|---|
| 4 | 4 |
|
| 5 | 5 |
#include "sh_intc.h" |
| 6 | 6 |
|
| 7 |
#define A7ADDR(x) ((x) & 0x1fffffff) |
|
| 8 |
#define P4ADDR(x) ((x) | 0xe0000000) |
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| 9 |
|
|
| 7 | 10 |
/* sh7750.c */ |
| 8 | 11 |
struct SH7750State; |
| 9 | 12 |
|
| b/hw/sh7750.c | ||
|---|---|---|
| 683 | 683 |
sh7750_mem_write, s); |
| 684 | 684 |
cpu_register_physical_memory_offset(0x1f000000, 0x1000, |
| 685 | 685 |
sh7750_io_memory, 0x1f000000); |
| 686 |
cpu_register_physical_memory_offset(0xff000000, 0x1000, |
|
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sh7750_io_memory, 0x1f000000); |
|
| 686 | 688 |
cpu_register_physical_memory_offset(0x1f800000, 0x1000, |
| 687 | 689 |
sh7750_io_memory, 0x1f800000); |
| 690 |
cpu_register_physical_memory_offset(0xff800000, 0x1000, |
|
| 691 |
sh7750_io_memory, 0x1f800000); |
|
| 688 | 692 |
cpu_register_physical_memory_offset(0x1fc00000, 0x1000, |
| 689 | 693 |
sh7750_io_memory, 0x1fc00000); |
| 694 |
cpu_register_physical_memory_offset(0xffc00000, 0x1000, |
|
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sh7750_io_memory, 0x1fc00000); |
|
| 690 | 696 |
|
| 691 | 697 |
sh7750_mm_cache_and_tlb = cpu_register_io_memory(0, |
| 692 | 698 |
sh7750_mmct_read, |
| b/hw/sh_intc.c | ||
|---|---|---|
| 307 | 307 |
static void sh_intc_register(struct intc_desc *desc, |
| 308 | 308 |
unsigned long address) |
| 309 | 309 |
{
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if (address) |
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cpu_register_physical_memory_offset(INTC_A7(address), 4,
|
|
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if (address) {
|
|
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cpu_register_physical_memory_offset(P4ADDR(address), 4,
|
|
| 312 | 312 |
desc->iomemtype, INTC_A7(address)); |
| 313 |
cpu_register_physical_memory_offset(A7ADDR(address), 4, |
|
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desc->iomemtype, INTC_A7(address)); |
|
| 315 |
} |
|
| 313 | 316 |
} |
| 314 | 317 |
|
| 315 | 318 |
static void sh_intc_register_source(struct intc_desc *desc, |
| b/hw/sh_serial.c | ||
|---|---|---|
| 399 | 399 |
|
| 400 | 400 |
s_io_memory = cpu_register_io_memory(0, sh_serial_readfn, |
| 401 | 401 |
sh_serial_writefn, s); |
| 402 |
cpu_register_physical_memory(base, 0x28, s_io_memory); |
|
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cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory); |
|
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cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory); |
|
| 403 | 404 |
|
| 404 | 405 |
s->chr = chr; |
| 405 | 406 |
|
| b/hw/sh_timer.c | ||
|---|---|---|
| 320 | 320 |
ch2_irq0); /* ch2_irq1 not supported */ |
| 321 | 321 |
iomemtype = cpu_register_io_memory(0, tmu012_readfn, |
| 322 | 322 |
tmu012_writefn, s); |
| 323 |
cpu_register_physical_memory(base, 0x00001000, iomemtype); |
|
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cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype); |
|
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cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype); |
|
| 324 | 325 |
/* ??? Save/restore. */ |
| 325 | 326 |
} |
| b/target-sh4/helper.c | ||
|---|---|---|
| 439 | 439 |
if (address >= 0x80000000 && address < 0xc0000000) {
|
| 440 | 440 |
/* Mask upper 3 bits for P1 and P2 areas */ |
| 441 | 441 |
*physical = address & 0x1fffffff; |
| 442 |
} else if (address >= 0xfd000000 && address < 0xfe000000) {
|
|
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/* PCI memory space */ |
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*physical = address; |
|
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} else if (address >= 0xfc000000) {
|
|
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/* |
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* Mask upper 3 bits for control registers in P4 area, |
|
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* to unify access to control registers via P0-P3 area. |
|
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* The addresses for cache store queue, TLB address array |
|
| 450 |
* are not masked. |
|
| 451 |
*/ |
|
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*physical = address & 0x1fffffff; |
|
| 453 | 442 |
} else {
|
| 454 |
/* access to cache store queue, or TLB address array. */ |
|
| 455 | 443 |
*physical = address; |
| 456 | 444 |
} |
| 457 | 445 |
*prot = PAGE_READ | PAGE_WRITE; |
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