Revision 5c16736a target-sh4/helper.c

b/target-sh4/helper.c
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	if (address >= 0x80000000 && address < 0xc0000000) {
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	    /* Mask upper 3 bits for P1 and P2 areas */
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	    *physical = address & 0x1fffffff;
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        } else if (address >= 0xfd000000 && address < 0xfe000000) {
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            /* PCI memory space */
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            *physical = address;
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	} else if (address >= 0xfc000000) {
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	    /*
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	     * Mask upper 3 bits for control registers in P4 area,
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	     * to unify access to control registers via P0-P3 area.
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	     * The addresses for cache store queue, TLB address array
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	     * are not masked.
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	     */
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	*physical = address & 0x1fffffff;
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	} else {
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	    /* access to cache store queue, or TLB address array. */
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	    *physical = address;
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	}
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	*prot = PAGE_READ | PAGE_WRITE;

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