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/*
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* TI OMAP processors emulation.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "vl.h" |
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#include "arm_pic.h" |
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/* Should signal the TCMI */
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uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
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{ |
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OMAP_8B_REG(addr); |
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return 0; |
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} |
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void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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OMAP_8B_REG(addr); |
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} |
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uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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{ |
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OMAP_16B_REG(addr); |
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return 0; |
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} |
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void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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OMAP_16B_REG(addr); |
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} |
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uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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{ |
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OMAP_32B_REG(addr); |
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return 0; |
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} |
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|
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void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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OMAP_32B_REG(addr); |
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} |
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|
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/* Interrupt Handlers */
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struct omap_intr_handler_s {
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qemu_irq *pins; |
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qemu_irq *parent_pic; |
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target_phys_addr_t base; |
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|
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/* state */
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uint32_t irqs; |
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uint32_t mask; |
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uint32_t sens_edge; |
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uint32_t fiq; |
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int priority[32]; |
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uint32_t new_irq_agr; |
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uint32_t new_fiq_agr; |
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int sir_irq;
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int sir_fiq;
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int stats[32]; |
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}; |
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|
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static void omap_inth_update(struct omap_intr_handler_s *s) |
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{ |
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uint32_t irq = s->irqs & ~s->mask & ~s->fiq; |
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uint32_t fiq = s->irqs & ~s->mask & s->fiq; |
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if (s->new_irq_agr || !irq) {
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qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq); |
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if (irq)
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s->new_irq_agr = 0;
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} |
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if (s->new_fiq_agr || !irq) {
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qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq); |
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if (fiq)
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s->new_fiq_agr = 0;
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} |
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} |
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static void omap_inth_sir_update(struct omap_intr_handler_s *s) |
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{ |
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int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
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uint32_t level = s->irqs & ~s->mask; |
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intr_irq = 0;
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intr_fiq = 0;
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p_irq = -1;
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p_fiq = -1;
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/* Find the interrupt line with the highest dynamic priority */
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for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) { |
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p = s->priority[i]; |
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if (s->fiq & (1 << i)) { |
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if (p > p_fiq) {
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p_fiq = p; |
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intr_fiq = i; |
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} |
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} else {
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if (p > p_irq) {
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p_irq = p; |
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intr_irq = i; |
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} |
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} |
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f = ffs(level >> 1);
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} |
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s->sir_irq = intr_irq; |
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s->sir_fiq = intr_fiq; |
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} |
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#define INT_FALLING_EDGE 0 |
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#define INT_LOW_LEVEL 1 |
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|
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static void omap_set_intr(void *opaque, int irq, int req) |
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{ |
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struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
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uint32_t rise; |
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if (req) {
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rise = ~ih->irqs & (1 << irq);
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ih->irqs |= rise; |
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ih->stats[irq] += !!rise; |
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} else {
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rise = ih->sens_edge & ih->irqs & (1 << irq);
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ih->irqs &= ~rise; |
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} |
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if (rise & ~ih->mask) {
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omap_inth_sir_update(ih); |
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omap_inth_update(ih); |
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} |
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} |
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static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
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{ |
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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int i, offset = addr - s->base;
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switch (offset) {
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case 0x00: /* ITR */ |
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return s->irqs;
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case 0x04: /* MIR */ |
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return s->mask;
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case 0x10: /* SIR_IRQ_CODE */ |
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i = s->sir_irq; |
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if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
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s->irqs &= ~(1 << i);
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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} |
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return i;
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case 0x14: /* SIR_FIQ_CODE */ |
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i = s->sir_fiq; |
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if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) { |
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s->irqs &= ~(1 << i);
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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} |
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return i;
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case 0x18: /* CONTROL_REG */ |
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return 0; |
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case 0x1c: /* ILR0 */ |
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case 0x20: /* ILR1 */ |
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case 0x24: /* ILR2 */ |
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case 0x28: /* ILR3 */ |
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case 0x2c: /* ILR4 */ |
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case 0x30: /* ILR5 */ |
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case 0x34: /* ILR6 */ |
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case 0x38: /* ILR7 */ |
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case 0x3c: /* ILR8 */ |
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case 0x40: /* ILR9 */ |
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case 0x44: /* ILR10 */ |
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case 0x48: /* ILR11 */ |
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case 0x4c: /* ILR12 */ |
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case 0x50: /* ILR13 */ |
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case 0x54: /* ILR14 */ |
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case 0x58: /* ILR15 */ |
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case 0x5c: /* ILR16 */ |
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case 0x60: /* ILR17 */ |
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case 0x64: /* ILR18 */ |
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case 0x68: /* ILR19 */ |
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case 0x6c: /* ILR20 */ |
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case 0x70: /* ILR21 */ |
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case 0x74: /* ILR22 */ |
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case 0x78: /* ILR23 */ |
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case 0x7c: /* ILR24 */ |
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case 0x80: /* ILR25 */ |
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case 0x84: /* ILR26 */ |
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case 0x88: /* ILR27 */ |
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case 0x8c: /* ILR28 */ |
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case 0x90: /* ILR29 */ |
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case 0x94: /* ILR30 */ |
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case 0x98: /* ILR31 */ |
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i = (offset - 0x1c) >> 2; |
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return (s->priority[i] << 2) | |
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(((s->sens_edge >> i) & 1) << 1) | |
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((s->fiq >> i) & 1);
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|
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case 0x9c: /* ISR */ |
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return 0x00000000; |
225 |
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default:
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OMAP_BAD_REG(addr); |
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break;
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} |
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return 0; |
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} |
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static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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int i, offset = addr - s->base;
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switch (offset) {
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case 0x00: /* ITR */ |
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s->irqs &= value; |
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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return;
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|
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case 0x04: /* MIR */ |
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s->mask = value; |
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omap_inth_sir_update(s); |
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omap_inth_update(s); |
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return;
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|
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case 0x10: /* SIR_IRQ_CODE */ |
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case 0x14: /* SIR_FIQ_CODE */ |
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OMAP_RO_REG(addr); |
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break;
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|
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case 0x18: /* CONTROL_REG */ |
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if (value & 2) |
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s->new_fiq_agr = ~0;
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if (value & 1) |
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s->new_irq_agr = ~0;
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omap_inth_update(s); |
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return;
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|
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case 0x1c: /* ILR0 */ |
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case 0x20: /* ILR1 */ |
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case 0x24: /* ILR2 */ |
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case 0x28: /* ILR3 */ |
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case 0x2c: /* ILR4 */ |
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case 0x30: /* ILR5 */ |
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case 0x34: /* ILR6 */ |
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case 0x38: /* ILR7 */ |
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case 0x3c: /* ILR8 */ |
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case 0x40: /* ILR9 */ |
275 |
case 0x44: /* ILR10 */ |
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case 0x48: /* ILR11 */ |
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case 0x4c: /* ILR12 */ |
278 |
case 0x50: /* ILR13 */ |
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case 0x54: /* ILR14 */ |
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case 0x58: /* ILR15 */ |
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case 0x5c: /* ILR16 */ |
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case 0x60: /* ILR17 */ |
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case 0x64: /* ILR18 */ |
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case 0x68: /* ILR19 */ |
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case 0x6c: /* ILR20 */ |
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case 0x70: /* ILR21 */ |
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case 0x74: /* ILR22 */ |
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case 0x78: /* ILR23 */ |
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case 0x7c: /* ILR24 */ |
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case 0x80: /* ILR25 */ |
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case 0x84: /* ILR26 */ |
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case 0x88: /* ILR27 */ |
293 |
case 0x8c: /* ILR28 */ |
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case 0x90: /* ILR29 */ |
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case 0x94: /* ILR30 */ |
296 |
case 0x98: /* ILR31 */ |
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i = (offset - 0x1c) >> 2; |
298 |
s->priority[i] = (value >> 2) & 0x1f; |
299 |
s->sens_edge &= ~(1 << i);
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s->sens_edge |= ((value >> 1) & 1) << i; |
301 |
s->fiq &= ~(1 << i);
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s->fiq |= (value & 1) << i;
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return;
|
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|
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case 0x9c: /* ISR */ |
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for (i = 0; i < 32; i ++) |
307 |
if (value & (1 << i)) { |
308 |
omap_set_intr(s, i, 1);
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return;
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} |
311 |
return;
|
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|
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default:
|
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OMAP_BAD_REG(addr); |
315 |
} |
316 |
} |
317 |
|
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static CPUReadMemoryFunc *omap_inth_readfn[] = {
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omap_badwidth_read32, |
320 |
omap_badwidth_read32, |
321 |
omap_inth_read, |
322 |
}; |
323 |
|
324 |
static CPUWriteMemoryFunc *omap_inth_writefn[] = {
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omap_inth_write, |
326 |
omap_inth_write, |
327 |
omap_inth_write, |
328 |
}; |
329 |
|
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static void omap_inth_reset(struct omap_intr_handler_s *s) |
331 |
{ |
332 |
s->irqs = 0x00000000;
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s->mask = 0xffffffff;
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s->sens_edge = 0x00000000;
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s->fiq = 0x00000000;
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memset(s->priority, 0, sizeof(s->priority)); |
337 |
s->new_irq_agr = ~0;
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s->new_fiq_agr = ~0;
|
339 |
s->sir_irq = 0;
|
340 |
s->sir_fiq = 0;
|
341 |
|
342 |
omap_inth_update(s); |
343 |
} |
344 |
|
345 |
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
|
346 |
unsigned long size, qemu_irq parent[2], omap_clk clk) |
347 |
{ |
348 |
int iomemtype;
|
349 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
350 |
qemu_mallocz(sizeof(struct omap_intr_handler_s)); |
351 |
|
352 |
s->parent_pic = parent; |
353 |
s->base = base; |
354 |
s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
|
355 |
omap_inth_reset(s); |
356 |
|
357 |
iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
|
358 |
omap_inth_writefn, s); |
359 |
cpu_register_physical_memory(s->base, size, iomemtype); |
360 |
|
361 |
return s;
|
362 |
} |
363 |
|
364 |
/* OMAP1 DMA module */
|
365 |
typedef enum { |
366 |
constant = 0,
|
367 |
post_incremented, |
368 |
single_index, |
369 |
double_index, |
370 |
} omap_dma_addressing_t; |
371 |
|
372 |
struct omap_dma_channel_s {
|
373 |
int burst[2]; |
374 |
int pack[2]; |
375 |
enum omap_dma_port port[2]; |
376 |
target_phys_addr_t addr[2];
|
377 |
omap_dma_addressing_t mode[2];
|
378 |
int data_type;
|
379 |
int end_prog;
|
380 |
int repeat;
|
381 |
int auto_init;
|
382 |
int priority;
|
383 |
int fs;
|
384 |
int sync;
|
385 |
int running;
|
386 |
int interrupts;
|
387 |
int status;
|
388 |
int signalled;
|
389 |
int post_sync;
|
390 |
int transfer;
|
391 |
uint16_t elements; |
392 |
uint16_t frames; |
393 |
uint16_t frame_index; |
394 |
uint16_t element_index; |
395 |
uint16_t cpc; |
396 |
|
397 |
struct omap_dma_reg_set_s {
|
398 |
target_phys_addr_t src, dest; |
399 |
int frame;
|
400 |
int element;
|
401 |
int frame_delta[2]; |
402 |
int elem_delta[2]; |
403 |
int frames;
|
404 |
int elements;
|
405 |
} active_set; |
406 |
}; |
407 |
|
408 |
struct omap_dma_s {
|
409 |
qemu_irq *ih; |
410 |
QEMUTimer *tm; |
411 |
struct omap_mpu_state_s *mpu;
|
412 |
target_phys_addr_t base; |
413 |
omap_clk clk; |
414 |
int64_t delay; |
415 |
uint32_t drq; |
416 |
|
417 |
uint16_t gcr; |
418 |
int run_count;
|
419 |
|
420 |
int chans;
|
421 |
struct omap_dma_channel_s ch[16]; |
422 |
struct omap_dma_lcd_channel_s lcd_ch;
|
423 |
}; |
424 |
|
425 |
static void omap_dma_interrupts_update(struct omap_dma_s *s) |
426 |
{ |
427 |
/* First three interrupts are shared between two channels each. */
|
428 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6], |
429 |
(s->ch[0].status | s->ch[6].status) & 0x3f); |
430 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7], |
431 |
(s->ch[1].status | s->ch[7].status) & 0x3f); |
432 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8], |
433 |
(s->ch[2].status | s->ch[8].status) & 0x3f); |
434 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH3], |
435 |
(s->ch[3].status) & 0x3f); |
436 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH4], |
437 |
(s->ch[4].status) & 0x3f); |
438 |
qemu_set_irq(s->ih[OMAP_INT_DMA_CH5], |
439 |
(s->ch[5].status) & 0x3f); |
440 |
} |
441 |
|
442 |
static void omap_dma_channel_load(struct omap_dma_s *s, int ch) |
443 |
{ |
444 |
struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
|
445 |
int i;
|
446 |
|
447 |
/*
|
448 |
* TODO: verify address ranges and alignment
|
449 |
* TODO: port endianness
|
450 |
*/
|
451 |
|
452 |
a->src = s->ch[ch].addr[0];
|
453 |
a->dest = s->ch[ch].addr[1];
|
454 |
a->frames = s->ch[ch].frames; |
455 |
a->elements = s->ch[ch].elements; |
456 |
a->frame = 0;
|
457 |
a->element = 0;
|
458 |
|
459 |
if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
|
460 |
printf("%s: bad DMA request\n", __FUNCTION__);
|
461 |
return;
|
462 |
} |
463 |
|
464 |
for (i = 0; i < 2; i ++) |
465 |
switch (s->ch[ch].mode[i]) {
|
466 |
case constant:
|
467 |
a->elem_delta[i] = 0;
|
468 |
a->frame_delta[i] = 0;
|
469 |
break;
|
470 |
case post_incremented:
|
471 |
a->elem_delta[i] = s->ch[ch].data_type; |
472 |
a->frame_delta[i] = 0;
|
473 |
break;
|
474 |
case single_index:
|
475 |
a->elem_delta[i] = s->ch[ch].data_type + |
476 |
s->ch[ch].element_index - 1;
|
477 |
if (s->ch[ch].element_index > 0x7fff) |
478 |
a->elem_delta[i] -= 0x10000;
|
479 |
a->frame_delta[i] = 0;
|
480 |
break;
|
481 |
case double_index:
|
482 |
a->elem_delta[i] = s->ch[ch].data_type + |
483 |
s->ch[ch].element_index - 1;
|
484 |
if (s->ch[ch].element_index > 0x7fff) |
485 |
a->elem_delta[i] -= 0x10000;
|
486 |
a->frame_delta[i] = s->ch[ch].frame_index - |
487 |
s->ch[ch].element_index; |
488 |
if (s->ch[ch].frame_index > 0x7fff) |
489 |
a->frame_delta[i] -= 0x10000;
|
490 |
break;
|
491 |
default:
|
492 |
break;
|
493 |
} |
494 |
} |
495 |
|
496 |
static inline void omap_dma_request_run(struct omap_dma_s *s, |
497 |
int channel, int request) |
498 |
{ |
499 |
next_channel:
|
500 |
if (request > 0) |
501 |
for (; channel < 9; channel ++) |
502 |
if (s->ch[channel].sync == request && s->ch[channel].running)
|
503 |
break;
|
504 |
if (channel >= 9) |
505 |
return;
|
506 |
|
507 |
if (s->ch[channel].transfer) {
|
508 |
if (request > 0) { |
509 |
s->ch[channel ++].post_sync = request; |
510 |
goto next_channel;
|
511 |
} |
512 |
s->ch[channel].status |= 0x02; /* Synchronisation drop */ |
513 |
omap_dma_interrupts_update(s); |
514 |
return;
|
515 |
} |
516 |
|
517 |
if (!s->ch[channel].signalled)
|
518 |
s->run_count ++; |
519 |
s->ch[channel].signalled = 1;
|
520 |
|
521 |
if (request > 0) |
522 |
s->ch[channel].status |= 0x40; /* External request */ |
523 |
|
524 |
if (s->delay && !qemu_timer_pending(s->tm))
|
525 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
526 |
|
527 |
if (request > 0) { |
528 |
channel ++; |
529 |
goto next_channel;
|
530 |
} |
531 |
} |
532 |
|
533 |
static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel) |
534 |
{ |
535 |
if (s->ch[channel].signalled)
|
536 |
s->run_count --; |
537 |
s->ch[channel].signalled = 0;
|
538 |
|
539 |
if (!s->run_count)
|
540 |
qemu_del_timer(s->tm); |
541 |
} |
542 |
|
543 |
static void omap_dma_channel_run(struct omap_dma_s *s) |
544 |
{ |
545 |
int ch;
|
546 |
uint16_t status; |
547 |
uint8_t value[4];
|
548 |
struct omap_dma_port_if_s *src_p, *dest_p;
|
549 |
struct omap_dma_reg_set_s *a;
|
550 |
|
551 |
for (ch = 0; ch < 9; ch ++) { |
552 |
a = &s->ch[ch].active_set; |
553 |
|
554 |
src_p = &s->mpu->port[s->ch[ch].port[0]];
|
555 |
dest_p = &s->mpu->port[s->ch[ch].port[1]];
|
556 |
if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
|
557 |
!dest_p->addr_valid(s->mpu, a->dest))) { |
558 |
#if 0
|
559 |
/* Bus time-out */
|
560 |
if (s->ch[ch].interrupts & 0x01)
|
561 |
s->ch[ch].status |= 0x01;
|
562 |
omap_dma_request_stop(s, ch);
|
563 |
continue;
|
564 |
#endif
|
565 |
printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
|
566 |
} |
567 |
|
568 |
status = s->ch[ch].status; |
569 |
while (status == s->ch[ch].status && s->ch[ch].signalled) {
|
570 |
/* Transfer a single element */
|
571 |
s->ch[ch].transfer = 1;
|
572 |
cpu_physical_memory_read(a->src, value, s->ch[ch].data_type); |
573 |
cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type); |
574 |
s->ch[ch].transfer = 0;
|
575 |
|
576 |
a->src += a->elem_delta[0];
|
577 |
a->dest += a->elem_delta[1];
|
578 |
a->element ++; |
579 |
|
580 |
/* Check interrupt conditions */
|
581 |
if (a->element == a->elements) {
|
582 |
a->element = 0;
|
583 |
a->src += a->frame_delta[0];
|
584 |
a->dest += a->frame_delta[1];
|
585 |
a->frame ++; |
586 |
|
587 |
if (a->frame == a->frames) {
|
588 |
if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
|
589 |
s->ch[ch].running = 0;
|
590 |
|
591 |
if (s->ch[ch].auto_init &&
|
592 |
(s->ch[ch].repeat || |
593 |
s->ch[ch].end_prog)) |
594 |
omap_dma_channel_load(s, ch); |
595 |
|
596 |
if (s->ch[ch].interrupts & 0x20) |
597 |
s->ch[ch].status |= 0x20;
|
598 |
|
599 |
if (!s->ch[ch].sync)
|
600 |
omap_dma_request_stop(s, ch); |
601 |
} |
602 |
|
603 |
if (s->ch[ch].interrupts & 0x08) |
604 |
s->ch[ch].status |= 0x08;
|
605 |
|
606 |
if (s->ch[ch].sync && s->ch[ch].fs &&
|
607 |
!(s->drq & (1 << s->ch[ch].sync))) {
|
608 |
s->ch[ch].status &= ~0x40;
|
609 |
omap_dma_request_stop(s, ch); |
610 |
} |
611 |
} |
612 |
|
613 |
if (a->element == 1 && a->frame == a->frames - 1) |
614 |
if (s->ch[ch].interrupts & 0x10) |
615 |
s->ch[ch].status |= 0x10;
|
616 |
|
617 |
if (a->element == (a->elements >> 1)) |
618 |
if (s->ch[ch].interrupts & 0x04) |
619 |
s->ch[ch].status |= 0x04;
|
620 |
|
621 |
if (s->ch[ch].sync && !s->ch[ch].fs &&
|
622 |
!(s->drq & (1 << s->ch[ch].sync))) {
|
623 |
s->ch[ch].status &= ~0x40;
|
624 |
omap_dma_request_stop(s, ch); |
625 |
} |
626 |
|
627 |
/*
|
628 |
* Process requests made while the element was
|
629 |
* being transferred.
|
630 |
*/
|
631 |
if (s->ch[ch].post_sync) {
|
632 |
omap_dma_request_run(s, 0, s->ch[ch].post_sync);
|
633 |
s->ch[ch].post_sync = 0;
|
634 |
} |
635 |
|
636 |
#if 0
|
637 |
break;
|
638 |
#endif
|
639 |
} |
640 |
|
641 |
s->ch[ch].cpc = a->dest & 0x0000ffff;
|
642 |
} |
643 |
|
644 |
omap_dma_interrupts_update(s); |
645 |
if (s->run_count && s->delay)
|
646 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
647 |
} |
648 |
|
649 |
static int omap_dma_ch_reg_read(struct omap_dma_s *s, |
650 |
int ch, int reg, uint16_t *value) { |
651 |
switch (reg) {
|
652 |
case 0x00: /* SYS_DMA_CSDP_CH0 */ |
653 |
*value = (s->ch[ch].burst[1] << 14) | |
654 |
(s->ch[ch].pack[1] << 13) | |
655 |
(s->ch[ch].port[1] << 9) | |
656 |
(s->ch[ch].burst[0] << 7) | |
657 |
(s->ch[ch].pack[0] << 6) | |
658 |
(s->ch[ch].port[0] << 2) | |
659 |
(s->ch[ch].data_type >> 1);
|
660 |
break;
|
661 |
|
662 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
663 |
*value = (s->ch[ch].mode[1] << 14) | |
664 |
(s->ch[ch].mode[0] << 12) | |
665 |
(s->ch[ch].end_prog << 11) |
|
666 |
(s->ch[ch].repeat << 9) |
|
667 |
(s->ch[ch].auto_init << 8) |
|
668 |
(s->ch[ch].running << 7) |
|
669 |
(s->ch[ch].priority << 6) |
|
670 |
(s->ch[ch].fs << 5) | s->ch[ch].sync;
|
671 |
break;
|
672 |
|
673 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
674 |
*value = s->ch[ch].interrupts; |
675 |
break;
|
676 |
|
677 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
678 |
/* FIXME: shared CSR for channels sharing the interrupts */
|
679 |
*value = s->ch[ch].status; |
680 |
s->ch[ch].status &= 0x40;
|
681 |
omap_dma_interrupts_update(s); |
682 |
break;
|
683 |
|
684 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
685 |
*value = s->ch[ch].addr[0] & 0x0000ffff; |
686 |
break;
|
687 |
|
688 |
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
689 |
*value = s->ch[ch].addr[0] >> 16; |
690 |
break;
|
691 |
|
692 |
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
693 |
*value = s->ch[ch].addr[1] & 0x0000ffff; |
694 |
break;
|
695 |
|
696 |
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
697 |
*value = s->ch[ch].addr[1] >> 16; |
698 |
break;
|
699 |
|
700 |
case 0x10: /* SYS_DMA_CEN_CH0 */ |
701 |
*value = s->ch[ch].elements; |
702 |
break;
|
703 |
|
704 |
case 0x12: /* SYS_DMA_CFN_CH0 */ |
705 |
*value = s->ch[ch].frames; |
706 |
break;
|
707 |
|
708 |
case 0x14: /* SYS_DMA_CFI_CH0 */ |
709 |
*value = s->ch[ch].frame_index; |
710 |
break;
|
711 |
|
712 |
case 0x16: /* SYS_DMA_CEI_CH0 */ |
713 |
*value = s->ch[ch].element_index; |
714 |
break;
|
715 |
|
716 |
case 0x18: /* SYS_DMA_CPC_CH0 */ |
717 |
*value = s->ch[ch].cpc; |
718 |
break;
|
719 |
|
720 |
default:
|
721 |
return 1; |
722 |
} |
723 |
return 0; |
724 |
} |
725 |
|
726 |
static int omap_dma_ch_reg_write(struct omap_dma_s *s, |
727 |
int ch, int reg, uint16_t value) { |
728 |
switch (reg) {
|
729 |
case 0x00: /* SYS_DMA_CSDP_CH0 */ |
730 |
s->ch[ch].burst[1] = (value & 0xc000) >> 14; |
731 |
s->ch[ch].pack[1] = (value & 0x2000) >> 13; |
732 |
s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); |
733 |
s->ch[ch].burst[0] = (value & 0x0180) >> 7; |
734 |
s->ch[ch].pack[0] = (value & 0x0040) >> 6; |
735 |
s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); |
736 |
s->ch[ch].data_type = (1 << (value & 3)); |
737 |
if (s->ch[ch].port[0] >= omap_dma_port_last) |
738 |
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
739 |
s->ch[ch].port[0]);
|
740 |
if (s->ch[ch].port[1] >= omap_dma_port_last) |
741 |
printf("%s: invalid DMA port %i\n", __FUNCTION__,
|
742 |
s->ch[ch].port[1]);
|
743 |
if ((value & 3) == 3) |
744 |
printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
|
745 |
break;
|
746 |
|
747 |
case 0x02: /* SYS_DMA_CCR_CH0 */ |
748 |
s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); |
749 |
s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); |
750 |
s->ch[ch].end_prog = (value & 0x0800) >> 11; |
751 |
s->ch[ch].repeat = (value & 0x0200) >> 9; |
752 |
s->ch[ch].auto_init = (value & 0x0100) >> 8; |
753 |
s->ch[ch].priority = (value & 0x0040) >> 6; |
754 |
s->ch[ch].fs = (value & 0x0020) >> 5; |
755 |
s->ch[ch].sync = value & 0x001f;
|
756 |
if (value & 0x0080) { |
757 |
if (s->ch[ch].running) {
|
758 |
if (!s->ch[ch].signalled &&
|
759 |
s->ch[ch].auto_init && s->ch[ch].end_prog) |
760 |
omap_dma_channel_load(s, ch); |
761 |
} else {
|
762 |
s->ch[ch].running = 1;
|
763 |
omap_dma_channel_load(s, ch); |
764 |
} |
765 |
if (!s->ch[ch].sync || (s->drq & (1 << s->ch[ch].sync))) |
766 |
omap_dma_request_run(s, ch, 0);
|
767 |
} else {
|
768 |
s->ch[ch].running = 0;
|
769 |
omap_dma_request_stop(s, ch); |
770 |
} |
771 |
break;
|
772 |
|
773 |
case 0x04: /* SYS_DMA_CICR_CH0 */ |
774 |
s->ch[ch].interrupts = value & 0x003f;
|
775 |
break;
|
776 |
|
777 |
case 0x06: /* SYS_DMA_CSR_CH0 */ |
778 |
return 1; |
779 |
|
780 |
case 0x08: /* SYS_DMA_CSSA_L_CH0 */ |
781 |
s->ch[ch].addr[0] &= 0xffff0000; |
782 |
s->ch[ch].addr[0] |= value;
|
783 |
break;
|
784 |
|
785 |
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ |
786 |
s->ch[ch].addr[0] &= 0x0000ffff; |
787 |
s->ch[ch].addr[0] |= value << 16; |
788 |
break;
|
789 |
|
790 |
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ |
791 |
s->ch[ch].addr[1] &= 0xffff0000; |
792 |
s->ch[ch].addr[1] |= value;
|
793 |
break;
|
794 |
|
795 |
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ |
796 |
s->ch[ch].addr[1] &= 0x0000ffff; |
797 |
s->ch[ch].addr[1] |= value << 16; |
798 |
break;
|
799 |
|
800 |
case 0x10: /* SYS_DMA_CEN_CH0 */ |
801 |
s->ch[ch].elements = value & 0xffff;
|
802 |
break;
|
803 |
|
804 |
case 0x12: /* SYS_DMA_CFN_CH0 */ |
805 |
s->ch[ch].frames = value & 0xffff;
|
806 |
break;
|
807 |
|
808 |
case 0x14: /* SYS_DMA_CFI_CH0 */ |
809 |
s->ch[ch].frame_index = value & 0xffff;
|
810 |
break;
|
811 |
|
812 |
case 0x16: /* SYS_DMA_CEI_CH0 */ |
813 |
s->ch[ch].element_index = value & 0xffff;
|
814 |
break;
|
815 |
|
816 |
case 0x18: /* SYS_DMA_CPC_CH0 */ |
817 |
return 1; |
818 |
|
819 |
default:
|
820 |
OMAP_BAD_REG((unsigned long) reg); |
821 |
} |
822 |
return 0; |
823 |
} |
824 |
|
825 |
static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) |
826 |
{ |
827 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
828 |
int i, reg, ch, offset = addr - s->base;
|
829 |
uint16_t ret; |
830 |
|
831 |
switch (offset) {
|
832 |
case 0x000 ... 0x2fe: |
833 |
reg = offset & 0x3f;
|
834 |
ch = (offset >> 6) & 0x0f; |
835 |
if (omap_dma_ch_reg_read(s, ch, reg, &ret))
|
836 |
break;
|
837 |
return ret;
|
838 |
|
839 |
case 0x300: /* SYS_DMA_LCD_CTRL */ |
840 |
i = s->lcd_ch.condition; |
841 |
s->lcd_ch.condition = 0;
|
842 |
qemu_irq_lower(s->lcd_ch.irq); |
843 |
return ((s->lcd_ch.src == imif) << 6) | (i << 3) | |
844 |
(s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
|
845 |
|
846 |
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
847 |
return s->lcd_ch.src_f1_top & 0xffff; |
848 |
|
849 |
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
850 |
return s->lcd_ch.src_f1_top >> 16; |
851 |
|
852 |
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
853 |
return s->lcd_ch.src_f1_bottom & 0xffff; |
854 |
|
855 |
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
856 |
return s->lcd_ch.src_f1_bottom >> 16; |
857 |
|
858 |
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
859 |
return s->lcd_ch.src_f2_top & 0xffff; |
860 |
|
861 |
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
862 |
return s->lcd_ch.src_f2_top >> 16; |
863 |
|
864 |
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
865 |
return s->lcd_ch.src_f2_bottom & 0xffff; |
866 |
|
867 |
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
868 |
return s->lcd_ch.src_f2_bottom >> 16; |
869 |
|
870 |
case 0x400: /* SYS_DMA_GCR */ |
871 |
return s->gcr;
|
872 |
} |
873 |
|
874 |
OMAP_BAD_REG(addr); |
875 |
return 0; |
876 |
} |
877 |
|
878 |
static void omap_dma_write(void *opaque, target_phys_addr_t addr, |
879 |
uint32_t value) |
880 |
{ |
881 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
882 |
int reg, ch, offset = addr - s->base;
|
883 |
|
884 |
switch (offset) {
|
885 |
case 0x000 ... 0x2fe: |
886 |
reg = offset & 0x3f;
|
887 |
ch = (offset >> 6) & 0x0f; |
888 |
if (omap_dma_ch_reg_write(s, ch, reg, value))
|
889 |
OMAP_RO_REG(addr); |
890 |
break;
|
891 |
|
892 |
case 0x300: /* SYS_DMA_LCD_CTRL */ |
893 |
s->lcd_ch.src = (value & 0x40) ? imif : emiff;
|
894 |
s->lcd_ch.condition = 0;
|
895 |
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
|
896 |
s->lcd_ch.interrupts = (value >> 1) & 1; |
897 |
s->lcd_ch.dual = value & 1;
|
898 |
break;
|
899 |
|
900 |
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ |
901 |
s->lcd_ch.src_f1_top &= 0xffff0000;
|
902 |
s->lcd_ch.src_f1_top |= 0x0000ffff & value;
|
903 |
break;
|
904 |
|
905 |
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ |
906 |
s->lcd_ch.src_f1_top &= 0x0000ffff;
|
907 |
s->lcd_ch.src_f1_top |= value << 16;
|
908 |
break;
|
909 |
|
910 |
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ |
911 |
s->lcd_ch.src_f1_bottom &= 0xffff0000;
|
912 |
s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
|
913 |
break;
|
914 |
|
915 |
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ |
916 |
s->lcd_ch.src_f1_bottom &= 0x0000ffff;
|
917 |
s->lcd_ch.src_f1_bottom |= value << 16;
|
918 |
break;
|
919 |
|
920 |
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ |
921 |
s->lcd_ch.src_f2_top &= 0xffff0000;
|
922 |
s->lcd_ch.src_f2_top |= 0x0000ffff & value;
|
923 |
break;
|
924 |
|
925 |
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ |
926 |
s->lcd_ch.src_f2_top &= 0x0000ffff;
|
927 |
s->lcd_ch.src_f2_top |= value << 16;
|
928 |
break;
|
929 |
|
930 |
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ |
931 |
s->lcd_ch.src_f2_bottom &= 0xffff0000;
|
932 |
s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
|
933 |
break;
|
934 |
|
935 |
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ |
936 |
s->lcd_ch.src_f2_bottom &= 0x0000ffff;
|
937 |
s->lcd_ch.src_f2_bottom |= value << 16;
|
938 |
break;
|
939 |
|
940 |
case 0x400: /* SYS_DMA_GCR */ |
941 |
s->gcr = value & 0x000c;
|
942 |
break;
|
943 |
|
944 |
default:
|
945 |
OMAP_BAD_REG(addr); |
946 |
} |
947 |
} |
948 |
|
949 |
static CPUReadMemoryFunc *omap_dma_readfn[] = {
|
950 |
omap_badwidth_read16, |
951 |
omap_dma_read, |
952 |
omap_badwidth_read16, |
953 |
}; |
954 |
|
955 |
static CPUWriteMemoryFunc *omap_dma_writefn[] = {
|
956 |
omap_badwidth_write16, |
957 |
omap_dma_write, |
958 |
omap_badwidth_write16, |
959 |
}; |
960 |
|
961 |
static void omap_dma_request(void *opaque, int drq, int req) |
962 |
{ |
963 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
964 |
/* The request pins are level triggered. */
|
965 |
if (req) {
|
966 |
if (~s->drq & (1 << drq)) { |
967 |
s->drq |= 1 << drq;
|
968 |
omap_dma_request_run(s, 0, drq);
|
969 |
} |
970 |
} else
|
971 |
s->drq &= ~(1 << drq);
|
972 |
} |
973 |
|
974 |
static void omap_dma_clk_update(void *opaque, int line, int on) |
975 |
{ |
976 |
struct omap_dma_s *s = (struct omap_dma_s *) opaque; |
977 |
|
978 |
if (on) {
|
979 |
s->delay = ticks_per_sec >> 5;
|
980 |
if (s->run_count)
|
981 |
qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay); |
982 |
} else {
|
983 |
s->delay = 0;
|
984 |
qemu_del_timer(s->tm); |
985 |
} |
986 |
} |
987 |
|
988 |
static void omap_dma_reset(struct omap_dma_s *s) |
989 |
{ |
990 |
int i;
|
991 |
|
992 |
qemu_del_timer(s->tm); |
993 |
s->gcr = 0x0004;
|
994 |
s->drq = 0x00000000;
|
995 |
s->run_count = 0;
|
996 |
s->lcd_ch.src = emiff; |
997 |
s->lcd_ch.condition = 0;
|
998 |
s->lcd_ch.interrupts = 0;
|
999 |
s->lcd_ch.dual = 0;
|
1000 |
memset(s->ch, 0, sizeof(s->ch)); |
1001 |
for (i = 0; i < s->chans; i ++) |
1002 |
s->ch[i].interrupts = 0x0003;
|
1003 |
} |
1004 |
|
1005 |
struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
|
1006 |
qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
|
1007 |
{ |
1008 |
int iomemtype;
|
1009 |
struct omap_dma_s *s = (struct omap_dma_s *) |
1010 |
qemu_mallocz(sizeof(struct omap_dma_s)); |
1011 |
|
1012 |
s->ih = pic; |
1013 |
s->base = base; |
1014 |
s->chans = 9;
|
1015 |
s->mpu = mpu; |
1016 |
s->clk = clk; |
1017 |
s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD]; |
1018 |
s->lcd_ch.mpu = mpu; |
1019 |
s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s); |
1020 |
omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
1021 |
mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
|
1022 |
omap_dma_reset(s); |
1023 |
omap_dma_clk_update(s, 0, 1); |
1024 |
|
1025 |
iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
|
1026 |
omap_dma_writefn, s); |
1027 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
1028 |
|
1029 |
return s;
|
1030 |
} |
1031 |
|
1032 |
/* DMA ports */
|
1033 |
int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
1034 |
target_phys_addr_t addr) |
1035 |
{ |
1036 |
return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
1037 |
} |
1038 |
|
1039 |
int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
1040 |
target_phys_addr_t addr) |
1041 |
{ |
1042 |
return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
1043 |
} |
1044 |
|
1045 |
int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
1046 |
target_phys_addr_t addr) |
1047 |
{ |
1048 |
return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
1049 |
} |
1050 |
|
1051 |
int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
1052 |
target_phys_addr_t addr) |
1053 |
{ |
1054 |
return addr >= 0xfffb0000 && addr < 0xffff0000; |
1055 |
} |
1056 |
|
1057 |
int omap_validate_local_addr(struct omap_mpu_state_s *s, |
1058 |
target_phys_addr_t addr) |
1059 |
{ |
1060 |
return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
1061 |
} |
1062 |
|
1063 |
int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
1064 |
target_phys_addr_t addr) |
1065 |
{ |
1066 |
return addr >= 0xe1010000 && addr < 0xe1020004; |
1067 |
} |
1068 |
|
1069 |
/* MPU OS timers */
|
1070 |
struct omap_mpu_timer_s {
|
1071 |
qemu_irq irq; |
1072 |
omap_clk clk; |
1073 |
target_phys_addr_t base; |
1074 |
uint32_t val; |
1075 |
int64_t time; |
1076 |
QEMUTimer *timer; |
1077 |
int64_t rate; |
1078 |
int it_ena;
|
1079 |
|
1080 |
int enable;
|
1081 |
int ptv;
|
1082 |
int ar;
|
1083 |
int st;
|
1084 |
uint32_t reset_val; |
1085 |
}; |
1086 |
|
1087 |
static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
1088 |
{ |
1089 |
uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
1090 |
|
1091 |
if (timer->st && timer->enable && timer->rate)
|
1092 |
return timer->val - muldiv64(distance >> (timer->ptv + 1), |
1093 |
timer->rate, ticks_per_sec); |
1094 |
else
|
1095 |
return timer->val;
|
1096 |
} |
1097 |
|
1098 |
static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
1099 |
{ |
1100 |
timer->val = omap_timer_read(timer); |
1101 |
timer->time = qemu_get_clock(vm_clock); |
1102 |
} |
1103 |
|
1104 |
static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
1105 |
{ |
1106 |
int64_t expires; |
1107 |
|
1108 |
if (timer->enable && timer->st && timer->rate) {
|
1109 |
timer->val = timer->reset_val; /* Should skip this on clk enable */
|
1110 |
expires = timer->time + muldiv64(timer->val << (timer->ptv + 1),
|
1111 |
ticks_per_sec, timer->rate); |
1112 |
qemu_mod_timer(timer->timer, expires); |
1113 |
} else
|
1114 |
qemu_del_timer(timer->timer); |
1115 |
} |
1116 |
|
1117 |
static void omap_timer_tick(void *opaque) |
1118 |
{ |
1119 |
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1120 |
omap_timer_sync(timer); |
1121 |
|
1122 |
if (!timer->ar) {
|
1123 |
timer->val = 0;
|
1124 |
timer->st = 0;
|
1125 |
} |
1126 |
|
1127 |
if (timer->it_ena)
|
1128 |
qemu_irq_raise(timer->irq); |
1129 |
omap_timer_update(timer); |
1130 |
} |
1131 |
|
1132 |
static void omap_timer_clk_update(void *opaque, int line, int on) |
1133 |
{ |
1134 |
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
1135 |
|
1136 |
omap_timer_sync(timer); |
1137 |
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
1138 |
omap_timer_update(timer); |
1139 |
} |
1140 |
|
1141 |
static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
1142 |
{ |
1143 |
omap_clk_adduser(timer->clk, |
1144 |
qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
1145 |
timer->rate = omap_clk_getrate(timer->clk); |
1146 |
} |
1147 |
|
1148 |
static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
1149 |
{ |
1150 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1151 |
int offset = addr - s->base;
|
1152 |
|
1153 |
switch (offset) {
|
1154 |
case 0x00: /* CNTL_TIMER */ |
1155 |
return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
1156 |
|
1157 |
case 0x04: /* LOAD_TIM */ |
1158 |
break;
|
1159 |
|
1160 |
case 0x08: /* READ_TIM */ |
1161 |
return omap_timer_read(s);
|
1162 |
} |
1163 |
|
1164 |
OMAP_BAD_REG(addr); |
1165 |
return 0; |
1166 |
} |
1167 |
|
1168 |
static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
1169 |
uint32_t value) |
1170 |
{ |
1171 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
1172 |
int offset = addr - s->base;
|
1173 |
|
1174 |
switch (offset) {
|
1175 |
case 0x00: /* CNTL_TIMER */ |
1176 |
omap_timer_sync(s); |
1177 |
s->enable = (value >> 5) & 1; |
1178 |
s->ptv = (value >> 2) & 7; |
1179 |
s->ar = (value >> 1) & 1; |
1180 |
s->st = value & 1;
|
1181 |
omap_timer_update(s); |
1182 |
return;
|
1183 |
|
1184 |
case 0x04: /* LOAD_TIM */ |
1185 |
s->reset_val = value; |
1186 |
return;
|
1187 |
|
1188 |
case 0x08: /* READ_TIM */ |
1189 |
OMAP_RO_REG(addr); |
1190 |
break;
|
1191 |
|
1192 |
default:
|
1193 |
OMAP_BAD_REG(addr); |
1194 |
} |
1195 |
} |
1196 |
|
1197 |
static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
|
1198 |
omap_badwidth_read32, |
1199 |
omap_badwidth_read32, |
1200 |
omap_mpu_timer_read, |
1201 |
}; |
1202 |
|
1203 |
static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
|
1204 |
omap_badwidth_write32, |
1205 |
omap_badwidth_write32, |
1206 |
omap_mpu_timer_write, |
1207 |
}; |
1208 |
|
1209 |
static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
1210 |
{ |
1211 |
qemu_del_timer(s->timer); |
1212 |
s->enable = 0;
|
1213 |
s->reset_val = 31337;
|
1214 |
s->val = 0;
|
1215 |
s->ptv = 0;
|
1216 |
s->ar = 0;
|
1217 |
s->st = 0;
|
1218 |
s->it_ena = 1;
|
1219 |
} |
1220 |
|
1221 |
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
1222 |
qemu_irq irq, omap_clk clk) |
1223 |
{ |
1224 |
int iomemtype;
|
1225 |
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
1226 |
qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
1227 |
|
1228 |
s->irq = irq; |
1229 |
s->clk = clk; |
1230 |
s->base = base; |
1231 |
s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
1232 |
omap_mpu_timer_reset(s); |
1233 |
omap_timer_clk_setup(s); |
1234 |
|
1235 |
iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
|
1236 |
omap_mpu_timer_writefn, s); |
1237 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
1238 |
|
1239 |
return s;
|
1240 |
} |
1241 |
|
1242 |
/* Watchdog timer */
|
1243 |
struct omap_watchdog_timer_s {
|
1244 |
struct omap_mpu_timer_s timer;
|
1245 |
uint8_t last_wr; |
1246 |
int mode;
|
1247 |
int free;
|
1248 |
int reset;
|
1249 |
}; |
1250 |
|
1251 |
static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
1252 |
{ |
1253 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1254 |
int offset = addr - s->timer.base;
|
1255 |
|
1256 |
switch (offset) {
|
1257 |
case 0x00: /* CNTL_TIMER */ |
1258 |
return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
1259 |
(s->timer.st << 7) | (s->free << 1); |
1260 |
|
1261 |
case 0x04: /* READ_TIMER */ |
1262 |
return omap_timer_read(&s->timer);
|
1263 |
|
1264 |
case 0x08: /* TIMER_MODE */ |
1265 |
return s->mode << 15; |
1266 |
} |
1267 |
|
1268 |
OMAP_BAD_REG(addr); |
1269 |
return 0; |
1270 |
} |
1271 |
|
1272 |
static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
1273 |
uint32_t value) |
1274 |
{ |
1275 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
1276 |
int offset = addr - s->timer.base;
|
1277 |
|
1278 |
switch (offset) {
|
1279 |
case 0x00: /* CNTL_TIMER */ |
1280 |
omap_timer_sync(&s->timer); |
1281 |
s->timer.ptv = (value >> 9) & 7; |
1282 |
s->timer.ar = (value >> 8) & 1; |
1283 |
s->timer.st = (value >> 7) & 1; |
1284 |
s->free = (value >> 1) & 1; |
1285 |
omap_timer_update(&s->timer); |
1286 |
break;
|
1287 |
|
1288 |
case 0x04: /* LOAD_TIMER */ |
1289 |
s->timer.reset_val = value & 0xffff;
|
1290 |
break;
|
1291 |
|
1292 |
case 0x08: /* TIMER_MODE */ |
1293 |
if (!s->mode && ((value >> 15) & 1)) |
1294 |
omap_clk_get(s->timer.clk); |
1295 |
s->mode |= (value >> 15) & 1; |
1296 |
if (s->last_wr == 0xf5) { |
1297 |
if ((value & 0xff) == 0xa0) { |
1298 |
s->mode = 0;
|
1299 |
omap_clk_put(s->timer.clk); |
1300 |
} else {
|
1301 |
/* XXX: on T|E hardware somehow this has no effect,
|
1302 |
* on Zire 71 it works as specified. */
|
1303 |
s->reset = 1;
|
1304 |
qemu_system_reset_request(); |
1305 |
} |
1306 |
} |
1307 |
s->last_wr = value & 0xff;
|
1308 |
break;
|
1309 |
|
1310 |
default:
|
1311 |
OMAP_BAD_REG(addr); |
1312 |
} |
1313 |
} |
1314 |
|
1315 |
static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
|
1316 |
omap_badwidth_read16, |
1317 |
omap_wd_timer_read, |
1318 |
omap_badwidth_read16, |
1319 |
}; |
1320 |
|
1321 |
static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
|
1322 |
omap_badwidth_write16, |
1323 |
omap_wd_timer_write, |
1324 |
omap_badwidth_write16, |
1325 |
}; |
1326 |
|
1327 |
static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
1328 |
{ |
1329 |
qemu_del_timer(s->timer.timer); |
1330 |
if (!s->mode)
|
1331 |
omap_clk_get(s->timer.clk); |
1332 |
s->mode = 1;
|
1333 |
s->free = 1;
|
1334 |
s->reset = 0;
|
1335 |
s->timer.enable = 1;
|
1336 |
s->timer.it_ena = 1;
|
1337 |
s->timer.reset_val = 0xffff;
|
1338 |
s->timer.val = 0;
|
1339 |
s->timer.st = 0;
|
1340 |
s->timer.ptv = 0;
|
1341 |
s->timer.ar = 0;
|
1342 |
omap_timer_update(&s->timer); |
1343 |
} |
1344 |
|
1345 |
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
1346 |
qemu_irq irq, omap_clk clk) |
1347 |
{ |
1348 |
int iomemtype;
|
1349 |
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
1350 |
qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
1351 |
|
1352 |
s->timer.irq = irq; |
1353 |
s->timer.clk = clk; |
1354 |
s->timer.base = base; |
1355 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1356 |
omap_wd_timer_reset(s); |
1357 |
omap_timer_clk_setup(&s->timer); |
1358 |
|
1359 |
iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
|
1360 |
omap_wd_timer_writefn, s); |
1361 |
cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
|
1362 |
|
1363 |
return s;
|
1364 |
} |
1365 |
|
1366 |
/* 32-kHz timer */
|
1367 |
struct omap_32khz_timer_s {
|
1368 |
struct omap_mpu_timer_s timer;
|
1369 |
}; |
1370 |
|
1371 |
static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
1372 |
{ |
1373 |
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1374 |
int offset = addr - s->timer.base;
|
1375 |
|
1376 |
switch (offset) {
|
1377 |
case 0x00: /* TVR */ |
1378 |
return s->timer.reset_val;
|
1379 |
|
1380 |
case 0x04: /* TCR */ |
1381 |
return omap_timer_read(&s->timer);
|
1382 |
|
1383 |
case 0x08: /* CR */ |
1384 |
return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
1385 |
|
1386 |
default:
|
1387 |
break;
|
1388 |
} |
1389 |
OMAP_BAD_REG(addr); |
1390 |
return 0; |
1391 |
} |
1392 |
|
1393 |
static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
1394 |
uint32_t value) |
1395 |
{ |
1396 |
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
1397 |
int offset = addr - s->timer.base;
|
1398 |
|
1399 |
switch (offset) {
|
1400 |
case 0x00: /* TVR */ |
1401 |
s->timer.reset_val = value & 0x00ffffff;
|
1402 |
break;
|
1403 |
|
1404 |
case 0x04: /* TCR */ |
1405 |
OMAP_RO_REG(addr); |
1406 |
break;
|
1407 |
|
1408 |
case 0x08: /* CR */ |
1409 |
s->timer.ar = (value >> 3) & 1; |
1410 |
s->timer.it_ena = (value >> 2) & 1; |
1411 |
if (s->timer.st != (value & 1) || (value & 2)) { |
1412 |
omap_timer_sync(&s->timer); |
1413 |
s->timer.enable = value & 1;
|
1414 |
s->timer.st = value & 1;
|
1415 |
omap_timer_update(&s->timer); |
1416 |
} |
1417 |
break;
|
1418 |
|
1419 |
default:
|
1420 |
OMAP_BAD_REG(addr); |
1421 |
} |
1422 |
} |
1423 |
|
1424 |
static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
|
1425 |
omap_badwidth_read32, |
1426 |
omap_badwidth_read32, |
1427 |
omap_os_timer_read, |
1428 |
}; |
1429 |
|
1430 |
static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
|
1431 |
omap_badwidth_write32, |
1432 |
omap_badwidth_write32, |
1433 |
omap_os_timer_write, |
1434 |
}; |
1435 |
|
1436 |
static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
1437 |
{ |
1438 |
qemu_del_timer(s->timer.timer); |
1439 |
s->timer.enable = 0;
|
1440 |
s->timer.it_ena = 0;
|
1441 |
s->timer.reset_val = 0x00ffffff;
|
1442 |
s->timer.val = 0;
|
1443 |
s->timer.st = 0;
|
1444 |
s->timer.ptv = 0;
|
1445 |
s->timer.ar = 1;
|
1446 |
} |
1447 |
|
1448 |
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
1449 |
qemu_irq irq, omap_clk clk) |
1450 |
{ |
1451 |
int iomemtype;
|
1452 |
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
1453 |
qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
1454 |
|
1455 |
s->timer.irq = irq; |
1456 |
s->timer.clk = clk; |
1457 |
s->timer.base = base; |
1458 |
s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
1459 |
omap_os_timer_reset(s); |
1460 |
omap_timer_clk_setup(&s->timer); |
1461 |
|
1462 |
iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
|
1463 |
omap_os_timer_writefn, s); |
1464 |
cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
|
1465 |
|
1466 |
return s;
|
1467 |
} |
1468 |
|
1469 |
/* Ultra Low-Power Device Module */
|
1470 |
static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
1471 |
{ |
1472 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1473 |
int offset = addr - s->ulpd_pm_base;
|
1474 |
uint16_t ret; |
1475 |
|
1476 |
switch (offset) {
|
1477 |
case 0x14: /* IT_STATUS */ |
1478 |
ret = s->ulpd_pm_regs[offset >> 2];
|
1479 |
s->ulpd_pm_regs[offset >> 2] = 0; |
1480 |
qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1481 |
return ret;
|
1482 |
|
1483 |
case 0x18: /* Reserved */ |
1484 |
case 0x1c: /* Reserved */ |
1485 |
case 0x20: /* Reserved */ |
1486 |
case 0x28: /* Reserved */ |
1487 |
case 0x2c: /* Reserved */ |
1488 |
OMAP_BAD_REG(addr); |
1489 |
case 0x00: /* COUNTER_32_LSB */ |
1490 |
case 0x04: /* COUNTER_32_MSB */ |
1491 |
case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1492 |
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1493 |
case 0x10: /* GAUGING_CTRL */ |
1494 |
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1495 |
case 0x30: /* CLOCK_CTRL */ |
1496 |
case 0x34: /* SOFT_REQ */ |
1497 |
case 0x38: /* COUNTER_32_FIQ */ |
1498 |
case 0x3c: /* DPLL_CTRL */ |
1499 |
case 0x40: /* STATUS_REQ */ |
1500 |
/* XXX: check clk::usecount state for every clock */
|
1501 |
case 0x48: /* LOCL_TIME */ |
1502 |
case 0x4c: /* APLL_CTRL */ |
1503 |
case 0x50: /* POWER_CTRL */ |
1504 |
return s->ulpd_pm_regs[offset >> 2]; |
1505 |
} |
1506 |
|
1507 |
OMAP_BAD_REG(addr); |
1508 |
return 0; |
1509 |
} |
1510 |
|
1511 |
static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
1512 |
uint16_t diff, uint16_t value) |
1513 |
{ |
1514 |
if (diff & (1 << 4)) /* USB_MCLK_EN */ |
1515 |
omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
1516 |
if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
1517 |
omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
1518 |
} |
1519 |
|
1520 |
static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
1521 |
uint16_t diff, uint16_t value) |
1522 |
{ |
1523 |
if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
1524 |
omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
1525 |
if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
1526 |
omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
1527 |
if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
1528 |
omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
1529 |
if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
1530 |
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
1531 |
} |
1532 |
|
1533 |
static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
1534 |
uint32_t value) |
1535 |
{ |
1536 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1537 |
int offset = addr - s->ulpd_pm_base;
|
1538 |
int64_t now, ticks; |
1539 |
int div, mult;
|
1540 |
static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1541 |
uint16_t diff; |
1542 |
|
1543 |
switch (offset) {
|
1544 |
case 0x00: /* COUNTER_32_LSB */ |
1545 |
case 0x04: /* COUNTER_32_MSB */ |
1546 |
case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
1547 |
case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
1548 |
case 0x14: /* IT_STATUS */ |
1549 |
case 0x40: /* STATUS_REQ */ |
1550 |
OMAP_RO_REG(addr); |
1551 |
break;
|
1552 |
|
1553 |
case 0x10: /* GAUGING_CTRL */ |
1554 |
/* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
1555 |
if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) { |
1556 |
now = qemu_get_clock(vm_clock); |
1557 |
|
1558 |
if (value & 1) |
1559 |
s->ulpd_gauge_start = now; |
1560 |
else {
|
1561 |
now -= s->ulpd_gauge_start; |
1562 |
|
1563 |
/* 32-kHz ticks */
|
1564 |
ticks = muldiv64(now, 32768, ticks_per_sec);
|
1565 |
s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
1566 |
s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
1567 |
if (ticks >> 32) /* OVERFLOW_32K */ |
1568 |
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
1569 |
|
1570 |
/* High frequency ticks */
|
1571 |
ticks = muldiv64(now, 12000000, ticks_per_sec);
|
1572 |
s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
1573 |
s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
1574 |
if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
1575 |
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
1576 |
|
1577 |
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
1578 |
qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
1579 |
} |
1580 |
} |
1581 |
s->ulpd_pm_regs[offset >> 2] = value;
|
1582 |
break;
|
1583 |
|
1584 |
case 0x18: /* Reserved */ |
1585 |
case 0x1c: /* Reserved */ |
1586 |
case 0x20: /* Reserved */ |
1587 |
case 0x28: /* Reserved */ |
1588 |
case 0x2c: /* Reserved */ |
1589 |
OMAP_BAD_REG(addr); |
1590 |
case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
1591 |
case 0x38: /* COUNTER_32_FIQ */ |
1592 |
case 0x48: /* LOCL_TIME */ |
1593 |
case 0x50: /* POWER_CTRL */ |
1594 |
s->ulpd_pm_regs[offset >> 2] = value;
|
1595 |
break;
|
1596 |
|
1597 |
case 0x30: /* CLOCK_CTRL */ |
1598 |
diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1599 |
s->ulpd_pm_regs[offset >> 2] = value & 0x3f; |
1600 |
omap_ulpd_clk_update(s, diff, value); |
1601 |
break;
|
1602 |
|
1603 |
case 0x34: /* SOFT_REQ */ |
1604 |
diff = s->ulpd_pm_regs[offset >> 2] ^ value;
|
1605 |
s->ulpd_pm_regs[offset >> 2] = value & 0x1f; |
1606 |
omap_ulpd_req_update(s, diff, value); |
1607 |
break;
|
1608 |
|
1609 |
case 0x3c: /* DPLL_CTRL */ |
1610 |
/* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
1611 |
* omitted altogether, probably a typo. */
|
1612 |
/* This register has identical semantics with DPLL(1:3) control
|
1613 |
* registers, see omap_dpll_write() */
|
1614 |
diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1615 |
s->ulpd_pm_regs[offset >> 2] = value & 0x2fff; |
1616 |
if (diff & (0x3ff << 2)) { |
1617 |
if (value & (1 << 4)) { /* PLL_ENABLE */ |
1618 |
div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1619 |
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1620 |
} else {
|
1621 |
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1622 |
mult = 1;
|
1623 |
} |
1624 |
omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
1625 |
} |
1626 |
|
1627 |
/* Enter the desired mode. */
|
1628 |
s->ulpd_pm_regs[offset >> 2] =
|
1629 |
(s->ulpd_pm_regs[offset >> 2] & 0xfffe) | |
1630 |
((s->ulpd_pm_regs[offset >> 2] >> 4) & 1); |
1631 |
|
1632 |
/* Act as if the lock is restored. */
|
1633 |
s->ulpd_pm_regs[offset >> 2] |= 2; |
1634 |
break;
|
1635 |
|
1636 |
case 0x4c: /* APLL_CTRL */ |
1637 |
diff = s->ulpd_pm_regs[offset >> 2] & value;
|
1638 |
s->ulpd_pm_regs[offset >> 2] = value & 0xf; |
1639 |
if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
1640 |
omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
1641 |
(value & (1 << 0)) ? "apll" : "dpll4")); |
1642 |
break;
|
1643 |
|
1644 |
default:
|
1645 |
OMAP_BAD_REG(addr); |
1646 |
} |
1647 |
} |
1648 |
|
1649 |
static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
|
1650 |
omap_badwidth_read16, |
1651 |
omap_ulpd_pm_read, |
1652 |
omap_badwidth_read16, |
1653 |
}; |
1654 |
|
1655 |
static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
|
1656 |
omap_badwidth_write16, |
1657 |
omap_ulpd_pm_write, |
1658 |
omap_badwidth_write16, |
1659 |
}; |
1660 |
|
1661 |
static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
1662 |
{ |
1663 |
mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
1664 |
mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
1665 |
mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
1666 |
mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
1667 |
mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
1668 |
mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
1669 |
mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
1670 |
mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
1671 |
mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
1672 |
mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
1673 |
mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
1674 |
omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
1675 |
mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
1676 |
omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
1677 |
mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
1678 |
mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
1679 |
mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
1680 |
mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
1681 |
mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
1682 |
mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
1683 |
mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
1684 |
omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
1685 |
omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
1686 |
} |
1687 |
|
1688 |
static void omap_ulpd_pm_init(target_phys_addr_t base, |
1689 |
struct omap_mpu_state_s *mpu)
|
1690 |
{ |
1691 |
int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
1692 |
omap_ulpd_pm_writefn, mpu); |
1693 |
|
1694 |
mpu->ulpd_pm_base = base; |
1695 |
cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
|
1696 |
omap_ulpd_pm_reset(mpu); |
1697 |
} |
1698 |
|
1699 |
/* OMAP Pin Configuration */
|
1700 |
static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
1701 |
{ |
1702 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1703 |
int offset = addr - s->pin_cfg_base;
|
1704 |
|
1705 |
switch (offset) {
|
1706 |
case 0x00: /* FUNC_MUX_CTRL_0 */ |
1707 |
case 0x04: /* FUNC_MUX_CTRL_1 */ |
1708 |
case 0x08: /* FUNC_MUX_CTRL_2 */ |
1709 |
return s->func_mux_ctrl[offset >> 2]; |
1710 |
|
1711 |
case 0x0c: /* COMP_MODE_CTRL_0 */ |
1712 |
return s->comp_mode_ctrl[0]; |
1713 |
|
1714 |
case 0x10: /* FUNC_MUX_CTRL_3 */ |
1715 |
case 0x14: /* FUNC_MUX_CTRL_4 */ |
1716 |
case 0x18: /* FUNC_MUX_CTRL_5 */ |
1717 |
case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1718 |
case 0x20: /* FUNC_MUX_CTRL_7 */ |
1719 |
case 0x24: /* FUNC_MUX_CTRL_8 */ |
1720 |
case 0x28: /* FUNC_MUX_CTRL_9 */ |
1721 |
case 0x2c: /* FUNC_MUX_CTRL_A */ |
1722 |
case 0x30: /* FUNC_MUX_CTRL_B */ |
1723 |
case 0x34: /* FUNC_MUX_CTRL_C */ |
1724 |
case 0x38: /* FUNC_MUX_CTRL_D */ |
1725 |
return s->func_mux_ctrl[(offset >> 2) - 1]; |
1726 |
|
1727 |
case 0x40: /* PULL_DWN_CTRL_0 */ |
1728 |
case 0x44: /* PULL_DWN_CTRL_1 */ |
1729 |
case 0x48: /* PULL_DWN_CTRL_2 */ |
1730 |
case 0x4c: /* PULL_DWN_CTRL_3 */ |
1731 |
return s->pull_dwn_ctrl[(offset & 0xf) >> 2]; |
1732 |
|
1733 |
case 0x50: /* GATE_INH_CTRL_0 */ |
1734 |
return s->gate_inh_ctrl[0]; |
1735 |
|
1736 |
case 0x60: /* VOLTAGE_CTRL_0 */ |
1737 |
return s->voltage_ctrl[0]; |
1738 |
|
1739 |
case 0x70: /* TEST_DBG_CTRL_0 */ |
1740 |
return s->test_dbg_ctrl[0]; |
1741 |
|
1742 |
case 0x80: /* MOD_CONF_CTRL_0 */ |
1743 |
return s->mod_conf_ctrl[0]; |
1744 |
} |
1745 |
|
1746 |
OMAP_BAD_REG(addr); |
1747 |
return 0; |
1748 |
} |
1749 |
|
1750 |
static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
1751 |
uint32_t diff, uint32_t value) |
1752 |
{ |
1753 |
if (s->compat1509) {
|
1754 |
if (diff & (1 << 9)) /* BLUETOOTH */ |
1755 |
omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
1756 |
(~value >> 9) & 1); |
1757 |
if (diff & (1 << 7)) /* USB.CLKO */ |
1758 |
omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
1759 |
(value >> 7) & 1); |
1760 |
} |
1761 |
} |
1762 |
|
1763 |
static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
1764 |
uint32_t diff, uint32_t value) |
1765 |
{ |
1766 |
if (s->compat1509) {
|
1767 |
if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
1768 |
omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
1769 |
(value >> 31) & 1); |
1770 |
if (diff & (1 << 1)) /* CLK32K */ |
1771 |
omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
1772 |
(~value >> 1) & 1); |
1773 |
} |
1774 |
} |
1775 |
|
1776 |
static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
1777 |
uint32_t diff, uint32_t value) |
1778 |
{ |
1779 |
if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
1780 |
omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
1781 |
omap_findclk(s, ((value >> 31) & 1) ? |
1782 |
"ck_48m" : "armper_ck")); |
1783 |
if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
1784 |
omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
1785 |
omap_findclk(s, ((value >> 30) & 1) ? |
1786 |
"ck_48m" : "armper_ck")); |
1787 |
if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
1788 |
omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
1789 |
omap_findclk(s, ((value >> 29) & 1) ? |
1790 |
"ck_48m" : "armper_ck")); |
1791 |
if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
1792 |
omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
1793 |
omap_findclk(s, ((value >> 23) & 1) ? |
1794 |
"ck_48m" : "armper_ck")); |
1795 |
if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
1796 |
omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
1797 |
omap_findclk(s, ((value >> 12) & 1) ? |
1798 |
"ck_48m" : "armper_ck")); |
1799 |
if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
1800 |
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
1801 |
} |
1802 |
|
1803 |
static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
1804 |
uint32_t value) |
1805 |
{ |
1806 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1807 |
int offset = addr - s->pin_cfg_base;
|
1808 |
uint32_t diff; |
1809 |
|
1810 |
switch (offset) {
|
1811 |
case 0x00: /* FUNC_MUX_CTRL_0 */ |
1812 |
diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1813 |
s->func_mux_ctrl[offset >> 2] = value;
|
1814 |
omap_pin_funcmux0_update(s, diff, value); |
1815 |
return;
|
1816 |
|
1817 |
case 0x04: /* FUNC_MUX_CTRL_1 */ |
1818 |
diff = s->func_mux_ctrl[offset >> 2] ^ value;
|
1819 |
s->func_mux_ctrl[offset >> 2] = value;
|
1820 |
omap_pin_funcmux1_update(s, diff, value); |
1821 |
return;
|
1822 |
|
1823 |
case 0x08: /* FUNC_MUX_CTRL_2 */ |
1824 |
s->func_mux_ctrl[offset >> 2] = value;
|
1825 |
return;
|
1826 |
|
1827 |
case 0x0c: /* COMP_MODE_CTRL_0 */ |
1828 |
s->comp_mode_ctrl[0] = value;
|
1829 |
s->compat1509 = (value != 0x0000eaef);
|
1830 |
omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
1831 |
omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
1832 |
return;
|
1833 |
|
1834 |
case 0x10: /* FUNC_MUX_CTRL_3 */ |
1835 |
case 0x14: /* FUNC_MUX_CTRL_4 */ |
1836 |
case 0x18: /* FUNC_MUX_CTRL_5 */ |
1837 |
case 0x1c: /* FUNC_MUX_CTRL_6 */ |
1838 |
case 0x20: /* FUNC_MUX_CTRL_7 */ |
1839 |
case 0x24: /* FUNC_MUX_CTRL_8 */ |
1840 |
case 0x28: /* FUNC_MUX_CTRL_9 */ |
1841 |
case 0x2c: /* FUNC_MUX_CTRL_A */ |
1842 |
case 0x30: /* FUNC_MUX_CTRL_B */ |
1843 |
case 0x34: /* FUNC_MUX_CTRL_C */ |
1844 |
case 0x38: /* FUNC_MUX_CTRL_D */ |
1845 |
s->func_mux_ctrl[(offset >> 2) - 1] = value; |
1846 |
return;
|
1847 |
|
1848 |
case 0x40: /* PULL_DWN_CTRL_0 */ |
1849 |
case 0x44: /* PULL_DWN_CTRL_1 */ |
1850 |
case 0x48: /* PULL_DWN_CTRL_2 */ |
1851 |
case 0x4c: /* PULL_DWN_CTRL_3 */ |
1852 |
s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value; |
1853 |
return;
|
1854 |
|
1855 |
case 0x50: /* GATE_INH_CTRL_0 */ |
1856 |
s->gate_inh_ctrl[0] = value;
|
1857 |
return;
|
1858 |
|
1859 |
case 0x60: /* VOLTAGE_CTRL_0 */ |
1860 |
s->voltage_ctrl[0] = value;
|
1861 |
return;
|
1862 |
|
1863 |
case 0x70: /* TEST_DBG_CTRL_0 */ |
1864 |
s->test_dbg_ctrl[0] = value;
|
1865 |
return;
|
1866 |
|
1867 |
case 0x80: /* MOD_CONF_CTRL_0 */ |
1868 |
diff = s->mod_conf_ctrl[0] ^ value;
|
1869 |
s->mod_conf_ctrl[0] = value;
|
1870 |
omap_pin_modconf1_update(s, diff, value); |
1871 |
return;
|
1872 |
|
1873 |
default:
|
1874 |
OMAP_BAD_REG(addr); |
1875 |
} |
1876 |
} |
1877 |
|
1878 |
static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
|
1879 |
omap_badwidth_read32, |
1880 |
omap_badwidth_read32, |
1881 |
omap_pin_cfg_read, |
1882 |
}; |
1883 |
|
1884 |
static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
|
1885 |
omap_badwidth_write32, |
1886 |
omap_badwidth_write32, |
1887 |
omap_pin_cfg_write, |
1888 |
}; |
1889 |
|
1890 |
static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
1891 |
{ |
1892 |
/* Start in Compatibility Mode. */
|
1893 |
mpu->compat1509 = 1;
|
1894 |
omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
1895 |
omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
1896 |
omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
1897 |
memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
1898 |
memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
1899 |
memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
1900 |
memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
1901 |
memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
1902 |
memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
1903 |
memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
1904 |
} |
1905 |
|
1906 |
static void omap_pin_cfg_init(target_phys_addr_t base, |
1907 |
struct omap_mpu_state_s *mpu)
|
1908 |
{ |
1909 |
int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
1910 |
omap_pin_cfg_writefn, mpu); |
1911 |
|
1912 |
mpu->pin_cfg_base = base; |
1913 |
cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
|
1914 |
omap_pin_cfg_reset(mpu); |
1915 |
} |
1916 |
|
1917 |
/* Device Identification, Die Identification */
|
1918 |
static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
1919 |
{ |
1920 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1921 |
|
1922 |
switch (addr) {
|
1923 |
case 0xfffe1800: /* DIE_ID_LSB */ |
1924 |
return 0xc9581f0e; |
1925 |
case 0xfffe1804: /* DIE_ID_MSB */ |
1926 |
return 0xa8858bfa; |
1927 |
|
1928 |
case 0xfffe2000: /* PRODUCT_ID_LSB */ |
1929 |
return 0x00aaaafc; |
1930 |
case 0xfffe2004: /* PRODUCT_ID_MSB */ |
1931 |
return 0xcafeb574; |
1932 |
|
1933 |
case 0xfffed400: /* JTAG_ID_LSB */ |
1934 |
switch (s->mpu_model) {
|
1935 |
case omap310:
|
1936 |
return 0x03310315; |
1937 |
case omap1510:
|
1938 |
return 0x03310115; |
1939 |
} |
1940 |
break;
|
1941 |
|
1942 |
case 0xfffed404: /* JTAG_ID_MSB */ |
1943 |
switch (s->mpu_model) {
|
1944 |
case omap310:
|
1945 |
return 0xfb57402f; |
1946 |
case omap1510:
|
1947 |
return 0xfb47002f; |
1948 |
} |
1949 |
break;
|
1950 |
} |
1951 |
|
1952 |
OMAP_BAD_REG(addr); |
1953 |
return 0; |
1954 |
} |
1955 |
|
1956 |
static void omap_id_write(void *opaque, target_phys_addr_t addr, |
1957 |
uint32_t value) |
1958 |
{ |
1959 |
OMAP_BAD_REG(addr); |
1960 |
} |
1961 |
|
1962 |
static CPUReadMemoryFunc *omap_id_readfn[] = {
|
1963 |
omap_badwidth_read32, |
1964 |
omap_badwidth_read32, |
1965 |
omap_id_read, |
1966 |
}; |
1967 |
|
1968 |
static CPUWriteMemoryFunc *omap_id_writefn[] = {
|
1969 |
omap_badwidth_write32, |
1970 |
omap_badwidth_write32, |
1971 |
omap_id_write, |
1972 |
}; |
1973 |
|
1974 |
static void omap_id_init(struct omap_mpu_state_s *mpu) |
1975 |
{ |
1976 |
int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
1977 |
omap_id_writefn, mpu); |
1978 |
cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype); |
1979 |
cpu_register_physical_memory(0xfffed400, 0x100, iomemtype); |
1980 |
if (!cpu_is_omap15xx(mpu))
|
1981 |
cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype); |
1982 |
} |
1983 |
|
1984 |
/* MPUI Control (Dummy) */
|
1985 |
static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
1986 |
{ |
1987 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1988 |
int offset = addr - s->mpui_base;
|
1989 |
|
1990 |
switch (offset) {
|
1991 |
case 0x00: /* CTRL */ |
1992 |
return s->mpui_ctrl;
|
1993 |
case 0x04: /* DEBUG_ADDR */ |
1994 |
return 0x01ffffff; |
1995 |
case 0x08: /* DEBUG_DATA */ |
1996 |
return 0xffffffff; |
1997 |
case 0x0c: /* DEBUG_FLAG */ |
1998 |
return 0x00000800; |
1999 |
case 0x10: /* STATUS */ |
2000 |
return 0x00000000; |
2001 |
|
2002 |
/* Not in OMAP310 */
|
2003 |
case 0x14: /* DSP_STATUS */ |
2004 |
case 0x18: /* DSP_BOOT_CONFIG */ |
2005 |
return 0x00000000; |
2006 |
case 0x1c: /* DSP_MPUI_CONFIG */ |
2007 |
return 0x0000ffff; |
2008 |
} |
2009 |
|
2010 |
OMAP_BAD_REG(addr); |
2011 |
return 0; |
2012 |
} |
2013 |
|
2014 |
static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
2015 |
uint32_t value) |
2016 |
{ |
2017 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2018 |
int offset = addr - s->mpui_base;
|
2019 |
|
2020 |
switch (offset) {
|
2021 |
case 0x00: /* CTRL */ |
2022 |
s->mpui_ctrl = value & 0x007fffff;
|
2023 |
break;
|
2024 |
|
2025 |
case 0x04: /* DEBUG_ADDR */ |
2026 |
case 0x08: /* DEBUG_DATA */ |
2027 |
case 0x0c: /* DEBUG_FLAG */ |
2028 |
case 0x10: /* STATUS */ |
2029 |
/* Not in OMAP310 */
|
2030 |
case 0x14: /* DSP_STATUS */ |
2031 |
OMAP_RO_REG(addr); |
2032 |
case 0x18: /* DSP_BOOT_CONFIG */ |
2033 |
case 0x1c: /* DSP_MPUI_CONFIG */ |
2034 |
break;
|
2035 |
|
2036 |
default:
|
2037 |
OMAP_BAD_REG(addr); |
2038 |
} |
2039 |
} |
2040 |
|
2041 |
static CPUReadMemoryFunc *omap_mpui_readfn[] = {
|
2042 |
omap_badwidth_read32, |
2043 |
omap_badwidth_read32, |
2044 |
omap_mpui_read, |
2045 |
}; |
2046 |
|
2047 |
static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
|
2048 |
omap_badwidth_write32, |
2049 |
omap_badwidth_write32, |
2050 |
omap_mpui_write, |
2051 |
}; |
2052 |
|
2053 |
static void omap_mpui_reset(struct omap_mpu_state_s *s) |
2054 |
{ |
2055 |
s->mpui_ctrl = 0x0003ff1b;
|
2056 |
} |
2057 |
|
2058 |
static void omap_mpui_init(target_phys_addr_t base, |
2059 |
struct omap_mpu_state_s *mpu)
|
2060 |
{ |
2061 |
int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
2062 |
omap_mpui_writefn, mpu); |
2063 |
|
2064 |
mpu->mpui_base = base; |
2065 |
cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
|
2066 |
|
2067 |
omap_mpui_reset(mpu); |
2068 |
} |
2069 |
|
2070 |
/* TIPB Bridges */
|
2071 |
struct omap_tipb_bridge_s {
|
2072 |
target_phys_addr_t base; |
2073 |
qemu_irq abort; |
2074 |
|
2075 |
int width_intr;
|
2076 |
uint16_t control; |
2077 |
uint16_t alloc; |
2078 |
uint16_t buffer; |
2079 |
uint16_t enh_control; |
2080 |
}; |
2081 |
|
2082 |
static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
2083 |
{ |
2084 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2085 |
int offset = addr - s->base;
|
2086 |
|
2087 |
switch (offset) {
|
2088 |
case 0x00: /* TIPB_CNTL */ |
2089 |
return s->control;
|
2090 |
case 0x04: /* TIPB_BUS_ALLOC */ |
2091 |
return s->alloc;
|
2092 |
case 0x08: /* MPU_TIPB_CNTL */ |
2093 |
return s->buffer;
|
2094 |
case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2095 |
return s->enh_control;
|
2096 |
case 0x10: /* ADDRESS_DBG */ |
2097 |
case 0x14: /* DATA_DEBUG_LOW */ |
2098 |
case 0x18: /* DATA_DEBUG_HIGH */ |
2099 |
return 0xffff; |
2100 |
case 0x1c: /* DEBUG_CNTR_SIG */ |
2101 |
return 0x00f8; |
2102 |
} |
2103 |
|
2104 |
OMAP_BAD_REG(addr); |
2105 |
return 0; |
2106 |
} |
2107 |
|
2108 |
static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
2109 |
uint32_t value) |
2110 |
{ |
2111 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
2112 |
int offset = addr - s->base;
|
2113 |
|
2114 |
switch (offset) {
|
2115 |
case 0x00: /* TIPB_CNTL */ |
2116 |
s->control = value & 0xffff;
|
2117 |
break;
|
2118 |
|
2119 |
case 0x04: /* TIPB_BUS_ALLOC */ |
2120 |
s->alloc = value & 0x003f;
|
2121 |
break;
|
2122 |
|
2123 |
case 0x08: /* MPU_TIPB_CNTL */ |
2124 |
s->buffer = value & 0x0003;
|
2125 |
break;
|
2126 |
|
2127 |
case 0x0c: /* ENHANCED_TIPB_CNTL */ |
2128 |
s->width_intr = !(value & 2);
|
2129 |
s->enh_control = value & 0x000f;
|
2130 |
break;
|
2131 |
|
2132 |
case 0x10: /* ADDRESS_DBG */ |
2133 |
case 0x14: /* DATA_DEBUG_LOW */ |
2134 |
case 0x18: /* DATA_DEBUG_HIGH */ |
2135 |
case 0x1c: /* DEBUG_CNTR_SIG */ |
2136 |
OMAP_RO_REG(addr); |
2137 |
break;
|
2138 |
|
2139 |
default:
|
2140 |
OMAP_BAD_REG(addr); |
2141 |
} |
2142 |
} |
2143 |
|
2144 |
static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
|
2145 |
omap_badwidth_read16, |
2146 |
omap_tipb_bridge_read, |
2147 |
omap_tipb_bridge_read, |
2148 |
}; |
2149 |
|
2150 |
static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
|
2151 |
omap_badwidth_write16, |
2152 |
omap_tipb_bridge_write, |
2153 |
omap_tipb_bridge_write, |
2154 |
}; |
2155 |
|
2156 |
static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
2157 |
{ |
2158 |
s->control = 0xffff;
|
2159 |
s->alloc = 0x0009;
|
2160 |
s->buffer = 0x0000;
|
2161 |
s->enh_control = 0x000f;
|
2162 |
} |
2163 |
|
2164 |
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
2165 |
qemu_irq abort_irq, omap_clk clk) |
2166 |
{ |
2167 |
int iomemtype;
|
2168 |
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
2169 |
qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
2170 |
|
2171 |
s->abort = abort_irq; |
2172 |
s->base = base; |
2173 |
omap_tipb_bridge_reset(s); |
2174 |
|
2175 |
iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
|
2176 |
omap_tipb_bridge_writefn, s); |
2177 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2178 |
|
2179 |
return s;
|
2180 |
} |
2181 |
|
2182 |
/* Dummy Traffic Controller's Memory Interface */
|
2183 |
static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
2184 |
{ |
2185 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2186 |
int offset = addr - s->tcmi_base;
|
2187 |
uint32_t ret; |
2188 |
|
2189 |
switch (offset) {
|
2190 |
case 0xfffecc00: /* IMIF_PRIO */ |
2191 |
case 0xfffecc04: /* EMIFS_PRIO */ |
2192 |
case 0xfffecc08: /* EMIFF_PRIO */ |
2193 |
case 0xfffecc0c: /* EMIFS_CONFIG */ |
2194 |
case 0xfffecc10: /* EMIFS_CS0_CONFIG */ |
2195 |
case 0xfffecc14: /* EMIFS_CS1_CONFIG */ |
2196 |
case 0xfffecc18: /* EMIFS_CS2_CONFIG */ |
2197 |
case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ |
2198 |
case 0xfffecc24: /* EMIFF_MRS */ |
2199 |
case 0xfffecc28: /* TIMEOUT1 */ |
2200 |
case 0xfffecc2c: /* TIMEOUT2 */ |
2201 |
case 0xfffecc30: /* TIMEOUT3 */ |
2202 |
case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2203 |
case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ |
2204 |
return s->tcmi_regs[offset >> 2]; |
2205 |
|
2206 |
case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ |
2207 |
ret = s->tcmi_regs[offset >> 2];
|
2208 |
s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
2209 |
/* XXX: We can try using the VGA_DIRTY flag for this */
|
2210 |
return ret;
|
2211 |
} |
2212 |
|
2213 |
OMAP_BAD_REG(addr); |
2214 |
return 0; |
2215 |
} |
2216 |
|
2217 |
static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
2218 |
uint32_t value) |
2219 |
{ |
2220 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2221 |
int offset = addr - s->tcmi_base;
|
2222 |
|
2223 |
switch (offset) {
|
2224 |
case 0xfffecc00: /* IMIF_PRIO */ |
2225 |
case 0xfffecc04: /* EMIFS_PRIO */ |
2226 |
case 0xfffecc08: /* EMIFF_PRIO */ |
2227 |
case 0xfffecc10: /* EMIFS_CS0_CONFIG */ |
2228 |
case 0xfffecc14: /* EMIFS_CS1_CONFIG */ |
2229 |
case 0xfffecc18: /* EMIFS_CS2_CONFIG */ |
2230 |
case 0xfffecc1c: /* EMIFS_CS3_CONFIG */ |
2231 |
case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */ |
2232 |
case 0xfffecc24: /* EMIFF_MRS */ |
2233 |
case 0xfffecc28: /* TIMEOUT1 */ |
2234 |
case 0xfffecc2c: /* TIMEOUT2 */ |
2235 |
case 0xfffecc30: /* TIMEOUT3 */ |
2236 |
case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */ |
2237 |
case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */ |
2238 |
s->tcmi_regs[offset >> 2] = value;
|
2239 |
break;
|
2240 |
case 0xfffecc0c: /* EMIFS_CONFIG */ |
2241 |
s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4); |
2242 |
break;
|
2243 |
|
2244 |
default:
|
2245 |
OMAP_BAD_REG(addr); |
2246 |
} |
2247 |
} |
2248 |
|
2249 |
static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
|
2250 |
omap_badwidth_read32, |
2251 |
omap_badwidth_read32, |
2252 |
omap_tcmi_read, |
2253 |
}; |
2254 |
|
2255 |
static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
|
2256 |
omap_badwidth_write32, |
2257 |
omap_badwidth_write32, |
2258 |
omap_tcmi_write, |
2259 |
}; |
2260 |
|
2261 |
static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
2262 |
{ |
2263 |
mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
2264 |
mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
2265 |
mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
2266 |
mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
2267 |
mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
2268 |
mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
2269 |
mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
2270 |
mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
2271 |
mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
2272 |
mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
2273 |
mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
2274 |
mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
2275 |
mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
2276 |
mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
2277 |
mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
2278 |
} |
2279 |
|
2280 |
static void omap_tcmi_init(target_phys_addr_t base, |
2281 |
struct omap_mpu_state_s *mpu)
|
2282 |
{ |
2283 |
int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
2284 |
omap_tcmi_writefn, mpu); |
2285 |
|
2286 |
mpu->tcmi_base = base; |
2287 |
cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
|
2288 |
omap_tcmi_reset(mpu); |
2289 |
} |
2290 |
|
2291 |
/* Digital phase-locked loops control */
|
2292 |
static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
2293 |
{ |
2294 |
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2295 |
int offset = addr - s->base;
|
2296 |
|
2297 |
if (offset == 0x00) /* CTL_REG */ |
2298 |
return s->mode;
|
2299 |
|
2300 |
OMAP_BAD_REG(addr); |
2301 |
return 0; |
2302 |
} |
2303 |
|
2304 |
static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
2305 |
uint32_t value) |
2306 |
{ |
2307 |
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
2308 |
uint16_t diff; |
2309 |
int offset = addr - s->base;
|
2310 |
static const int bypass_div[4] = { 1, 2, 4, 4 }; |
2311 |
int div, mult;
|
2312 |
|
2313 |
if (offset == 0x00) { /* CTL_REG */ |
2314 |
/* See omap_ulpd_pm_write() too */
|
2315 |
diff = s->mode & value; |
2316 |
s->mode = value & 0x2fff;
|
2317 |
if (diff & (0x3ff << 2)) { |
2318 |
if (value & (1 << 4)) { /* PLL_ENABLE */ |
2319 |
div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
2320 |
mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
2321 |
} else {
|
2322 |
div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
2323 |
mult = 1;
|
2324 |
} |
2325 |
omap_clk_setrate(s->dpll, div, mult); |
2326 |
} |
2327 |
|
2328 |
/* Enter the desired mode. */
|
2329 |
s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
2330 |
|
2331 |
/* Act as if the lock is restored. */
|
2332 |
s->mode |= 2;
|
2333 |
} else {
|
2334 |
OMAP_BAD_REG(addr); |
2335 |
} |
2336 |
} |
2337 |
|
2338 |
static CPUReadMemoryFunc *omap_dpll_readfn[] = {
|
2339 |
omap_badwidth_read16, |
2340 |
omap_dpll_read, |
2341 |
omap_badwidth_read16, |
2342 |
}; |
2343 |
|
2344 |
static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
|
2345 |
omap_badwidth_write16, |
2346 |
omap_dpll_write, |
2347 |
omap_badwidth_write16, |
2348 |
}; |
2349 |
|
2350 |
static void omap_dpll_reset(struct dpll_ctl_s *s) |
2351 |
{ |
2352 |
s->mode = 0x2002;
|
2353 |
omap_clk_setrate(s->dpll, 1, 1); |
2354 |
} |
2355 |
|
2356 |
static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
2357 |
omap_clk clk) |
2358 |
{ |
2359 |
int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
2360 |
omap_dpll_writefn, s); |
2361 |
|
2362 |
s->base = base; |
2363 |
s->dpll = clk; |
2364 |
omap_dpll_reset(s); |
2365 |
|
2366 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
2367 |
} |
2368 |
|
2369 |
/* UARTs */
|
2370 |
struct omap_uart_s {
|
2371 |
SerialState *serial; /* TODO */
|
2372 |
}; |
2373 |
|
2374 |
static void omap_uart_reset(struct omap_uart_s *s) |
2375 |
{ |
2376 |
} |
2377 |
|
2378 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
2379 |
qemu_irq irq, omap_clk clk, CharDriverState *chr) |
2380 |
{ |
2381 |
struct omap_uart_s *s = (struct omap_uart_s *) |
2382 |
qemu_mallocz(sizeof(struct omap_uart_s)); |
2383 |
if (chr)
|
2384 |
s->serial = serial_mm_init(base, 2, irq, chr, 1); |
2385 |
return s;
|
2386 |
} |
2387 |
|
2388 |
/* MPU Clock/Reset/Power Mode Control */
|
2389 |
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
2390 |
{ |
2391 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2392 |
int offset = addr - s->clkm.mpu_base;
|
2393 |
|
2394 |
switch (offset) {
|
2395 |
case 0x00: /* ARM_CKCTL */ |
2396 |
return s->clkm.arm_ckctl;
|
2397 |
|
2398 |
case 0x04: /* ARM_IDLECT1 */ |
2399 |
return s->clkm.arm_idlect1;
|
2400 |
|
2401 |
case 0x08: /* ARM_IDLECT2 */ |
2402 |
return s->clkm.arm_idlect2;
|
2403 |
|
2404 |
case 0x0c: /* ARM_EWUPCT */ |
2405 |
return s->clkm.arm_ewupct;
|
2406 |
|
2407 |
case 0x10: /* ARM_RSTCT1 */ |
2408 |
return s->clkm.arm_rstct1;
|
2409 |
|
2410 |
case 0x14: /* ARM_RSTCT2 */ |
2411 |
return s->clkm.arm_rstct2;
|
2412 |
|
2413 |
case 0x18: /* ARM_SYSST */ |
2414 |
return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start; |
2415 |
|
2416 |
case 0x1c: /* ARM_CKOUT1 */ |
2417 |
return s->clkm.arm_ckout1;
|
2418 |
|
2419 |
case 0x20: /* ARM_CKOUT2 */ |
2420 |
break;
|
2421 |
} |
2422 |
|
2423 |
OMAP_BAD_REG(addr); |
2424 |
return 0; |
2425 |
} |
2426 |
|
2427 |
static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
2428 |
uint16_t diff, uint16_t value) |
2429 |
{ |
2430 |
omap_clk clk; |
2431 |
|
2432 |
if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
2433 |
if (value & (1 << 14)) |
2434 |
/* Reserved */;
|
2435 |
else {
|
2436 |
clk = omap_findclk(s, "arminth_ck");
|
2437 |
omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2438 |
} |
2439 |
} |
2440 |
if (diff & (1 << 12)) { /* ARM_TIMXO */ |
2441 |
clk = omap_findclk(s, "armtim_ck");
|
2442 |
if (value & (1 << 12)) |
2443 |
omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
2444 |
else
|
2445 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2446 |
} |
2447 |
/* XXX: en_dspck */
|
2448 |
if (diff & (3 << 10)) { /* DSPMMUDIV */ |
2449 |
clk = omap_findclk(s, "dspmmu_ck");
|
2450 |
omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
2451 |
} |
2452 |
if (diff & (3 << 8)) { /* TCDIV */ |
2453 |
clk = omap_findclk(s, "tc_ck");
|
2454 |
omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
2455 |
} |
2456 |
if (diff & (3 << 6)) { /* DSPDIV */ |
2457 |
clk = omap_findclk(s, "dsp_ck");
|
2458 |
omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
2459 |
} |
2460 |
if (diff & (3 << 4)) { /* ARMDIV */ |
2461 |
clk = omap_findclk(s, "arm_ck");
|
2462 |
omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
2463 |
} |
2464 |
if (diff & (3 << 2)) { /* LCDDIV */ |
2465 |
clk = omap_findclk(s, "lcd_ck");
|
2466 |
omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
2467 |
} |
2468 |
if (diff & (3 << 0)) { /* PERDIV */ |
2469 |
clk = omap_findclk(s, "armper_ck");
|
2470 |
omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
2471 |
} |
2472 |
} |
2473 |
|
2474 |
static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
2475 |
uint16_t diff, uint16_t value) |
2476 |
{ |
2477 |
omap_clk clk; |
2478 |
|
2479 |
if (value & (1 << 11)) /* SETARM_IDLE */ |
2480 |
cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
2481 |
if (!(value & (1 << 10))) /* WKUP_MODE */ |
2482 |
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
2483 |
|
2484 |
#define SET_CANIDLE(clock, bit) \
|
2485 |
if (diff & (1 << bit)) { \ |
2486 |
clk = omap_findclk(s, clock); \ |
2487 |
omap_clk_canidle(clk, (value >> bit) & 1); \
|
2488 |
} |
2489 |
SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
2490 |
SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
2491 |
SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
2492 |
SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
2493 |
SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
2494 |
SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
2495 |
SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
2496 |
SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
2497 |
SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
2498 |
SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
2499 |
SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
2500 |
SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
2501 |
SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
2502 |
SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
2503 |
} |
2504 |
|
2505 |
static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
2506 |
uint16_t diff, uint16_t value) |
2507 |
{ |
2508 |
omap_clk clk; |
2509 |
|
2510 |
#define SET_ONOFF(clock, bit) \
|
2511 |
if (diff & (1 << bit)) { \ |
2512 |
clk = omap_findclk(s, clock); \ |
2513 |
omap_clk_onoff(clk, (value >> bit) & 1); \
|
2514 |
} |
2515 |
SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
2516 |
SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
2517 |
SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
2518 |
SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
2519 |
SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
2520 |
SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
2521 |
SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
2522 |
SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
2523 |
SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
2524 |
SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
2525 |
SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
2526 |
} |
2527 |
|
2528 |
static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
2529 |
uint16_t diff, uint16_t value) |
2530 |
{ |
2531 |
omap_clk clk; |
2532 |
|
2533 |
if (diff & (3 << 4)) { /* TCLKOUT */ |
2534 |
clk = omap_findclk(s, "tclk_out");
|
2535 |
switch ((value >> 4) & 3) { |
2536 |
case 1: |
2537 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
2538 |
omap_clk_onoff(clk, 1);
|
2539 |
break;
|
2540 |
case 2: |
2541 |
omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
2542 |
omap_clk_onoff(clk, 1);
|
2543 |
break;
|
2544 |
default:
|
2545 |
omap_clk_onoff(clk, 0);
|
2546 |
} |
2547 |
} |
2548 |
if (diff & (3 << 2)) { /* DCLKOUT */ |
2549 |
clk = omap_findclk(s, "dclk_out");
|
2550 |
switch ((value >> 2) & 3) { |
2551 |
case 0: |
2552 |
omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
2553 |
break;
|
2554 |
case 1: |
2555 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
2556 |
break;
|
2557 |
case 2: |
2558 |
omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
2559 |
break;
|
2560 |
case 3: |
2561 |
omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2562 |
break;
|
2563 |
} |
2564 |
} |
2565 |
if (diff & (3 << 0)) { /* ACLKOUT */ |
2566 |
clk = omap_findclk(s, "aclk_out");
|
2567 |
switch ((value >> 0) & 3) { |
2568 |
case 1: |
2569 |
omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
2570 |
omap_clk_onoff(clk, 1);
|
2571 |
break;
|
2572 |
case 2: |
2573 |
omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
2574 |
omap_clk_onoff(clk, 1);
|
2575 |
break;
|
2576 |
case 3: |
2577 |
omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
2578 |
omap_clk_onoff(clk, 1);
|
2579 |
break;
|
2580 |
default:
|
2581 |
omap_clk_onoff(clk, 0);
|
2582 |
} |
2583 |
} |
2584 |
} |
2585 |
|
2586 |
static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
2587 |
uint32_t value) |
2588 |
{ |
2589 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2590 |
int offset = addr - s->clkm.mpu_base;
|
2591 |
uint16_t diff; |
2592 |
omap_clk clk; |
2593 |
static const char *clkschemename[8] = { |
2594 |
"fully synchronous", "fully asynchronous", "synchronous scalable", |
2595 |
"mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
2596 |
}; |
2597 |
|
2598 |
switch (offset) {
|
2599 |
case 0x00: /* ARM_CKCTL */ |
2600 |
diff = s->clkm.arm_ckctl ^ value; |
2601 |
s->clkm.arm_ckctl = value & 0x7fff;
|
2602 |
omap_clkm_ckctl_update(s, diff, value); |
2603 |
return;
|
2604 |
|
2605 |
case 0x04: /* ARM_IDLECT1 */ |
2606 |
diff = s->clkm.arm_idlect1 ^ value; |
2607 |
s->clkm.arm_idlect1 = value & 0x0fff;
|
2608 |
omap_clkm_idlect1_update(s, diff, value); |
2609 |
return;
|
2610 |
|
2611 |
case 0x08: /* ARM_IDLECT2 */ |
2612 |
diff = s->clkm.arm_idlect2 ^ value; |
2613 |
s->clkm.arm_idlect2 = value & 0x07ff;
|
2614 |
omap_clkm_idlect2_update(s, diff, value); |
2615 |
return;
|
2616 |
|
2617 |
case 0x0c: /* ARM_EWUPCT */ |
2618 |
diff = s->clkm.arm_ewupct ^ value; |
2619 |
s->clkm.arm_ewupct = value & 0x003f;
|
2620 |
return;
|
2621 |
|
2622 |
case 0x10: /* ARM_RSTCT1 */ |
2623 |
diff = s->clkm.arm_rstct1 ^ value; |
2624 |
s->clkm.arm_rstct1 = value & 0x0007;
|
2625 |
if (value & 9) { |
2626 |
qemu_system_reset_request(); |
2627 |
s->clkm.cold_start = 0xa;
|
2628 |
} |
2629 |
if (diff & ~value & 4) { /* DSP_RST */ |
2630 |
omap_mpui_reset(s); |
2631 |
omap_tipb_bridge_reset(s->private_tipb); |
2632 |
omap_tipb_bridge_reset(s->public_tipb); |
2633 |
} |
2634 |
if (diff & 2) { /* DSP_EN */ |
2635 |
clk = omap_findclk(s, "dsp_ck");
|
2636 |
omap_clk_canidle(clk, (~value >> 1) & 1); |
2637 |
} |
2638 |
return;
|
2639 |
|
2640 |
case 0x14: /* ARM_RSTCT2 */ |
2641 |
s->clkm.arm_rstct2 = value & 0x0001;
|
2642 |
return;
|
2643 |
|
2644 |
case 0x18: /* ARM_SYSST */ |
2645 |
if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
2646 |
s->clkm.clocking_scheme = (value >> 11) & 7; |
2647 |
printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
2648 |
clkschemename[s->clkm.clocking_scheme]); |
2649 |
} |
2650 |
s->clkm.cold_start &= value & 0x3f;
|
2651 |
return;
|
2652 |
|
2653 |
case 0x1c: /* ARM_CKOUT1 */ |
2654 |
diff = s->clkm.arm_ckout1 ^ value; |
2655 |
s->clkm.arm_ckout1 = value & 0x003f;
|
2656 |
omap_clkm_ckout1_update(s, diff, value); |
2657 |
return;
|
2658 |
|
2659 |
case 0x20: /* ARM_CKOUT2 */ |
2660 |
default:
|
2661 |
OMAP_BAD_REG(addr); |
2662 |
} |
2663 |
} |
2664 |
|
2665 |
static CPUReadMemoryFunc *omap_clkm_readfn[] = {
|
2666 |
omap_badwidth_read16, |
2667 |
omap_clkm_read, |
2668 |
omap_badwidth_read16, |
2669 |
}; |
2670 |
|
2671 |
static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
|
2672 |
omap_badwidth_write16, |
2673 |
omap_clkm_write, |
2674 |
omap_badwidth_write16, |
2675 |
}; |
2676 |
|
2677 |
static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
2678 |
{ |
2679 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2680 |
int offset = addr - s->clkm.dsp_base;
|
2681 |
|
2682 |
switch (offset) {
|
2683 |
case 0x04: /* DSP_IDLECT1 */ |
2684 |
return s->clkm.dsp_idlect1;
|
2685 |
|
2686 |
case 0x08: /* DSP_IDLECT2 */ |
2687 |
return s->clkm.dsp_idlect2;
|
2688 |
|
2689 |
case 0x14: /* DSP_RSTCT2 */ |
2690 |
return s->clkm.dsp_rstct2;
|
2691 |
|
2692 |
case 0x18: /* DSP_SYSST */ |
2693 |
return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start | |
2694 |
(s->env->halted << 6); /* Quite useless... */ |
2695 |
} |
2696 |
|
2697 |
OMAP_BAD_REG(addr); |
2698 |
return 0; |
2699 |
} |
2700 |
|
2701 |
static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
2702 |
uint16_t diff, uint16_t value) |
2703 |
{ |
2704 |
omap_clk clk; |
2705 |
|
2706 |
SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
2707 |
} |
2708 |
|
2709 |
static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
2710 |
uint16_t diff, uint16_t value) |
2711 |
{ |
2712 |
omap_clk clk; |
2713 |
|
2714 |
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
2715 |
} |
2716 |
|
2717 |
static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
2718 |
uint32_t value) |
2719 |
{ |
2720 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2721 |
int offset = addr - s->clkm.dsp_base;
|
2722 |
uint16_t diff; |
2723 |
|
2724 |
switch (offset) {
|
2725 |
case 0x04: /* DSP_IDLECT1 */ |
2726 |
diff = s->clkm.dsp_idlect1 ^ value; |
2727 |
s->clkm.dsp_idlect1 = value & 0x01f7;
|
2728 |
omap_clkdsp_idlect1_update(s, diff, value); |
2729 |
break;
|
2730 |
|
2731 |
case 0x08: /* DSP_IDLECT2 */ |
2732 |
s->clkm.dsp_idlect2 = value & 0x0037;
|
2733 |
diff = s->clkm.dsp_idlect1 ^ value; |
2734 |
omap_clkdsp_idlect2_update(s, diff, value); |
2735 |
break;
|
2736 |
|
2737 |
case 0x14: /* DSP_RSTCT2 */ |
2738 |
s->clkm.dsp_rstct2 = value & 0x0001;
|
2739 |
break;
|
2740 |
|
2741 |
case 0x18: /* DSP_SYSST */ |
2742 |
s->clkm.cold_start &= value & 0x3f;
|
2743 |
break;
|
2744 |
|
2745 |
default:
|
2746 |
OMAP_BAD_REG(addr); |
2747 |
} |
2748 |
} |
2749 |
|
2750 |
static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
|
2751 |
omap_badwidth_read16, |
2752 |
omap_clkdsp_read, |
2753 |
omap_badwidth_read16, |
2754 |
}; |
2755 |
|
2756 |
static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
|
2757 |
omap_badwidth_write16, |
2758 |
omap_clkdsp_write, |
2759 |
omap_badwidth_write16, |
2760 |
}; |
2761 |
|
2762 |
static void omap_clkm_reset(struct omap_mpu_state_s *s) |
2763 |
{ |
2764 |
if (s->wdt && s->wdt->reset)
|
2765 |
s->clkm.cold_start = 0x6;
|
2766 |
s->clkm.clocking_scheme = 0;
|
2767 |
omap_clkm_ckctl_update(s, ~0, 0x3000); |
2768 |
s->clkm.arm_ckctl = 0x3000;
|
2769 |
omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 & 0x0400, 0x0400); |
2770 |
s->clkm.arm_idlect1 = 0x0400;
|
2771 |
omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 & 0x0100, 0x0100); |
2772 |
s->clkm.arm_idlect2 = 0x0100;
|
2773 |
s->clkm.arm_ewupct = 0x003f;
|
2774 |
s->clkm.arm_rstct1 = 0x0000;
|
2775 |
s->clkm.arm_rstct2 = 0x0000;
|
2776 |
s->clkm.arm_ckout1 = 0x0015;
|
2777 |
s->clkm.dpll1_mode = 0x2002;
|
2778 |
omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
2779 |
s->clkm.dsp_idlect1 = 0x0040;
|
2780 |
omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
2781 |
s->clkm.dsp_idlect2 = 0x0000;
|
2782 |
s->clkm.dsp_rstct2 = 0x0000;
|
2783 |
} |
2784 |
|
2785 |
static void omap_clkm_init(target_phys_addr_t mpu_base, |
2786 |
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
2787 |
{ |
2788 |
int iomemtype[2] = { |
2789 |
cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
|
2790 |
cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
|
2791 |
}; |
2792 |
|
2793 |
s->clkm.mpu_base = mpu_base; |
2794 |
s->clkm.dsp_base = dsp_base; |
2795 |
s->clkm.cold_start = 0x3a;
|
2796 |
omap_clkm_reset(s); |
2797 |
|
2798 |
cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]); |
2799 |
cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]); |
2800 |
} |
2801 |
|
2802 |
/* MPU I/O */
|
2803 |
struct omap_mpuio_s {
|
2804 |
target_phys_addr_t base; |
2805 |
qemu_irq irq; |
2806 |
qemu_irq kbd_irq; |
2807 |
qemu_irq *in; |
2808 |
qemu_irq handler[16];
|
2809 |
qemu_irq wakeup; |
2810 |
|
2811 |
uint16_t inputs; |
2812 |
uint16_t outputs; |
2813 |
uint16_t dir; |
2814 |
uint16_t edge; |
2815 |
uint16_t mask; |
2816 |
uint16_t ints; |
2817 |
|
2818 |
uint16_t debounce; |
2819 |
uint16_t latch; |
2820 |
uint8_t event; |
2821 |
|
2822 |
uint8_t buttons[5];
|
2823 |
uint8_t row_latch; |
2824 |
uint8_t cols; |
2825 |
int kbd_mask;
|
2826 |
int clk;
|
2827 |
}; |
2828 |
|
2829 |
static void omap_mpuio_set(void *opaque, int line, int level) |
2830 |
{ |
2831 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2832 |
uint16_t prev = s->inputs; |
2833 |
|
2834 |
if (level)
|
2835 |
s->inputs |= 1 << line;
|
2836 |
else
|
2837 |
s->inputs &= ~(1 << line);
|
2838 |
|
2839 |
if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
2840 |
if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
2841 |
s->ints |= 1 << line;
|
2842 |
qemu_irq_raise(s->irq); |
2843 |
/* TODO: wakeup */
|
2844 |
} |
2845 |
if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
2846 |
(s->event >> 1) == line) /* PIN_SELECT */ |
2847 |
s->latch = s->inputs; |
2848 |
} |
2849 |
} |
2850 |
|
2851 |
static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
2852 |
{ |
2853 |
int i;
|
2854 |
uint8_t *row, rows = 0, cols = ~s->cols;
|
2855 |
|
2856 |
for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
2857 |
if (*row & cols)
|
2858 |
rows |= i; |
2859 |
|
2860 |
qemu_set_irq(s->kbd_irq, rows && ~s->kbd_mask && s->clk); |
2861 |
s->row_latch = rows ^ 0x1f;
|
2862 |
} |
2863 |
|
2864 |
static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
2865 |
{ |
2866 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2867 |
int offset = addr - s->base;
|
2868 |
uint16_t ret; |
2869 |
|
2870 |
switch (offset) {
|
2871 |
case 0x00: /* INPUT_LATCH */ |
2872 |
return s->inputs;
|
2873 |
|
2874 |
case 0x04: /* OUTPUT_REG */ |
2875 |
return s->outputs;
|
2876 |
|
2877 |
case 0x08: /* IO_CNTL */ |
2878 |
return s->dir;
|
2879 |
|
2880 |
case 0x10: /* KBR_LATCH */ |
2881 |
return s->row_latch;
|
2882 |
|
2883 |
case 0x14: /* KBC_REG */ |
2884 |
return s->cols;
|
2885 |
|
2886 |
case 0x18: /* GPIO_EVENT_MODE_REG */ |
2887 |
return s->event;
|
2888 |
|
2889 |
case 0x1c: /* GPIO_INT_EDGE_REG */ |
2890 |
return s->edge;
|
2891 |
|
2892 |
case 0x20: /* KBD_INT */ |
2893 |
return (s->row_latch != 0x1f) && !s->kbd_mask; |
2894 |
|
2895 |
case 0x24: /* GPIO_INT */ |
2896 |
ret = s->ints; |
2897 |
s->ints &= s->mask; |
2898 |
if (ret)
|
2899 |
qemu_irq_lower(s->irq); |
2900 |
return ret;
|
2901 |
|
2902 |
case 0x28: /* KBD_MASKIT */ |
2903 |
return s->kbd_mask;
|
2904 |
|
2905 |
case 0x2c: /* GPIO_MASKIT */ |
2906 |
return s->mask;
|
2907 |
|
2908 |
case 0x30: /* GPIO_DEBOUNCING_REG */ |
2909 |
return s->debounce;
|
2910 |
|
2911 |
case 0x34: /* GPIO_LATCH_REG */ |
2912 |
return s->latch;
|
2913 |
} |
2914 |
|
2915 |
OMAP_BAD_REG(addr); |
2916 |
return 0; |
2917 |
} |
2918 |
|
2919 |
static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
2920 |
uint32_t value) |
2921 |
{ |
2922 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2923 |
int offset = addr - s->base;
|
2924 |
uint16_t diff; |
2925 |
int ln;
|
2926 |
|
2927 |
switch (offset) {
|
2928 |
case 0x04: /* OUTPUT_REG */ |
2929 |
diff = s->outputs ^ (value & ~s->dir); |
2930 |
s->outputs = value; |
2931 |
value &= ~s->dir; |
2932 |
while ((ln = ffs(diff))) {
|
2933 |
ln --; |
2934 |
if (s->handler[ln])
|
2935 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2936 |
diff &= ~(1 << ln);
|
2937 |
} |
2938 |
break;
|
2939 |
|
2940 |
case 0x08: /* IO_CNTL */ |
2941 |
diff = s->outputs & (s->dir ^ value); |
2942 |
s->dir = value; |
2943 |
|
2944 |
value = s->outputs & ~s->dir; |
2945 |
while ((ln = ffs(diff))) {
|
2946 |
ln --; |
2947 |
if (s->handler[ln])
|
2948 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
2949 |
diff &= ~(1 << ln);
|
2950 |
} |
2951 |
break;
|
2952 |
|
2953 |
case 0x14: /* KBC_REG */ |
2954 |
s->cols = value; |
2955 |
omap_mpuio_kbd_update(s); |
2956 |
break;
|
2957 |
|
2958 |
case 0x18: /* GPIO_EVENT_MODE_REG */ |
2959 |
s->event = value & 0x1f;
|
2960 |
break;
|
2961 |
|
2962 |
case 0x1c: /* GPIO_INT_EDGE_REG */ |
2963 |
s->edge = value; |
2964 |
break;
|
2965 |
|
2966 |
case 0x28: /* KBD_MASKIT */ |
2967 |
s->kbd_mask = value & 1;
|
2968 |
omap_mpuio_kbd_update(s); |
2969 |
break;
|
2970 |
|
2971 |
case 0x2c: /* GPIO_MASKIT */ |
2972 |
s->mask = value; |
2973 |
break;
|
2974 |
|
2975 |
case 0x30: /* GPIO_DEBOUNCING_REG */ |
2976 |
s->debounce = value & 0x1ff;
|
2977 |
break;
|
2978 |
|
2979 |
case 0x00: /* INPUT_LATCH */ |
2980 |
case 0x10: /* KBR_LATCH */ |
2981 |
case 0x20: /* KBD_INT */ |
2982 |
case 0x24: /* GPIO_INT */ |
2983 |
case 0x34: /* GPIO_LATCH_REG */ |
2984 |
OMAP_RO_REG(addr); |
2985 |
return;
|
2986 |
|
2987 |
default:
|
2988 |
OMAP_BAD_REG(addr); |
2989 |
return;
|
2990 |
} |
2991 |
} |
2992 |
|
2993 |
static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
|
2994 |
omap_badwidth_read16, |
2995 |
omap_mpuio_read, |
2996 |
omap_badwidth_read16, |
2997 |
}; |
2998 |
|
2999 |
static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
|
3000 |
omap_badwidth_write16, |
3001 |
omap_mpuio_write, |
3002 |
omap_badwidth_write16, |
3003 |
}; |
3004 |
|
3005 |
void omap_mpuio_reset(struct omap_mpuio_s *s) |
3006 |
{ |
3007 |
s->inputs = 0;
|
3008 |
s->outputs = 0;
|
3009 |
s->dir = ~0;
|
3010 |
s->event = 0;
|
3011 |
s->edge = 0;
|
3012 |
s->kbd_mask = 0;
|
3013 |
s->mask = 0;
|
3014 |
s->debounce = 0;
|
3015 |
s->latch = 0;
|
3016 |
s->ints = 0;
|
3017 |
s->row_latch = 0x1f;
|
3018 |
s->clk = 1;
|
3019 |
} |
3020 |
|
3021 |
static void omap_mpuio_onoff(void *opaque, int line, int on) |
3022 |
{ |
3023 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
3024 |
|
3025 |
s->clk = on; |
3026 |
if (on)
|
3027 |
omap_mpuio_kbd_update(s); |
3028 |
} |
3029 |
|
3030 |
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
3031 |
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
3032 |
omap_clk clk) |
3033 |
{ |
3034 |
int iomemtype;
|
3035 |
struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
3036 |
qemu_mallocz(sizeof(struct omap_mpuio_s)); |
3037 |
|
3038 |
s->base = base; |
3039 |
s->irq = gpio_int; |
3040 |
s->kbd_irq = kbd_int; |
3041 |
s->wakeup = wakeup; |
3042 |
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
3043 |
omap_mpuio_reset(s); |
3044 |
|
3045 |
iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
|
3046 |
omap_mpuio_writefn, s); |
3047 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3048 |
|
3049 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
3050 |
|
3051 |
return s;
|
3052 |
} |
3053 |
|
3054 |
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
3055 |
{ |
3056 |
return s->in;
|
3057 |
} |
3058 |
|
3059 |
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
3060 |
{ |
3061 |
if (line >= 16 || line < 0) |
3062 |
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3063 |
s->handler[line] = handler; |
3064 |
} |
3065 |
|
3066 |
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
3067 |
{ |
3068 |
if (row >= 5 || row < 0) |
3069 |
cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
|
3070 |
__FUNCTION__, col, row); |
3071 |
|
3072 |
if (down)
|
3073 |
s->buttons[row] |= 1 << col;
|
3074 |
else
|
3075 |
s->buttons[row] &= ~(1 << col);
|
3076 |
|
3077 |
omap_mpuio_kbd_update(s); |
3078 |
} |
3079 |
|
3080 |
/* General-Purpose I/O */
|
3081 |
struct omap_gpio_s {
|
3082 |
target_phys_addr_t base; |
3083 |
qemu_irq irq; |
3084 |
qemu_irq *in; |
3085 |
qemu_irq handler[16];
|
3086 |
|
3087 |
uint16_t inputs; |
3088 |
uint16_t outputs; |
3089 |
uint16_t dir; |
3090 |
uint16_t edge; |
3091 |
uint16_t mask; |
3092 |
uint16_t ints; |
3093 |
}; |
3094 |
|
3095 |
static void omap_gpio_set(void *opaque, int line, int level) |
3096 |
{ |
3097 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3098 |
uint16_t prev = s->inputs; |
3099 |
|
3100 |
if (level)
|
3101 |
s->inputs |= 1 << line;
|
3102 |
else
|
3103 |
s->inputs &= ~(1 << line);
|
3104 |
|
3105 |
if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
|
3106 |
(1 << line) & s->dir & ~s->mask) {
|
3107 |
s->ints |= 1 << line;
|
3108 |
qemu_irq_raise(s->irq); |
3109 |
} |
3110 |
} |
3111 |
|
3112 |
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
3113 |
{ |
3114 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3115 |
int offset = addr - s->base;
|
3116 |
|
3117 |
switch (offset) {
|
3118 |
case 0x00: /* DATA_INPUT */ |
3119 |
return s->inputs;
|
3120 |
|
3121 |
case 0x04: /* DATA_OUTPUT */ |
3122 |
return s->outputs;
|
3123 |
|
3124 |
case 0x08: /* DIRECTION_CONTROL */ |
3125 |
return s->dir;
|
3126 |
|
3127 |
case 0x0c: /* INTERRUPT_CONTROL */ |
3128 |
return s->edge;
|
3129 |
|
3130 |
case 0x10: /* INTERRUPT_MASK */ |
3131 |
return s->mask;
|
3132 |
|
3133 |
case 0x14: /* INTERRUPT_STATUS */ |
3134 |
return s->ints;
|
3135 |
} |
3136 |
|
3137 |
OMAP_BAD_REG(addr); |
3138 |
return 0; |
3139 |
} |
3140 |
|
3141 |
static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
3142 |
uint32_t value) |
3143 |
{ |
3144 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
3145 |
int offset = addr - s->base;
|
3146 |
uint16_t diff; |
3147 |
int ln;
|
3148 |
|
3149 |
switch (offset) {
|
3150 |
case 0x00: /* DATA_INPUT */ |
3151 |
OMAP_RO_REG(addr); |
3152 |
return;
|
3153 |
|
3154 |
case 0x04: /* DATA_OUTPUT */ |
3155 |
diff = (s->outputs ^ value) & ~s->dir; |
3156 |
s->outputs = value; |
3157 |
while ((ln = ffs(diff))) {
|
3158 |
ln --; |
3159 |
if (s->handler[ln])
|
3160 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
3161 |
diff &= ~(1 << ln);
|
3162 |
} |
3163 |
break;
|
3164 |
|
3165 |
case 0x08: /* DIRECTION_CONTROL */ |
3166 |
diff = s->outputs & (s->dir ^ value); |
3167 |
s->dir = value; |
3168 |
|
3169 |
value = s->outputs & ~s->dir; |
3170 |
while ((ln = ffs(diff))) {
|
3171 |
ln --; |
3172 |
if (s->handler[ln])
|
3173 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
3174 |
diff &= ~(1 << ln);
|
3175 |
} |
3176 |
break;
|
3177 |
|
3178 |
case 0x0c: /* INTERRUPT_CONTROL */ |
3179 |
s->edge = value; |
3180 |
break;
|
3181 |
|
3182 |
case 0x10: /* INTERRUPT_MASK */ |
3183 |
s->mask = value; |
3184 |
break;
|
3185 |
|
3186 |
case 0x14: /* INTERRUPT_STATUS */ |
3187 |
s->ints &= ~value; |
3188 |
if (!s->ints)
|
3189 |
qemu_irq_lower(s->irq); |
3190 |
break;
|
3191 |
|
3192 |
default:
|
3193 |
OMAP_BAD_REG(addr); |
3194 |
return;
|
3195 |
} |
3196 |
} |
3197 |
|
3198 |
/* *Some* sources say the memory region is 32-bit. */
|
3199 |
static CPUReadMemoryFunc *omap_gpio_readfn[] = {
|
3200 |
omap_badwidth_read16, |
3201 |
omap_gpio_read, |
3202 |
omap_badwidth_read16, |
3203 |
}; |
3204 |
|
3205 |
static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
|
3206 |
omap_badwidth_write16, |
3207 |
omap_gpio_write, |
3208 |
omap_badwidth_write16, |
3209 |
}; |
3210 |
|
3211 |
void omap_gpio_reset(struct omap_gpio_s *s) |
3212 |
{ |
3213 |
s->inputs = 0;
|
3214 |
s->outputs = ~0;
|
3215 |
s->dir = ~0;
|
3216 |
s->edge = ~0;
|
3217 |
s->mask = ~0;
|
3218 |
s->ints = 0;
|
3219 |
} |
3220 |
|
3221 |
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
3222 |
qemu_irq irq, omap_clk clk) |
3223 |
{ |
3224 |
int iomemtype;
|
3225 |
struct omap_gpio_s *s = (struct omap_gpio_s *) |
3226 |
qemu_mallocz(sizeof(struct omap_gpio_s)); |
3227 |
|
3228 |
s->base = base; |
3229 |
s->irq = irq; |
3230 |
s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
|
3231 |
omap_gpio_reset(s); |
3232 |
|
3233 |
iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
|
3234 |
omap_gpio_writefn, s); |
3235 |
cpu_register_physical_memory(s->base, 0x1000, iomemtype);
|
3236 |
|
3237 |
return s;
|
3238 |
} |
3239 |
|
3240 |
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
|
3241 |
{ |
3242 |
return s->in;
|
3243 |
} |
3244 |
|
3245 |
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
3246 |
{ |
3247 |
if (line >= 16 || line < 0) |
3248 |
cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
|
3249 |
s->handler[line] = handler; |
3250 |
} |
3251 |
|
3252 |
/* MicroWire Interface */
|
3253 |
struct omap_uwire_s {
|
3254 |
target_phys_addr_t base; |
3255 |
qemu_irq txirq; |
3256 |
qemu_irq rxirq; |
3257 |
qemu_irq txdrq; |
3258 |
|
3259 |
uint16_t txbuf; |
3260 |
uint16_t rxbuf; |
3261 |
uint16_t control; |
3262 |
uint16_t setup[5];
|
3263 |
|
3264 |
struct uwire_slave_s *chip[4]; |
3265 |
}; |
3266 |
|
3267 |
static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
3268 |
{ |
3269 |
int chipselect = (s->control >> 10) & 3; /* INDEX */ |
3270 |
struct uwire_slave_s *slave = s->chip[chipselect];
|
3271 |
|
3272 |
if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
3273 |
if (s->control & (1 << 12)) /* CS_CMD */ |
3274 |
if (slave && slave->send)
|
3275 |
slave->send(slave->opaque, |
3276 |
s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
3277 |
s->control &= ~(1 << 14); /* CSRB */ |
3278 |
/* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
3279 |
* a DRQ. When is the level IRQ supposed to be reset? */
|
3280 |
} |
3281 |
|
3282 |
if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
3283 |
if (s->control & (1 << 12)) /* CS_CMD */ |
3284 |
if (slave && slave->receive)
|
3285 |
s->rxbuf = slave->receive(slave->opaque); |
3286 |
s->control |= 1 << 15; /* RDRB */ |
3287 |
/* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
3288 |
* a DRQ. When is the level IRQ supposed to be reset? */
|
3289 |
} |
3290 |
} |
3291 |
|
3292 |
static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) |
3293 |
{ |
3294 |
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
3295 |
int offset = addr - s->base;
|
3296 |
|
3297 |
switch (offset) {
|
3298 |
case 0x00: /* RDR */ |
3299 |
s->control &= ~(1 << 15); /* RDRB */ |
3300 |
return s->rxbuf;
|
3301 |
|
3302 |
case 0x04: /* CSR */ |
3303 |
return s->control;
|
3304 |
|
3305 |
case 0x08: /* SR1 */ |
3306 |
return s->setup[0]; |
3307 |
case 0x0c: /* SR2 */ |
3308 |
return s->setup[1]; |
3309 |
case 0x10: /* SR3 */ |
3310 |
return s->setup[2]; |
3311 |
case 0x14: /* SR4 */ |
3312 |
return s->setup[3]; |
3313 |
case 0x18: /* SR5 */ |
3314 |
return s->setup[4]; |
3315 |
} |
3316 |
|
3317 |
OMAP_BAD_REG(addr); |
3318 |
return 0; |
3319 |
} |
3320 |
|
3321 |
static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
3322 |
uint32_t value) |
3323 |
{ |
3324 |
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
3325 |
int offset = addr - s->base;
|
3326 |
|
3327 |
switch (offset) {
|
3328 |
case 0x00: /* TDR */ |
3329 |
s->txbuf = value; /* TD */
|
3330 |
s->control |= 1 << 14; /* CSRB */ |
3331 |
if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
3332 |
((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
3333 |
(s->control & (1 << 12)))) /* CS_CMD */ |
3334 |
omap_uwire_transfer_start(s); |
3335 |
break;
|
3336 |
|
3337 |
case 0x04: /* CSR */ |
3338 |
s->control = value & 0x1fff;
|
3339 |
if (value & (1 << 13)) /* START */ |
3340 |
omap_uwire_transfer_start(s); |
3341 |
break;
|
3342 |
|
3343 |
case 0x08: /* SR1 */ |
3344 |
s->setup[0] = value & 0x003f; |
3345 |
break;
|
3346 |
|
3347 |
case 0x0c: /* SR2 */ |
3348 |
s->setup[1] = value & 0x0fc0; |
3349 |
break;
|
3350 |
|
3351 |
case 0x10: /* SR3 */ |
3352 |
s->setup[2] = value & 0x0003; |
3353 |
break;
|
3354 |
|
3355 |
case 0x14: /* SR4 */ |
3356 |
s->setup[3] = value & 0x0001; |
3357 |
break;
|
3358 |
|
3359 |
case 0x18: /* SR5 */ |
3360 |
s->setup[4] = value & 0x000f; |
3361 |
break;
|
3362 |
|
3363 |
default:
|
3364 |
OMAP_BAD_REG(addr); |
3365 |
return;
|
3366 |
} |
3367 |
} |
3368 |
|
3369 |
static CPUReadMemoryFunc *omap_uwire_readfn[] = {
|
3370 |
omap_badwidth_read16, |
3371 |
omap_uwire_read, |
3372 |
omap_badwidth_read16, |
3373 |
}; |
3374 |
|
3375 |
static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
|
3376 |
omap_badwidth_write16, |
3377 |
omap_uwire_write, |
3378 |
omap_badwidth_write16, |
3379 |
}; |
3380 |
|
3381 |
void omap_uwire_reset(struct omap_uwire_s *s) |
3382 |
{ |
3383 |
s->control = 0;
|
3384 |
s->setup[0] = 0; |
3385 |
s->setup[1] = 0; |
3386 |
s->setup[2] = 0; |
3387 |
s->setup[3] = 0; |
3388 |
s->setup[4] = 0; |
3389 |
} |
3390 |
|
3391 |
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
3392 |
qemu_irq *irq, qemu_irq dma, omap_clk clk) |
3393 |
{ |
3394 |
int iomemtype;
|
3395 |
struct omap_uwire_s *s = (struct omap_uwire_s *) |
3396 |
qemu_mallocz(sizeof(struct omap_uwire_s)); |
3397 |
|
3398 |
s->base = base; |
3399 |
s->txirq = irq[0];
|
3400 |
s->rxirq = irq[1];
|
3401 |
s->txdrq = dma; |
3402 |
omap_uwire_reset(s); |
3403 |
|
3404 |
iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
|
3405 |
omap_uwire_writefn, s); |
3406 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
3407 |
|
3408 |
return s;
|
3409 |
} |
3410 |
|
3411 |
void omap_uwire_attach(struct omap_uwire_s *s, |
3412 |
struct uwire_slave_s *slave, int chipselect) |
3413 |
{ |
3414 |
if (chipselect < 0 || chipselect > 3) |
3415 |
cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", __FUNCTION__,
|
3416 |
chipselect); |
3417 |
|
3418 |
s->chip[chipselect] = slave; |
3419 |
} |
3420 |
|
3421 |
/* Pseudonoise Pulse-Width Light Modulator */
|
3422 |
void omap_pwl_update(struct omap_mpu_state_s *s) |
3423 |
{ |
3424 |
int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
3425 |
|
3426 |
if (output != s->pwl.output) {
|
3427 |
s->pwl.output = output; |
3428 |
printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
|
3429 |
} |
3430 |
} |
3431 |
|
3432 |
static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
3433 |
{ |
3434 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3435 |
int offset = addr - s->pwl.base;
|
3436 |
|
3437 |
switch (offset) {
|
3438 |
case 0x00: /* PWL_LEVEL */ |
3439 |
return s->pwl.level;
|
3440 |
case 0x04: /* PWL_CTRL */ |
3441 |
return s->pwl.enable;
|
3442 |
} |
3443 |
OMAP_BAD_REG(addr); |
3444 |
return 0; |
3445 |
} |
3446 |
|
3447 |
static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
3448 |
uint32_t value) |
3449 |
{ |
3450 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3451 |
int offset = addr - s->pwl.base;
|
3452 |
|
3453 |
switch (offset) {
|
3454 |
case 0x00: /* PWL_LEVEL */ |
3455 |
s->pwl.level = value; |
3456 |
omap_pwl_update(s); |
3457 |
break;
|
3458 |
case 0x04: /* PWL_CTRL */ |
3459 |
s->pwl.enable = value & 1;
|
3460 |
omap_pwl_update(s); |
3461 |
break;
|
3462 |
default:
|
3463 |
OMAP_BAD_REG(addr); |
3464 |
return;
|
3465 |
} |
3466 |
} |
3467 |
|
3468 |
static CPUReadMemoryFunc *omap_pwl_readfn[] = {
|
3469 |
omap_badwidth_read8, |
3470 |
omap_badwidth_read8, |
3471 |
omap_pwl_read, |
3472 |
}; |
3473 |
|
3474 |
static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
|
3475 |
omap_badwidth_write8, |
3476 |
omap_badwidth_write8, |
3477 |
omap_pwl_write, |
3478 |
}; |
3479 |
|
3480 |
void omap_pwl_reset(struct omap_mpu_state_s *s) |
3481 |
{ |
3482 |
s->pwl.output = 0;
|
3483 |
s->pwl.level = 0;
|
3484 |
s->pwl.enable = 0;
|
3485 |
s->pwl.clk = 1;
|
3486 |
omap_pwl_update(s); |
3487 |
} |
3488 |
|
3489 |
static void omap_pwl_clk_update(void *opaque, int line, int on) |
3490 |
{ |
3491 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3492 |
|
3493 |
s->pwl.clk = on; |
3494 |
omap_pwl_update(s); |
3495 |
} |
3496 |
|
3497 |
static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
3498 |
omap_clk clk) |
3499 |
{ |
3500 |
int iomemtype;
|
3501 |
|
3502 |
s->pwl.base = base; |
3503 |
omap_pwl_reset(s); |
3504 |
|
3505 |
iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
|
3506 |
omap_pwl_writefn, s); |
3507 |
cpu_register_physical_memory(s->pwl.base, 0x800, iomemtype);
|
3508 |
|
3509 |
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
3510 |
} |
3511 |
|
3512 |
/* Pulse-Width Tone module */
|
3513 |
static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) |
3514 |
{ |
3515 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3516 |
int offset = addr - s->pwt.base;
|
3517 |
|
3518 |
switch (offset) {
|
3519 |
case 0x00: /* FRC */ |
3520 |
return s->pwt.frc;
|
3521 |
case 0x04: /* VCR */ |
3522 |
return s->pwt.vrc;
|
3523 |
case 0x08: /* GCR */ |
3524 |
return s->pwt.gcr;
|
3525 |
} |
3526 |
OMAP_BAD_REG(addr); |
3527 |
return 0; |
3528 |
} |
3529 |
|
3530 |
static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
3531 |
uint32_t value) |
3532 |
{ |
3533 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
3534 |
int offset = addr - s->pwt.base;
|
3535 |
|
3536 |
switch (offset) {
|
3537 |
case 0x00: /* FRC */ |
3538 |
s->pwt.frc = value & 0x3f;
|
3539 |
break;
|
3540 |
case 0x04: /* VRC */ |
3541 |
if ((value ^ s->pwt.vrc) & 1) { |
3542 |
if (value & 1) |
3543 |
printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
3544 |
/* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
|
3545 |
((omap_clk_getrate(s->pwt.clk) >> 3) /
|
3546 |
/* Pre-multiplexer divider */
|
3547 |
((s->pwt.gcr & 2) ? 1 : 154) / |
3548 |
/* Octave multiplexer */
|
3549 |
(2 << (value & 3)) * |
3550 |
/* 101/107 divider */
|
3551 |
((value & (1 << 2)) ? 101 : 107) * |
3552 |
/* 49/55 divider */
|
3553 |
((value & (1 << 3)) ? 49 : 55) * |
3554 |
/* 50/63 divider */
|
3555 |
((value & (1 << 4)) ? 50 : 63) * |
3556 |
/* 80/127 divider */
|
3557 |
((value & (1 << 5)) ? 80 : 127) / |
3558 |
(107 * 55 * 63 * 127))); |
3559 |
else
|
3560 |
printf("%s: silence!\n", __FUNCTION__);
|
3561 |
} |
3562 |
s->pwt.vrc = value & 0x7f;
|
3563 |
break;
|
3564 |
case 0x08: /* GCR */ |
3565 |
s->pwt.gcr = value & 3;
|
3566 |
break;
|
3567 |
default:
|
3568 |
OMAP_BAD_REG(addr); |
3569 |
return;
|
3570 |
} |
3571 |
} |
3572 |
|
3573 |
static CPUReadMemoryFunc *omap_pwt_readfn[] = {
|
3574 |
omap_badwidth_read8, |
3575 |
omap_badwidth_read8, |
3576 |
omap_pwt_read, |
3577 |
}; |
3578 |
|
3579 |
static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
|
3580 |
omap_badwidth_write8, |
3581 |
omap_badwidth_write8, |
3582 |
omap_pwt_write, |
3583 |
}; |
3584 |
|
3585 |
void omap_pwt_reset(struct omap_mpu_state_s *s) |
3586 |
{ |
3587 |
s->pwt.frc = 0;
|
3588 |
s->pwt.vrc = 0;
|
3589 |
s->pwt.gcr = 0;
|
3590 |
} |
3591 |
|
3592 |
static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
3593 |
omap_clk clk) |
3594 |
{ |
3595 |
int iomemtype;
|
3596 |
|
3597 |
s->pwt.base = base; |
3598 |
s->pwt.clk = clk; |
3599 |
omap_pwt_reset(s); |
3600 |
|
3601 |
iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
|
3602 |
omap_pwt_writefn, s); |
3603 |
cpu_register_physical_memory(s->pwt.base, 0x800, iomemtype);
|
3604 |
} |
3605 |
|
3606 |
/* Inter-Integrated Circuit Controller (only the "New I2C") */
|
3607 |
struct omap_i2c_s {
|
3608 |
target_phys_addr_t base; |
3609 |
qemu_irq irq; |
3610 |
qemu_irq drq[2];
|
3611 |
i2c_slave slave; |
3612 |
i2c_bus *bus; |
3613 |
|
3614 |
uint8_t mask; |
3615 |
uint16_t stat; |
3616 |
uint16_t dma; |
3617 |
uint16_t count; |
3618 |
int count_cur;
|
3619 |
uint32_t fifo; |
3620 |
int rxlen;
|
3621 |
int txlen;
|
3622 |
uint16_t control; |
3623 |
uint16_t addr[2];
|
3624 |
uint8_t divider; |
3625 |
uint8_t times[2];
|
3626 |
uint16_t test; |
3627 |
}; |
3628 |
|
3629 |
static void omap_i2c_interrupts_update(struct omap_i2c_s *s) |
3630 |
{ |
3631 |
qemu_set_irq(s->irq, s->stat & s->mask); |
3632 |
if ((s->dma >> 15) & 1) /* RDMA_EN */ |
3633 |
qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ |
3634 |
if ((s->dma >> 7) & 1) /* XDMA_EN */ |
3635 |
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ |
3636 |
} |
3637 |
|
3638 |
/* These are only stubs now. */
|
3639 |
static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event) |
3640 |
{ |
3641 |
struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
3642 |
|
3643 |
if ((~s->control >> 15) & 1) /* I2C_EN */ |
3644 |
return;
|
3645 |
|
3646 |
switch (event) {
|
3647 |
case I2C_START_SEND:
|
3648 |
case I2C_START_RECV:
|
3649 |
s->stat |= 1 << 9; /* AAS */ |
3650 |
break;
|
3651 |
case I2C_FINISH:
|
3652 |
s->stat |= 1 << 2; /* ARDY */ |
3653 |
break;
|
3654 |
case I2C_NACK:
|
3655 |
s->stat |= 1 << 1; /* NACK */ |
3656 |
break;
|
3657 |
} |
3658 |
|
3659 |
omap_i2c_interrupts_update(s); |
3660 |
} |
3661 |
|
3662 |
static int omap_i2c_rx(i2c_slave *i2c) |
3663 |
{ |
3664 |
struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
3665 |
uint8_t ret = 0;
|
3666 |
|
3667 |
if ((~s->control >> 15) & 1) /* I2C_EN */ |
3668 |
return -1; |
3669 |
|
3670 |
if (s->txlen)
|
3671 |
ret = s->fifo >> ((-- s->txlen) << 3) & 0xff; |
3672 |
else
|
3673 |
s->stat |= 1 << 10; /* XUDF */ |
3674 |
s->stat |= 1 << 4; /* XRDY */ |
3675 |
|
3676 |
omap_i2c_interrupts_update(s); |
3677 |
return ret;
|
3678 |
} |
3679 |
|
3680 |
static int omap_i2c_tx(i2c_slave *i2c, uint8_t data) |
3681 |
{ |
3682 |
struct omap_i2c_s *s = (struct omap_i2c_s *) i2c; |
3683 |
|
3684 |
if ((~s->control >> 15) & 1) /* I2C_EN */ |
3685 |
return 1; |
3686 |
|
3687 |
if (s->rxlen < 4) |
3688 |
s->fifo |= data << ((s->rxlen ++) << 3);
|
3689 |
else
|
3690 |
s->stat |= 1 << 11; /* ROVR */ |
3691 |
s->stat |= 1 << 3; /* RRDY */ |
3692 |
|
3693 |
omap_i2c_interrupts_update(s); |
3694 |
return 1; |
3695 |
} |
3696 |
|
3697 |
static void omap_i2c_fifo_run(struct omap_i2c_s *s) |
3698 |
{ |
3699 |
int ack = 1; |
3700 |
|
3701 |
if (!i2c_bus_busy(s->bus))
|
3702 |
return;
|
3703 |
|
3704 |
if ((s->control >> 2) & 1) { /* RM */ |
3705 |
if ((s->control >> 1) & 1) { /* STP */ |
3706 |
i2c_end_transfer(s->bus); |
3707 |
s->control &= ~(1 << 1); /* STP */ |
3708 |
s->count_cur = s->count; |
3709 |
} else if ((s->control >> 9) & 1) { /* TRX */ |
3710 |
while (ack && s->txlen)
|
3711 |
ack = (i2c_send(s->bus, |
3712 |
(s->fifo >> ((-- s->txlen) << 3)) &
|
3713 |
0xff) >= 0); |
3714 |
s->stat |= 1 << 4; /* XRDY */ |
3715 |
} else {
|
3716 |
while (s->rxlen < 4) |
3717 |
s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
|
3718 |
s->stat |= 1 << 3; /* RRDY */ |
3719 |
} |
3720 |
} else {
|
3721 |
if ((s->control >> 9) & 1) { /* TRX */ |
3722 |
while (ack && s->count_cur && s->txlen) {
|
3723 |
ack = (i2c_send(s->bus, |
3724 |
(s->fifo >> ((-- s->txlen) << 3)) &
|
3725 |
0xff) >= 0); |
3726 |
s->count_cur --; |
3727 |
} |
3728 |
if (ack && s->count_cur)
|
3729 |
s->stat |= 1 << 4; /* XRDY */ |
3730 |
if (!s->count_cur) {
|
3731 |
s->stat |= 1 << 2; /* ARDY */ |
3732 |
s->control &= ~(1 << 10); /* MST */ |
3733 |
} |
3734 |
} else {
|
3735 |
while (s->count_cur && s->rxlen < 4) { |
3736 |
s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
|
3737 |
s->count_cur --; |
3738 |
} |
3739 |
if (s->rxlen)
|
3740 |
s->stat |= 1 << 3; /* RRDY */ |
3741 |
} |
3742 |
if (!s->count_cur) {
|
3743 |
if ((s->control >> 1) & 1) { /* STP */ |
3744 |
i2c_end_transfer(s->bus); |
3745 |
s->control &= ~(1 << 1); /* STP */ |
3746 |
s->count_cur = s->count; |
3747 |
} else {
|
3748 |
s->stat |= 1 << 2; /* ARDY */ |
3749 |
s->control &= ~(1 << 10); /* MST */ |
3750 |
} |
3751 |
} |
3752 |
} |
3753 |
|
3754 |
s->stat |= (!ack) << 1; /* NACK */ |
3755 |
if (!ack)
|
3756 |
s->control &= ~(1 << 1); /* STP */ |
3757 |
} |
3758 |
|
3759 |
static void omap_i2c_reset(struct omap_i2c_s *s) |
3760 |
{ |
3761 |
s->mask = 0;
|
3762 |
s->stat = 0;
|
3763 |
s->dma = 0;
|
3764 |
s->count = 0;
|
3765 |
s->count_cur = 0;
|
3766 |
s->fifo = 0;
|
3767 |
s->rxlen = 0;
|
3768 |
s->txlen = 0;
|
3769 |
s->control = 0;
|
3770 |
s->addr[0] = 0; |
3771 |
s->addr[1] = 0; |
3772 |
s->divider = 0;
|
3773 |
s->times[0] = 0; |
3774 |
s->times[1] = 0; |
3775 |
s->test = 0;
|
3776 |
} |
3777 |
|
3778 |
static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) |
3779 |
{ |
3780 |
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
3781 |
int offset = addr - s->base;
|
3782 |
uint16_t ret; |
3783 |
|
3784 |
switch (offset) {
|
3785 |
case 0x00: /* I2C_REV */ |
3786 |
/* TODO: set a value greater or equal to real hardware */
|
3787 |
return 0x11; /* REV */ |
3788 |
|
3789 |
case 0x04: /* I2C_IE */ |
3790 |
return s->mask;
|
3791 |
|
3792 |
case 0x08: /* I2C_STAT */ |
3793 |
return s->stat | (i2c_bus_busy(s->bus) << 12); |
3794 |
|
3795 |
case 0x0c: /* I2C_IV */ |
3796 |
ret = ffs(s->stat & s->mask); |
3797 |
if (ret)
|
3798 |
s->stat ^= 1 << (ret - 1); |
3799 |
omap_i2c_interrupts_update(s); |
3800 |
return ret;
|
3801 |
|
3802 |
case 0x14: /* I2C_BUF */ |
3803 |
return s->dma;
|
3804 |
|
3805 |
case 0x18: /* I2C_CNT */ |
3806 |
return s->count_cur; /* DCOUNT */ |
3807 |
|
3808 |
case 0x1c: /* I2C_DATA */ |
3809 |
ret = 0;
|
3810 |
if (s->control & (1 << 14)) { /* BE */ |
3811 |
ret |= ((s->fifo >> 0) & 0xff) << 8; |
3812 |
ret |= ((s->fifo >> 8) & 0xff) << 0; |
3813 |
} else {
|
3814 |
ret |= ((s->fifo >> 8) & 0xff) << 8; |
3815 |
ret |= ((s->fifo >> 0) & 0xff) << 0; |
3816 |
} |
3817 |
if (s->rxlen == 1) { |
3818 |
s->stat |= 1 << 15; /* SBD */ |
3819 |
s->rxlen = 0;
|
3820 |
} else if (s->rxlen > 1) { |
3821 |
if (s->rxlen > 2) |
3822 |
s->fifo >>= 16;
|
3823 |
s->rxlen -= 2;
|
3824 |
} else
|
3825 |
/* XXX: remote access (qualifier) error - what's that? */;
|
3826 |
if (!s->rxlen) {
|
3827 |
s->stat |= ~(1 << 3); /* RRDY */ |
3828 |
if (((s->control >> 10) & 1) && /* MST */ |
3829 |
((~s->control >> 9) & 1)) { /* TRX */ |
3830 |
s->stat |= 1 << 2; /* ARDY */ |
3831 |
s->control &= ~(1 << 10); /* MST */ |
3832 |
} |
3833 |
} |
3834 |
s->stat &= ~(1 << 11); /* ROVR */ |
3835 |
omap_i2c_fifo_run(s); |
3836 |
omap_i2c_interrupts_update(s); |
3837 |
return ret;
|
3838 |
|
3839 |
case 0x24: /* I2C_CON */ |
3840 |
return s->control;
|
3841 |
|
3842 |
case 0x28: /* I2C_OA */ |
3843 |
return s->addr[0]; |
3844 |
|
3845 |
case 0x2c: /* I2C_SA */ |
3846 |
return s->addr[1]; |
3847 |
|
3848 |
case 0x30: /* I2C_PSC */ |
3849 |
return s->divider;
|
3850 |
|
3851 |
case 0x34: /* I2C_SCLL */ |
3852 |
return s->times[0]; |
3853 |
|
3854 |
case 0x38: /* I2C_SCLH */ |
3855 |
return s->times[1]; |
3856 |
|
3857 |
case 0x3c: /* I2C_SYSTEST */ |
3858 |
if (s->test & (1 << 15)) { /* ST_EN */ |
3859 |
s->test ^= 0xa;
|
3860 |
return s->test;
|
3861 |
} else
|
3862 |
return s->test & ~0x300f; |
3863 |
} |
3864 |
|
3865 |
OMAP_BAD_REG(addr); |
3866 |
return 0; |
3867 |
} |
3868 |
|
3869 |
static void omap_i2c_write(void *opaque, target_phys_addr_t addr, |
3870 |
uint32_t value) |
3871 |
{ |
3872 |
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
3873 |
int offset = addr - s->base;
|
3874 |
int nack;
|
3875 |
|
3876 |
switch (offset) {
|
3877 |
case 0x00: /* I2C_REV */ |
3878 |
case 0x08: /* I2C_STAT */ |
3879 |
case 0x0c: /* I2C_IV */ |
3880 |
OMAP_BAD_REG(addr); |
3881 |
return;
|
3882 |
|
3883 |
case 0x04: /* I2C_IE */ |
3884 |
s->mask = value & 0x1f;
|
3885 |
break;
|
3886 |
|
3887 |
case 0x14: /* I2C_BUF */ |
3888 |
s->dma = value & 0x8080;
|
3889 |
if (value & (1 << 15)) /* RDMA_EN */ |
3890 |
s->mask &= ~(1 << 3); /* RRDY_IE */ |
3891 |
if (value & (1 << 7)) /* XDMA_EN */ |
3892 |
s->mask &= ~(1 << 4); /* XRDY_IE */ |
3893 |
break;
|
3894 |
|
3895 |
case 0x18: /* I2C_CNT */ |
3896 |
s->count = value; /* DCOUNT */
|
3897 |
break;
|
3898 |
|
3899 |
case 0x1c: /* I2C_DATA */ |
3900 |
if (s->txlen > 2) { |
3901 |
/* XXX: remote access (qualifier) error - what's that? */
|
3902 |
break;
|
3903 |
} |
3904 |
s->fifo <<= 16;
|
3905 |
s->txlen += 2;
|
3906 |
if (s->control & (1 << 14)) { /* BE */ |
3907 |
s->fifo |= ((value >> 8) & 0xff) << 8; |
3908 |
s->fifo |= ((value >> 0) & 0xff) << 0; |
3909 |
} else {
|
3910 |
s->fifo |= ((value >> 0) & 0xff) << 8; |
3911 |
s->fifo |= ((value >> 8) & 0xff) << 0; |
3912 |
} |
3913 |
s->stat &= ~(1 << 10); /* XUDF */ |
3914 |
if (s->txlen > 2) |
3915 |
s->stat &= ~(1 << 4); /* XRDY */ |
3916 |
omap_i2c_fifo_run(s); |
3917 |
omap_i2c_interrupts_update(s); |
3918 |
break;
|
3919 |
|
3920 |
case 0x24: /* I2C_CON */ |
3921 |
s->control = value & 0xcf07;
|
3922 |
if (~value & (1 << 15)) { /* I2C_EN */ |
3923 |
omap_i2c_reset(s); |
3924 |
break;
|
3925 |
} |
3926 |
if (~value & (1 << 10)) { /* MST */ |
3927 |
printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
|
3928 |
break;
|
3929 |
} |
3930 |
if (value & (1 << 9)) { /* XA */ |
3931 |
printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
|
3932 |
break;
|
3933 |
} |
3934 |
if (value & (1 << 0)) { /* STT */ |
3935 |
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ |
3936 |
(~value >> 9) & 1); /* TRX */ |
3937 |
s->stat |= nack << 1; /* NACK */ |
3938 |
s->control &= ~(1 << 0); /* STT */ |
3939 |
if (nack)
|
3940 |
s->control &= ~(1 << 1); /* STP */ |
3941 |
else
|
3942 |
omap_i2c_fifo_run(s); |
3943 |
omap_i2c_interrupts_update(s); |
3944 |
} |
3945 |
break;
|
3946 |
|
3947 |
case 0x28: /* I2C_OA */ |
3948 |
s->addr[0] = value & 0x3ff; |
3949 |
i2c_set_slave_address(&s->slave, value & 0x7f);
|
3950 |
break;
|
3951 |
|
3952 |
case 0x2c: /* I2C_SA */ |
3953 |
s->addr[1] = value & 0x3ff; |
3954 |
break;
|
3955 |
|
3956 |
case 0x30: /* I2C_PSC */ |
3957 |
s->divider = value; |
3958 |
break;
|
3959 |
|
3960 |
case 0x34: /* I2C_SCLL */ |
3961 |
s->times[0] = value;
|
3962 |
break;
|
3963 |
|
3964 |
case 0x38: /* I2C_SCLH */ |
3965 |
s->times[1] = value;
|
3966 |
break;
|
3967 |
|
3968 |
case 0x3c: /* I2C_SYSTEST */ |
3969 |
s->test = value & 0xf00f;
|
3970 |
if (value & (1 << 15)) /* ST_EN */ |
3971 |
printf("%s: System Test not supported\n", __FUNCTION__);
|
3972 |
break;
|
3973 |
|
3974 |
default:
|
3975 |
OMAP_BAD_REG(addr); |
3976 |
return;
|
3977 |
} |
3978 |
} |
3979 |
|
3980 |
static CPUReadMemoryFunc *omap_i2c_readfn[] = {
|
3981 |
omap_badwidth_read16, |
3982 |
omap_i2c_read, |
3983 |
omap_badwidth_read16, |
3984 |
}; |
3985 |
|
3986 |
static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
|
3987 |
omap_badwidth_write16, |
3988 |
omap_i2c_write, |
3989 |
omap_i2c_write, /* TODO: Only the last fifo write can be 8 bit. */
|
3990 |
}; |
3991 |
|
3992 |
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
3993 |
qemu_irq irq, qemu_irq *dma, omap_clk clk) |
3994 |
{ |
3995 |
int iomemtype;
|
3996 |
struct omap_i2c_s *s = (struct omap_i2c_s *) |
3997 |
qemu_mallocz(sizeof(struct omap_i2c_s)); |
3998 |
|
3999 |
s->base = base; |
4000 |
s->irq = irq; |
4001 |
s->drq[0] = dma[0]; |
4002 |
s->drq[1] = dma[1]; |
4003 |
s->slave.event = omap_i2c_event; |
4004 |
s->slave.recv = omap_i2c_rx; |
4005 |
s->slave.send = omap_i2c_tx; |
4006 |
s->bus = i2c_init_bus(); |
4007 |
omap_i2c_reset(s); |
4008 |
|
4009 |
iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
|
4010 |
omap_i2c_writefn, s); |
4011 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4012 |
|
4013 |
return s;
|
4014 |
} |
4015 |
|
4016 |
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
|
4017 |
{ |
4018 |
return s->bus;
|
4019 |
} |
4020 |
|
4021 |
/* Real-time Clock module */
|
4022 |
struct omap_rtc_s {
|
4023 |
target_phys_addr_t base; |
4024 |
qemu_irq irq; |
4025 |
qemu_irq alarm; |
4026 |
QEMUTimer *clk; |
4027 |
|
4028 |
uint8_t interrupts; |
4029 |
uint8_t status; |
4030 |
int16_t comp_reg; |
4031 |
int running;
|
4032 |
int pm_am;
|
4033 |
int auto_comp;
|
4034 |
int round;
|
4035 |
struct tm *(*convert)(const time_t *timep, struct tm *result); |
4036 |
struct tm alarm_tm;
|
4037 |
time_t alarm_ti; |
4038 |
|
4039 |
struct tm current_tm;
|
4040 |
time_t ti; |
4041 |
uint64_t tick; |
4042 |
}; |
4043 |
|
4044 |
static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
4045 |
{ |
4046 |
qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
4047 |
} |
4048 |
|
4049 |
static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
4050 |
{ |
4051 |
s->alarm_ti = mktime(&s->alarm_tm); |
4052 |
if (s->alarm_ti == -1) |
4053 |
printf("%s: conversion failed\n", __FUNCTION__);
|
4054 |
} |
4055 |
|
4056 |
static inline uint8_t omap_rtc_bcd(int num) |
4057 |
{ |
4058 |
return ((num / 10) << 4) | (num % 10); |
4059 |
} |
4060 |
|
4061 |
static inline int omap_rtc_bin(uint8_t num) |
4062 |
{ |
4063 |
return (num & 15) + 10 * (num >> 4); |
4064 |
} |
4065 |
|
4066 |
static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) |
4067 |
{ |
4068 |
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
4069 |
int offset = addr - s->base;
|
4070 |
uint8_t i; |
4071 |
|
4072 |
switch (offset) {
|
4073 |
case 0x00: /* SECONDS_REG */ |
4074 |
return omap_rtc_bcd(s->current_tm.tm_sec);
|
4075 |
|
4076 |
case 0x04: /* MINUTES_REG */ |
4077 |
return omap_rtc_bcd(s->current_tm.tm_min);
|
4078 |
|
4079 |
case 0x08: /* HOURS_REG */ |
4080 |
if (s->pm_am)
|
4081 |
return ((s->current_tm.tm_hour > 11) << 7) | |
4082 |
omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
4083 |
else
|
4084 |
return omap_rtc_bcd(s->current_tm.tm_hour);
|
4085 |
|
4086 |
case 0x0c: /* DAYS_REG */ |
4087 |
return omap_rtc_bcd(s->current_tm.tm_mday);
|
4088 |
|
4089 |
case 0x10: /* MONTHS_REG */ |
4090 |
return omap_rtc_bcd(s->current_tm.tm_mon + 1); |
4091 |
|
4092 |
case 0x14: /* YEARS_REG */ |
4093 |
return omap_rtc_bcd(s->current_tm.tm_year % 100); |
4094 |
|
4095 |
case 0x18: /* WEEK_REG */ |
4096 |
return s->current_tm.tm_wday;
|
4097 |
|
4098 |
case 0x20: /* ALARM_SECONDS_REG */ |
4099 |
return omap_rtc_bcd(s->alarm_tm.tm_sec);
|
4100 |
|
4101 |
case 0x24: /* ALARM_MINUTES_REG */ |
4102 |
return omap_rtc_bcd(s->alarm_tm.tm_min);
|
4103 |
|
4104 |
case 0x28: /* ALARM_HOURS_REG */ |
4105 |
if (s->pm_am)
|
4106 |
return ((s->alarm_tm.tm_hour > 11) << 7) | |
4107 |
omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
4108 |
else
|
4109 |
return omap_rtc_bcd(s->alarm_tm.tm_hour);
|
4110 |
|
4111 |
case 0x2c: /* ALARM_DAYS_REG */ |
4112 |
return omap_rtc_bcd(s->alarm_tm.tm_mday);
|
4113 |
|
4114 |
case 0x30: /* ALARM_MONTHS_REG */ |
4115 |
return omap_rtc_bcd(s->alarm_tm.tm_mon + 1); |
4116 |
|
4117 |
case 0x34: /* ALARM_YEARS_REG */ |
4118 |
return omap_rtc_bcd(s->alarm_tm.tm_year % 100); |
4119 |
|
4120 |
case 0x40: /* RTC_CTRL_REG */ |
4121 |
return (s->pm_am << 3) | (s->auto_comp << 2) | |
4122 |
(s->round << 1) | s->running;
|
4123 |
|
4124 |
case 0x44: /* RTC_STATUS_REG */ |
4125 |
i = s->status; |
4126 |
s->status &= ~0x3d;
|
4127 |
return i;
|
4128 |
|
4129 |
case 0x48: /* RTC_INTERRUPTS_REG */ |
4130 |
return s->interrupts;
|
4131 |
|
4132 |
case 0x4c: /* RTC_COMP_LSB_REG */ |
4133 |
return ((uint16_t) s->comp_reg) & 0xff; |
4134 |
|
4135 |
case 0x50: /* RTC_COMP_MSB_REG */ |
4136 |
return ((uint16_t) s->comp_reg) >> 8; |
4137 |
} |
4138 |
|
4139 |
OMAP_BAD_REG(addr); |
4140 |
return 0; |
4141 |
} |
4142 |
|
4143 |
static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
4144 |
uint32_t value) |
4145 |
{ |
4146 |
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
4147 |
int offset = addr - s->base;
|
4148 |
struct tm new_tm;
|
4149 |
time_t ti[2];
|
4150 |
|
4151 |
switch (offset) {
|
4152 |
case 0x00: /* SECONDS_REG */ |
4153 |
#if ALMDEBUG
|
4154 |
printf("RTC SEC_REG <-- %02x\n", value);
|
4155 |
#endif
|
4156 |
s->ti -= s->current_tm.tm_sec; |
4157 |
s->ti += omap_rtc_bin(value); |
4158 |
return;
|
4159 |
|
4160 |
case 0x04: /* MINUTES_REG */ |
4161 |
#if ALMDEBUG
|
4162 |
printf("RTC MIN_REG <-- %02x\n", value);
|
4163 |
#endif
|
4164 |
s->ti -= s->current_tm.tm_min * 60;
|
4165 |
s->ti += omap_rtc_bin(value) * 60;
|
4166 |
return;
|
4167 |
|
4168 |
case 0x08: /* HOURS_REG */ |
4169 |
#if ALMDEBUG
|
4170 |
printf("RTC HRS_REG <-- %02x\n", value);
|
4171 |
#endif
|
4172 |
s->ti -= s->current_tm.tm_hour * 3600;
|
4173 |
if (s->pm_am) {
|
4174 |
s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600; |
4175 |
s->ti += ((value >> 7) & 1) * 43200; |
4176 |
} else
|
4177 |
s->ti += omap_rtc_bin(value & 0x3f) * 3600; |
4178 |
return;
|
4179 |
|
4180 |
case 0x0c: /* DAYS_REG */ |
4181 |
#if ALMDEBUG
|
4182 |
printf("RTC DAY_REG <-- %02x\n", value);
|
4183 |
#endif
|
4184 |
s->ti -= s->current_tm.tm_mday * 86400;
|
4185 |
s->ti += omap_rtc_bin(value) * 86400;
|
4186 |
return;
|
4187 |
|
4188 |
case 0x10: /* MONTHS_REG */ |
4189 |
#if ALMDEBUG
|
4190 |
printf("RTC MTH_REG <-- %02x\n", value);
|
4191 |
#endif
|
4192 |
memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
4193 |
new_tm.tm_mon = omap_rtc_bin(value); |
4194 |
ti[0] = mktime(&s->current_tm);
|
4195 |
ti[1] = mktime(&new_tm);
|
4196 |
|
4197 |
if (ti[0] != -1 && ti[1] != -1) { |
4198 |
s->ti -= ti[0];
|
4199 |
s->ti += ti[1];
|
4200 |
} else {
|
4201 |
/* A less accurate version */
|
4202 |
s->ti -= s->current_tm.tm_mon * 2592000;
|
4203 |
s->ti += omap_rtc_bin(value) * 2592000;
|
4204 |
} |
4205 |
return;
|
4206 |
|
4207 |
case 0x14: /* YEARS_REG */ |
4208 |
#if ALMDEBUG
|
4209 |
printf("RTC YRS_REG <-- %02x\n", value);
|
4210 |
#endif
|
4211 |
memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
4212 |
new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
|
4213 |
ti[0] = mktime(&s->current_tm);
|
4214 |
ti[1] = mktime(&new_tm);
|
4215 |
|
4216 |
if (ti[0] != -1 && ti[1] != -1) { |
4217 |
s->ti -= ti[0];
|
4218 |
s->ti += ti[1];
|
4219 |
} else {
|
4220 |
/* A less accurate version */
|
4221 |
s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
4222 |
s->ti += omap_rtc_bin(value) * 31536000;
|
4223 |
} |
4224 |
return;
|
4225 |
|
4226 |
case 0x18: /* WEEK_REG */ |
4227 |
return; /* Ignored */ |
4228 |
|
4229 |
case 0x20: /* ALARM_SECONDS_REG */ |
4230 |
#if ALMDEBUG
|
4231 |
printf("ALM SEC_REG <-- %02x\n", value);
|
4232 |
#endif
|
4233 |
s->alarm_tm.tm_sec = omap_rtc_bin(value); |
4234 |
omap_rtc_alarm_update(s); |
4235 |
return;
|
4236 |
|
4237 |
case 0x24: /* ALARM_MINUTES_REG */ |
4238 |
#if ALMDEBUG
|
4239 |
printf("ALM MIN_REG <-- %02x\n", value);
|
4240 |
#endif
|
4241 |
s->alarm_tm.tm_min = omap_rtc_bin(value); |
4242 |
omap_rtc_alarm_update(s); |
4243 |
return;
|
4244 |
|
4245 |
case 0x28: /* ALARM_HOURS_REG */ |
4246 |
#if ALMDEBUG
|
4247 |
printf("ALM HRS_REG <-- %02x\n", value);
|
4248 |
#endif
|
4249 |
if (s->pm_am)
|
4250 |
s->alarm_tm.tm_hour = |
4251 |
((omap_rtc_bin(value & 0x3f)) % 12) + |
4252 |
((value >> 7) & 1) * 12; |
4253 |
else
|
4254 |
s->alarm_tm.tm_hour = omap_rtc_bin(value); |
4255 |
omap_rtc_alarm_update(s); |
4256 |
return;
|
4257 |
|
4258 |
case 0x2c: /* ALARM_DAYS_REG */ |
4259 |
#if ALMDEBUG
|
4260 |
printf("ALM DAY_REG <-- %02x\n", value);
|
4261 |
#endif
|
4262 |
s->alarm_tm.tm_mday = omap_rtc_bin(value); |
4263 |
omap_rtc_alarm_update(s); |
4264 |
return;
|
4265 |
|
4266 |
case 0x30: /* ALARM_MONTHS_REG */ |
4267 |
#if ALMDEBUG
|
4268 |
printf("ALM MON_REG <-- %02x\n", value);
|
4269 |
#endif
|
4270 |
s->alarm_tm.tm_mon = omap_rtc_bin(value); |
4271 |
omap_rtc_alarm_update(s); |
4272 |
return;
|
4273 |
|
4274 |
case 0x34: /* ALARM_YEARS_REG */ |
4275 |
#if ALMDEBUG
|
4276 |
printf("ALM YRS_REG <-- %02x\n", value);
|
4277 |
#endif
|
4278 |
s->alarm_tm.tm_year = omap_rtc_bin(value); |
4279 |
omap_rtc_alarm_update(s); |
4280 |
return;
|
4281 |
|
4282 |
case 0x40: /* RTC_CTRL_REG */ |
4283 |
#if ALMDEBUG
|
4284 |
printf("RTC CONTROL <-- %02x\n", value);
|
4285 |
#endif
|
4286 |
s->pm_am = (value >> 3) & 1; |
4287 |
s->auto_comp = (value >> 2) & 1; |
4288 |
s->round = (value >> 1) & 1; |
4289 |
s->running = value & 1;
|
4290 |
s->status &= 0xfd;
|
4291 |
s->status |= s->running << 1;
|
4292 |
return;
|
4293 |
|
4294 |
case 0x44: /* RTC_STATUS_REG */ |
4295 |
#if ALMDEBUG
|
4296 |
printf("RTC STATUSL <-- %02x\n", value);
|
4297 |
#endif
|
4298 |
s->status &= ~((value & 0xc0) ^ 0x80); |
4299 |
omap_rtc_interrupts_update(s); |
4300 |
return;
|
4301 |
|
4302 |
case 0x48: /* RTC_INTERRUPTS_REG */ |
4303 |
#if ALMDEBUG
|
4304 |
printf("RTC INTRS <-- %02x\n", value);
|
4305 |
#endif
|
4306 |
s->interrupts = value; |
4307 |
return;
|
4308 |
|
4309 |
case 0x4c: /* RTC_COMP_LSB_REG */ |
4310 |
#if ALMDEBUG
|
4311 |
printf("RTC COMPLSB <-- %02x\n", value);
|
4312 |
#endif
|
4313 |
s->comp_reg &= 0xff00;
|
4314 |
s->comp_reg |= 0x00ff & value;
|
4315 |
return;
|
4316 |
|
4317 |
case 0x50: /* RTC_COMP_MSB_REG */ |
4318 |
#if ALMDEBUG
|
4319 |
printf("RTC COMPMSB <-- %02x\n", value);
|
4320 |
#endif
|
4321 |
s->comp_reg &= 0x00ff;
|
4322 |
s->comp_reg |= 0xff00 & (value << 8); |
4323 |
return;
|
4324 |
|
4325 |
default:
|
4326 |
OMAP_BAD_REG(addr); |
4327 |
return;
|
4328 |
} |
4329 |
} |
4330 |
|
4331 |
static CPUReadMemoryFunc *omap_rtc_readfn[] = {
|
4332 |
omap_rtc_read, |
4333 |
omap_badwidth_read8, |
4334 |
omap_badwidth_read8, |
4335 |
}; |
4336 |
|
4337 |
static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
|
4338 |
omap_rtc_write, |
4339 |
omap_badwidth_write8, |
4340 |
omap_badwidth_write8, |
4341 |
}; |
4342 |
|
4343 |
static void omap_rtc_tick(void *opaque) |
4344 |
{ |
4345 |
struct omap_rtc_s *s = opaque;
|
4346 |
|
4347 |
if (s->round) {
|
4348 |
/* Round to nearest full minute. */
|
4349 |
if (s->current_tm.tm_sec < 30) |
4350 |
s->ti -= s->current_tm.tm_sec; |
4351 |
else
|
4352 |
s->ti += 60 - s->current_tm.tm_sec;
|
4353 |
|
4354 |
s->round = 0;
|
4355 |
} |
4356 |
|
4357 |
localtime_r(&s->ti, &s->current_tm); |
4358 |
|
4359 |
if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
4360 |
s->status |= 0x40;
|
4361 |
omap_rtc_interrupts_update(s); |
4362 |
} |
4363 |
|
4364 |
if (s->interrupts & 0x04) |
4365 |
switch (s->interrupts & 3) { |
4366 |
case 0: |
4367 |
s->status |= 0x04;
|
4368 |
qemu_irq_raise(s->irq); |
4369 |
break;
|
4370 |
case 1: |
4371 |
if (s->current_tm.tm_sec)
|
4372 |
break;
|
4373 |
s->status |= 0x08;
|
4374 |
qemu_irq_raise(s->irq); |
4375 |
break;
|
4376 |
case 2: |
4377 |
if (s->current_tm.tm_sec || s->current_tm.tm_min)
|
4378 |
break;
|
4379 |
s->status |= 0x10;
|
4380 |
qemu_irq_raise(s->irq); |
4381 |
break;
|
4382 |
case 3: |
4383 |
if (s->current_tm.tm_sec ||
|
4384 |
s->current_tm.tm_min || s->current_tm.tm_hour) |
4385 |
break;
|
4386 |
s->status |= 0x20;
|
4387 |
qemu_irq_raise(s->irq); |
4388 |
break;
|
4389 |
} |
4390 |
|
4391 |
/* Move on */
|
4392 |
if (s->running)
|
4393 |
s->ti ++; |
4394 |
s->tick += 1000;
|
4395 |
|
4396 |
/*
|
4397 |
* Every full hour add a rough approximation of the compensation
|
4398 |
* register to the 32kHz Timer (which drives the RTC) value.
|
4399 |
*/
|
4400 |
if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
|
4401 |
s->tick += s->comp_reg * 1000 / 32768; |
4402 |
|
4403 |
qemu_mod_timer(s->clk, s->tick); |
4404 |
} |
4405 |
|
4406 |
void omap_rtc_reset(struct omap_rtc_s *s) |
4407 |
{ |
4408 |
s->interrupts = 0;
|
4409 |
s->comp_reg = 0;
|
4410 |
s->running = 0;
|
4411 |
s->pm_am = 0;
|
4412 |
s->auto_comp = 0;
|
4413 |
s->round = 0;
|
4414 |
s->tick = qemu_get_clock(rt_clock); |
4415 |
memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
4416 |
s->alarm_tm.tm_mday = 0x01;
|
4417 |
s->status = 1 << 7; |
4418 |
time(&s->ti); |
4419 |
s->ti = mktime(s->convert(&s->ti, &s->current_tm)); |
4420 |
|
4421 |
omap_rtc_alarm_update(s); |
4422 |
omap_rtc_tick(s); |
4423 |
} |
4424 |
|
4425 |
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
4426 |
qemu_irq *irq, omap_clk clk) |
4427 |
{ |
4428 |
int iomemtype;
|
4429 |
struct omap_rtc_s *s = (struct omap_rtc_s *) |
4430 |
qemu_mallocz(sizeof(struct omap_rtc_s)); |
4431 |
|
4432 |
s->base = base; |
4433 |
s->irq = irq[0];
|
4434 |
s->alarm = irq[1];
|
4435 |
s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
4436 |
s->convert = rtc_utc ? gmtime_r : localtime_r; |
4437 |
|
4438 |
omap_rtc_reset(s); |
4439 |
|
4440 |
iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
|
4441 |
omap_rtc_writefn, s); |
4442 |
cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
4443 |
|
4444 |
return s;
|
4445 |
} |
4446 |
|
4447 |
/* General chip reset */
|
4448 |
static void omap_mpu_reset(void *opaque) |
4449 |
{ |
4450 |
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4451 |
|
4452 |
omap_clkm_reset(mpu); |
4453 |
omap_inth_reset(mpu->ih[0]);
|
4454 |
omap_inth_reset(mpu->ih[1]);
|
4455 |
omap_dma_reset(mpu->dma); |
4456 |
omap_mpu_timer_reset(mpu->timer[0]);
|
4457 |
omap_mpu_timer_reset(mpu->timer[1]);
|
4458 |
omap_mpu_timer_reset(mpu->timer[2]);
|
4459 |
omap_wd_timer_reset(mpu->wdt); |
4460 |
omap_os_timer_reset(mpu->os_timer); |
4461 |
omap_lcdc_reset(mpu->lcd); |
4462 |
omap_ulpd_pm_reset(mpu); |
4463 |
omap_pin_cfg_reset(mpu); |
4464 |
omap_mpui_reset(mpu); |
4465 |
omap_tipb_bridge_reset(mpu->private_tipb); |
4466 |
omap_tipb_bridge_reset(mpu->public_tipb); |
4467 |
omap_dpll_reset(&mpu->dpll[0]);
|
4468 |
omap_dpll_reset(&mpu->dpll[1]);
|
4469 |
omap_dpll_reset(&mpu->dpll[2]);
|
4470 |
omap_uart_reset(mpu->uart[0]);
|
4471 |
omap_uart_reset(mpu->uart[1]);
|
4472 |
omap_uart_reset(mpu->uart[2]);
|
4473 |
omap_mmc_reset(mpu->mmc); |
4474 |
omap_mpuio_reset(mpu->mpuio); |
4475 |
omap_gpio_reset(mpu->gpio); |
4476 |
omap_uwire_reset(mpu->microwire); |
4477 |
omap_pwl_reset(mpu); |
4478 |
omap_pwt_reset(mpu); |
4479 |
omap_i2c_reset(mpu->i2c); |
4480 |
omap_rtc_reset(mpu->rtc); |
4481 |
cpu_reset(mpu->env); |
4482 |
} |
4483 |
|
4484 |
static void omap_mpu_wakeup(void *opaque, int irq, int req) |
4485 |
{ |
4486 |
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
4487 |
|
4488 |
if (mpu->env->halted)
|
4489 |
cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
4490 |
} |
4491 |
|
4492 |
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
4493 |
DisplayState *ds, const char *core) |
4494 |
{ |
4495 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
4496 |
qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
4497 |
ram_addr_t imif_base, emiff_base; |
4498 |
|
4499 |
/* Core */
|
4500 |
s->mpu_model = omap310; |
4501 |
s->env = cpu_init(); |
4502 |
s->sdram_size = sdram_size; |
4503 |
s->sram_size = OMAP15XX_SRAM_SIZE; |
4504 |
|
4505 |
cpu_arm_set_model(s->env, core ?: "ti925t");
|
4506 |
|
4507 |
s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
4508 |
|
4509 |
/* Clocks */
|
4510 |
omap_clk_init(s); |
4511 |
|
4512 |
/* Memory-mapped stuff */
|
4513 |
cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
4514 |
(emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
4515 |
cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
4516 |
(imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
4517 |
|
4518 |
omap_clkm_init(0xfffece00, 0xe1008000, s); |
4519 |
|
4520 |
s->ih[0] = omap_inth_init(0xfffecb00, 0x100, |
4521 |
arm_pic_init_cpu(s->env), |
4522 |
omap_findclk(s, "arminth_ck"));
|
4523 |
s->ih[1] = omap_inth_init(0xfffe0000, 0x800, |
4524 |
&s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
|
4525 |
omap_findclk(s, "arminth_ck"));
|
4526 |
s->irq[0] = s->ih[0]->pins; |
4527 |
s->irq[1] = s->ih[1]->pins; |
4528 |
|
4529 |
s->dma = omap_dma_init(0xfffed800, s->irq[0], s, |
4530 |
omap_findclk(s, "dma_ck"));
|
4531 |
s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
4532 |
s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
4533 |
s->port[imif ].addr_valid = omap_validate_imif_addr; |
4534 |
s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
4535 |
s->port[local ].addr_valid = omap_validate_local_addr; |
4536 |
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
4537 |
|
4538 |
s->timer[0] = omap_mpu_timer_init(0xfffec500, |
4539 |
s->irq[0][OMAP_INT_TIMER1],
|
4540 |
omap_findclk(s, "mputim_ck"));
|
4541 |
s->timer[1] = omap_mpu_timer_init(0xfffec600, |
4542 |
s->irq[0][OMAP_INT_TIMER2],
|
4543 |
omap_findclk(s, "mputim_ck"));
|
4544 |
s->timer[2] = omap_mpu_timer_init(0xfffec700, |
4545 |
s->irq[0][OMAP_INT_TIMER3],
|
4546 |
omap_findclk(s, "mputim_ck"));
|
4547 |
|
4548 |
s->wdt = omap_wd_timer_init(0xfffec800,
|
4549 |
s->irq[0][OMAP_INT_WD_TIMER],
|
4550 |
omap_findclk(s, "armwdt_ck"));
|
4551 |
|
4552 |
s->os_timer = omap_os_timer_init(0xfffb9000,
|
4553 |
s->irq[1][OMAP_INT_OS_TIMER],
|
4554 |
omap_findclk(s, "clk32-kHz"));
|
4555 |
|
4556 |
s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
4557 |
&s->dma->lcd_ch, ds, imif_base, emiff_base, |
4558 |
omap_findclk(s, "lcd_ck"));
|
4559 |
|
4560 |
omap_ulpd_pm_init(0xfffe0800, s);
|
4561 |
omap_pin_cfg_init(0xfffe1000, s);
|
4562 |
omap_id_init(s); |
4563 |
|
4564 |
omap_mpui_init(0xfffec900, s);
|
4565 |
|
4566 |
s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
4567 |
s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
4568 |
omap_findclk(s, "tipb_ck"));
|
4569 |
s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
4570 |
s->irq[0][OMAP_INT_BRIDGE_PUB],
|
4571 |
omap_findclk(s, "tipb_ck"));
|
4572 |
|
4573 |
omap_tcmi_init(0xfffecc00, s);
|
4574 |
|
4575 |
s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
4576 |
omap_findclk(s, "uart1_ck"),
|
4577 |
serial_hds[0]);
|
4578 |
s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
4579 |
omap_findclk(s, "uart2_ck"),
|
4580 |
serial_hds[0] ? serial_hds[1] : 0); |
4581 |
s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3], |
4582 |
omap_findclk(s, "uart3_ck"),
|
4583 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
4584 |
|
4585 |
omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
4586 |
omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
4587 |
omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
4588 |
|
4589 |
s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN], |
4590 |
&s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
|
4591 |
|
4592 |
s->mpuio = omap_mpuio_init(0xfffb5000,
|
4593 |
s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
4594 |
s->wakeup, omap_findclk(s, "clk32-kHz"));
|
4595 |
|
4596 |
s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
4597 |
omap_findclk(s, "arm_gpio_ck"));
|
4598 |
|
4599 |
s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
4600 |
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
|
4601 |
|
4602 |
omap_pwl_init(0xfffb5800, s, omap_findclk(s, "clk32-kHz")); |
4603 |
omap_pwt_init(0xfffb6000, s, omap_findclk(s, "xtal_osc_12m")); |
4604 |
|
4605 |
s->i2c = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], |
4606 |
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
|
4607 |
|
4608 |
s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], |
4609 |
omap_findclk(s, "clk32-kHz"));
|
4610 |
qemu_register_reset(omap_mpu_reset, s); |
4611 |
|
4612 |
return s;
|
4613 |
} |