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/*
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* QEMU ESP/NCR53C9x emulation
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*
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* Copyright (c) 2005-2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h" |
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#include "scsi.h" |
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#include "esp.h" |
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/* debug ESP card */
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//#define DEBUG_ESP
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*/
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#ifdef DEBUG_ESP
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#define DPRINTF(fmt, ...) \
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do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) do {} while (0) |
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#endif
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#define ESP_ERROR(fmt, ...) \
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do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
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#define ESP_REGS 16 |
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#define TI_BUFSZ 16 |
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typedef struct ESPState ESPState; |
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struct ESPState {
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SysBusDevice busdev; |
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uint32_t it_shift; |
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qemu_irq irq; |
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uint8_t rregs[ESP_REGS]; |
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uint8_t wregs[ESP_REGS]; |
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int32_t ti_size; |
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uint32_t ti_rptr, ti_wptr; |
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uint8_t ti_buf[TI_BUFSZ]; |
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uint32_t sense; |
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uint32_t dma; |
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SCSIBus bus; |
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SCSIDevice *current_dev; |
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SCSIRequest *current_req; |
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uint8_t cmdbuf[TI_BUFSZ]; |
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uint32_t cmdlen; |
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uint32_t do_cmd; |
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left; |
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter; |
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uint8_t *async_buf; |
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uint32_t async_len; |
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ESPDMAMemoryReadWriteFunc dma_memory_read; |
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ESPDMAMemoryReadWriteFunc dma_memory_write; |
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void *dma_opaque;
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int dma_enabled;
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void (*dma_cb)(ESPState *s);
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}; |
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#define ESP_TCLO 0x0 |
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#define ESP_TCMID 0x1 |
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#define ESP_FIFO 0x2 |
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#define ESP_CMD 0x3 |
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#define ESP_RSTAT 0x4 |
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#define ESP_WBUSID 0x4 |
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#define ESP_RINTR 0x5 |
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#define ESP_WSEL 0x5 |
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#define ESP_RSEQ 0x6 |
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#define ESP_WSYNTP 0x6 |
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#define ESP_RFLAGS 0x7 |
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#define ESP_WSYNO 0x7 |
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#define ESP_CFG1 0x8 |
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#define ESP_RRES1 0x9 |
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#define ESP_WCCF 0x9 |
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#define ESP_RRES2 0xa |
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#define ESP_WTEST 0xa |
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#define ESP_CFG2 0xb |
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#define ESP_CFG3 0xc |
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#define ESP_RES3 0xd |
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#define ESP_TCHI 0xe |
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#define ESP_RES4 0xf |
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#define CMD_DMA 0x80 |
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#define CMD_CMD 0x7f |
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#define CMD_NOP 0x00 |
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#define CMD_FLUSH 0x01 |
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#define CMD_RESET 0x02 |
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#define CMD_BUSRESET 0x03 |
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#define CMD_TI 0x10 |
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#define CMD_ICCS 0x11 |
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#define CMD_MSGACC 0x12 |
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#define CMD_PAD 0x18 |
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#define CMD_SATN 0x1a |
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#define CMD_SEL 0x41 |
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#define CMD_SELATN 0x42 |
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#define CMD_SELATNS 0x43 |
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#define CMD_ENSEL 0x44 |
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#define STAT_DO 0x00 |
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#define STAT_DI 0x01 |
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#define STAT_CD 0x02 |
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#define STAT_ST 0x03 |
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#define STAT_MO 0x06 |
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#define STAT_MI 0x07 |
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#define STAT_PIO_MASK 0x06 |
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#define STAT_TC 0x10 |
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#define STAT_PE 0x20 |
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#define STAT_GE 0x40 |
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#define STAT_INT 0x80 |
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#define BUSID_DID 0x07 |
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#define INTR_FC 0x08 |
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#define INTR_BS 0x10 |
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#define INTR_DC 0x20 |
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#define INTR_RST 0x80 |
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#define SEQ_0 0x0 |
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#define SEQ_CD 0x4 |
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#define CFG1_RESREPT 0x40 |
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#define TCHI_FAS100A 0x4 |
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static void esp_raise_irq(ESPState *s) |
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{ |
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if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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s->rregs[ESP_RSTAT] |= STAT_INT; |
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qemu_irq_raise(s->irq); |
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DPRINTF("Raise IRQ\n");
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} |
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} |
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static void esp_lower_irq(ESPState *s) |
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{ |
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if (s->rregs[ESP_RSTAT] & STAT_INT) {
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s->rregs[ESP_RSTAT] &= ~STAT_INT; |
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qemu_irq_lower(s->irq); |
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DPRINTF("Lower IRQ\n");
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} |
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} |
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static void esp_dma_enable(void *opaque, int irq, int level) |
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{ |
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DeviceState *d = opaque; |
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ESPState *s = container_of(d, ESPState, busdev.qdev); |
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if (level) {
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s->dma_enabled = 1;
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DPRINTF("Raise enable\n");
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if (s->dma_cb) {
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s->dma_cb(s); |
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s->dma_cb = NULL;
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} |
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} else {
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DPRINTF("Lower enable\n");
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s->dma_enabled = 0;
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} |
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} |
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static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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{ |
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uint32_t dmalen; |
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int target;
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target = s->wregs[ESP_WBUSID] & BUSID_DID; |
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if (s->dma) {
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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s->dma_memory_read(s->dma_opaque, buf, dmalen); |
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} else {
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dmalen = s->ti_size; |
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memcpy(buf, s->ti_buf, dmalen); |
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buf[0] = 0; |
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} |
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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if (s->current_dev) {
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/* Started a new command before the old one finished. Cancel it. */
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s->current_dev->info->cancel_io(s->current_req); |
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s->async_len = 0;
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} |
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if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) {
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// No such drive
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s->rregs[ESP_RSTAT] = 0;
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s->rregs[ESP_RINTR] = INTR_DC; |
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s->rregs[ESP_RSEQ] = SEQ_0; |
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esp_raise_irq(s); |
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return 0; |
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} |
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s->current_dev = s->bus.devs[target]; |
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return dmalen;
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} |
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static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
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{ |
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int32_t datalen; |
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int lun;
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DPRINTF("do_busid_cmd: busid 0x%x\n", busid);
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lun = busid & 7;
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s->current_req = s->current_dev->info->alloc_req(s->current_dev, 0, lun);
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datalen = s->current_dev->info->send_command(s->current_req, buf); |
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s->ti_size = datalen; |
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if (datalen != 0) { |
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s->rregs[ESP_RSTAT] = STAT_TC; |
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) { |
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s->rregs[ESP_RSTAT] |= STAT_DI; |
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s->current_dev->info->read_data(s->current_req); |
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} else {
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s->rregs[ESP_RSTAT] |= STAT_DO; |
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s->current_dev->info->write_data(s->current_req); |
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} |
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} |
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
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s->rregs[ESP_RSEQ] = SEQ_CD; |
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esp_raise_irq(s); |
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} |
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static void do_cmd(ESPState *s, uint8_t *buf) |
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{ |
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uint8_t busid = buf[0];
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do_busid_cmd(s, &buf[1], busid);
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} |
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static void handle_satn(ESPState *s) |
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{ |
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uint8_t buf[32];
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int len;
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if (!s->dma_enabled) {
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s->dma_cb = handle_satn; |
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return;
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} |
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len = get_cmd(s, buf); |
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if (len)
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do_cmd(s, buf); |
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} |
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static void handle_s_without_atn(ESPState *s) |
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{ |
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uint8_t buf[32];
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int len;
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if (!s->dma_enabled) {
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s->dma_cb = handle_s_without_atn; |
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return;
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} |
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len = get_cmd(s, buf); |
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if (len) {
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do_busid_cmd(s, buf, 0);
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} |
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} |
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static void handle_satn_stop(ESPState *s) |
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{ |
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if (!s->dma_enabled) {
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s->dma_cb = handle_satn_stop; |
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return;
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} |
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s->cmdlen = get_cmd(s, s->cmdbuf); |
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
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s->rregs[ESP_RSEQ] = SEQ_CD; |
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esp_raise_irq(s); |
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} |
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} |
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static void write_response(ESPState *s) |
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{ |
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DPRINTF("Transfer status (sense=%d)\n", s->sense);
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s->ti_buf[0] = s->sense;
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s->ti_buf[1] = 0; |
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if (s->dma) {
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s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
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s->rregs[ESP_RSEQ] = SEQ_CD; |
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[ESP_RFLAGS] = 2;
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} |
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esp_raise_irq(s); |
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} |
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static void esp_dma_done(ESPState *s) |
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{ |
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s->rregs[ESP_RSTAT] |= STAT_TC; |
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s->rregs[ESP_RINTR] = INTR_BS; |
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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s->rregs[ESP_TCLO] = 0;
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s->rregs[ESP_TCMID] = 0;
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esp_raise_irq(s); |
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} |
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static void esp_do_dma(ESPState *s) |
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{ |
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uint32_t len; |
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int to_device;
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to_device = (s->ti_size < 0);
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len = s->dma_left; |
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if (s->do_cmd) {
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DPRINTF("command len %d + %d\n", s->cmdlen, len);
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s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
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s->ti_size = 0;
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s->cmdlen = 0;
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s->do_cmd = 0;
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do_cmd(s, s->cmdbuf); |
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return;
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} |
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if (s->async_len == 0) { |
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/* Defer until data is available. */
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return;
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} |
359 |
if (len > s->async_len) {
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len = s->async_len; |
361 |
} |
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if (to_device) {
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s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
364 |
} else {
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s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
366 |
} |
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s->dma_left -= len; |
368 |
s->async_buf += len; |
369 |
s->async_len -= len; |
370 |
if (to_device)
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s->ti_size += len; |
372 |
else
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s->ti_size -= len; |
374 |
if (s->async_len == 0) { |
375 |
if (to_device) {
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// ti_size is negative
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s->current_dev->info->write_data(s->current_req); |
378 |
} else {
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s->current_dev->info->read_data(s->current_req); |
380 |
/* If there is still data to be read from the device then
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complete the DMA operation immediately. Otherwise defer
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until the scsi layer has completed. */
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if (s->dma_left == 0 && s->ti_size > 0) { |
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esp_dma_done(s); |
385 |
} |
386 |
} |
387 |
} else {
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/* Partially filled a scsi buffer. Complete immediately. */
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esp_dma_done(s); |
390 |
} |
391 |
} |
392 |
|
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static void esp_command_complete(SCSIRequest *req, int reason, uint32_t arg) |
394 |
{ |
395 |
ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent); |
396 |
|
397 |
if (reason == SCSI_REASON_DONE) {
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DPRINTF("SCSI Command complete\n");
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if (s->ti_size != 0) |
400 |
DPRINTF("SCSI command completed unexpectedly\n");
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s->ti_size = 0;
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s->dma_left = 0;
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s->async_len = 0;
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if (arg)
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DPRINTF("Command failed\n");
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s->sense = arg; |
407 |
s->rregs[ESP_RSTAT] = STAT_ST; |
408 |
esp_dma_done(s); |
409 |
if (s->current_req) {
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410 |
scsi_req_unref(s->current_req); |
411 |
s->current_req = NULL;
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s->current_dev = NULL;
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} |
414 |
} else {
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DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
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s->async_len = arg; |
417 |
s->async_buf = s->current_dev->info->get_buf(req); |
418 |
if (s->dma_left) {
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esp_do_dma(s); |
420 |
} else if (s->dma_counter != 0 && s->ti_size <= 0) { |
421 |
/* If this was the last part of a DMA transfer then the
|
422 |
completion interrupt is deferred to here. */
|
423 |
esp_dma_done(s); |
424 |
} |
425 |
} |
426 |
} |
427 |
|
428 |
static void handle_ti(ESPState *s) |
429 |
{ |
430 |
uint32_t dmalen, minlen; |
431 |
|
432 |
dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
433 |
if (dmalen==0) { |
434 |
dmalen=0x10000;
|
435 |
} |
436 |
s->dma_counter = dmalen; |
437 |
|
438 |
if (s->do_cmd)
|
439 |
minlen = (dmalen < 32) ? dmalen : 32; |
440 |
else if (s->ti_size < 0) |
441 |
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
442 |
else
|
443 |
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
444 |
DPRINTF("Transfer Information len %d\n", minlen);
|
445 |
if (s->dma) {
|
446 |
s->dma_left = minlen; |
447 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
448 |
esp_do_dma(s); |
449 |
} else if (s->do_cmd) { |
450 |
DPRINTF("command len %d\n", s->cmdlen);
|
451 |
s->ti_size = 0;
|
452 |
s->cmdlen = 0;
|
453 |
s->do_cmd = 0;
|
454 |
do_cmd(s, s->cmdbuf); |
455 |
return;
|
456 |
} |
457 |
} |
458 |
|
459 |
static void esp_hard_reset(DeviceState *d) |
460 |
{ |
461 |
ESPState *s = container_of(d, ESPState, busdev.qdev); |
462 |
|
463 |
memset(s->rregs, 0, ESP_REGS);
|
464 |
memset(s->wregs, 0, ESP_REGS);
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s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
466 |
s->ti_size = 0;
|
467 |
s->ti_rptr = 0;
|
468 |
s->ti_wptr = 0;
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469 |
s->dma = 0;
|
470 |
s->do_cmd = 0;
|
471 |
s->dma_cb = NULL;
|
472 |
|
473 |
s->rregs[ESP_CFG1] = 7;
|
474 |
} |
475 |
|
476 |
static void esp_soft_reset(DeviceState *d) |
477 |
{ |
478 |
ESPState *s = container_of(d, ESPState, busdev.qdev); |
479 |
|
480 |
qemu_irq_lower(s->irq); |
481 |
esp_hard_reset(d); |
482 |
} |
483 |
|
484 |
static void parent_esp_reset(void *opaque, int irq, int level) |
485 |
{ |
486 |
if (level) {
|
487 |
esp_soft_reset(opaque); |
488 |
} |
489 |
} |
490 |
|
491 |
static void esp_gpio_demux(void *opaque, int irq, int level) |
492 |
{ |
493 |
switch (irq) {
|
494 |
case 0: |
495 |
parent_esp_reset(opaque, irq, level); |
496 |
break;
|
497 |
case 1: |
498 |
esp_dma_enable(opaque, irq, level); |
499 |
break;
|
500 |
} |
501 |
} |
502 |
|
503 |
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
504 |
{ |
505 |
ESPState *s = opaque; |
506 |
uint32_t saddr, old_val; |
507 |
|
508 |
saddr = addr >> s->it_shift; |
509 |
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
510 |
switch (saddr) {
|
511 |
case ESP_FIFO:
|
512 |
if (s->ti_size > 0) { |
513 |
s->ti_size--; |
514 |
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
515 |
/* Data out. */
|
516 |
ESP_ERROR("PIO data read not implemented\n");
|
517 |
s->rregs[ESP_FIFO] = 0;
|
518 |
} else {
|
519 |
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
520 |
} |
521 |
esp_raise_irq(s); |
522 |
} |
523 |
if (s->ti_size == 0) { |
524 |
s->ti_rptr = 0;
|
525 |
s->ti_wptr = 0;
|
526 |
} |
527 |
break;
|
528 |
case ESP_RINTR:
|
529 |
/* Clear sequence step, interrupt register and all status bits
|
530 |
except TC */
|
531 |
old_val = s->rregs[ESP_RINTR]; |
532 |
s->rregs[ESP_RINTR] = 0;
|
533 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
534 |
s->rregs[ESP_RSEQ] = SEQ_CD; |
535 |
esp_lower_irq(s); |
536 |
|
537 |
return old_val;
|
538 |
default:
|
539 |
break;
|
540 |
} |
541 |
return s->rregs[saddr];
|
542 |
} |
543 |
|
544 |
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
545 |
{ |
546 |
ESPState *s = opaque; |
547 |
uint32_t saddr; |
548 |
|
549 |
saddr = addr >> s->it_shift; |
550 |
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
551 |
val); |
552 |
switch (saddr) {
|
553 |
case ESP_TCLO:
|
554 |
case ESP_TCMID:
|
555 |
s->rregs[ESP_RSTAT] &= ~STAT_TC; |
556 |
break;
|
557 |
case ESP_FIFO:
|
558 |
if (s->do_cmd) {
|
559 |
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
560 |
} else if (s->ti_size == TI_BUFSZ - 1) { |
561 |
ESP_ERROR("fifo overrun\n");
|
562 |
} else {
|
563 |
s->ti_size++; |
564 |
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
565 |
} |
566 |
break;
|
567 |
case ESP_CMD:
|
568 |
s->rregs[saddr] = val; |
569 |
if (val & CMD_DMA) {
|
570 |
s->dma = 1;
|
571 |
/* Reload DMA counter. */
|
572 |
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
573 |
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
574 |
} else {
|
575 |
s->dma = 0;
|
576 |
} |
577 |
switch(val & CMD_CMD) {
|
578 |
case CMD_NOP:
|
579 |
DPRINTF("NOP (%2.2x)\n", val);
|
580 |
break;
|
581 |
case CMD_FLUSH:
|
582 |
DPRINTF("Flush FIFO (%2.2x)\n", val);
|
583 |
//s->ti_size = 0;
|
584 |
s->rregs[ESP_RINTR] = INTR_FC; |
585 |
s->rregs[ESP_RSEQ] = 0;
|
586 |
s->rregs[ESP_RFLAGS] = 0;
|
587 |
break;
|
588 |
case CMD_RESET:
|
589 |
DPRINTF("Chip reset (%2.2x)\n", val);
|
590 |
esp_soft_reset(&s->busdev.qdev); |
591 |
break;
|
592 |
case CMD_BUSRESET:
|
593 |
DPRINTF("Bus reset (%2.2x)\n", val);
|
594 |
s->rregs[ESP_RINTR] = INTR_RST; |
595 |
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
596 |
esp_raise_irq(s); |
597 |
} |
598 |
break;
|
599 |
case CMD_TI:
|
600 |
handle_ti(s); |
601 |
break;
|
602 |
case CMD_ICCS:
|
603 |
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
604 |
write_response(s); |
605 |
s->rregs[ESP_RINTR] = INTR_FC; |
606 |
s->rregs[ESP_RSTAT] |= STAT_MI; |
607 |
break;
|
608 |
case CMD_MSGACC:
|
609 |
DPRINTF("Message Accepted (%2.2x)\n", val);
|
610 |
s->rregs[ESP_RINTR] = INTR_DC; |
611 |
s->rregs[ESP_RSEQ] = 0;
|
612 |
s->rregs[ESP_RFLAGS] = 0;
|
613 |
esp_raise_irq(s); |
614 |
break;
|
615 |
case CMD_PAD:
|
616 |
DPRINTF("Transfer padding (%2.2x)\n", val);
|
617 |
s->rregs[ESP_RSTAT] = STAT_TC; |
618 |
s->rregs[ESP_RINTR] = INTR_FC; |
619 |
s->rregs[ESP_RSEQ] = 0;
|
620 |
break;
|
621 |
case CMD_SATN:
|
622 |
DPRINTF("Set ATN (%2.2x)\n", val);
|
623 |
break;
|
624 |
case CMD_SEL:
|
625 |
DPRINTF("Select without ATN (%2.2x)\n", val);
|
626 |
handle_s_without_atn(s); |
627 |
break;
|
628 |
case CMD_SELATN:
|
629 |
DPRINTF("Select with ATN (%2.2x)\n", val);
|
630 |
handle_satn(s); |
631 |
break;
|
632 |
case CMD_SELATNS:
|
633 |
DPRINTF("Select with ATN & stop (%2.2x)\n", val);
|
634 |
handle_satn_stop(s); |
635 |
break;
|
636 |
case CMD_ENSEL:
|
637 |
DPRINTF("Enable selection (%2.2x)\n", val);
|
638 |
s->rregs[ESP_RINTR] = 0;
|
639 |
break;
|
640 |
default:
|
641 |
ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
|
642 |
break;
|
643 |
} |
644 |
break;
|
645 |
case ESP_WBUSID ... ESP_WSYNO:
|
646 |
break;
|
647 |
case ESP_CFG1:
|
648 |
s->rregs[saddr] = val; |
649 |
break;
|
650 |
case ESP_WCCF ... ESP_WTEST:
|
651 |
break;
|
652 |
case ESP_CFG2 ... ESP_RES4:
|
653 |
s->rregs[saddr] = val; |
654 |
break;
|
655 |
default:
|
656 |
ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
|
657 |
return;
|
658 |
} |
659 |
s->wregs[saddr] = val; |
660 |
} |
661 |
|
662 |
static CPUReadMemoryFunc * const esp_mem_read[3] = { |
663 |
esp_mem_readb, |
664 |
NULL,
|
665 |
NULL,
|
666 |
}; |
667 |
|
668 |
static CPUWriteMemoryFunc * const esp_mem_write[3] = { |
669 |
esp_mem_writeb, |
670 |
NULL,
|
671 |
esp_mem_writeb, |
672 |
}; |
673 |
|
674 |
static const VMStateDescription vmstate_esp = { |
675 |
.name ="esp",
|
676 |
.version_id = 3,
|
677 |
.minimum_version_id = 3,
|
678 |
.minimum_version_id_old = 3,
|
679 |
.fields = (VMStateField []) { |
680 |
VMSTATE_BUFFER(rregs, ESPState), |
681 |
VMSTATE_BUFFER(wregs, ESPState), |
682 |
VMSTATE_INT32(ti_size, ESPState), |
683 |
VMSTATE_UINT32(ti_rptr, ESPState), |
684 |
VMSTATE_UINT32(ti_wptr, ESPState), |
685 |
VMSTATE_BUFFER(ti_buf, ESPState), |
686 |
VMSTATE_UINT32(sense, ESPState), |
687 |
VMSTATE_UINT32(dma, ESPState), |
688 |
VMSTATE_BUFFER(cmdbuf, ESPState), |
689 |
VMSTATE_UINT32(cmdlen, ESPState), |
690 |
VMSTATE_UINT32(do_cmd, ESPState), |
691 |
VMSTATE_UINT32(dma_left, ESPState), |
692 |
VMSTATE_END_OF_LIST() |
693 |
} |
694 |
}; |
695 |
|
696 |
void esp_init(target_phys_addr_t espaddr, int it_shift, |
697 |
ESPDMAMemoryReadWriteFunc dma_memory_read, |
698 |
ESPDMAMemoryReadWriteFunc dma_memory_write, |
699 |
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
|
700 |
qemu_irq *dma_enable) |
701 |
{ |
702 |
DeviceState *dev; |
703 |
SysBusDevice *s; |
704 |
ESPState *esp; |
705 |
|
706 |
dev = qdev_create(NULL, "esp"); |
707 |
esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
708 |
esp->dma_memory_read = dma_memory_read; |
709 |
esp->dma_memory_write = dma_memory_write; |
710 |
esp->dma_opaque = dma_opaque; |
711 |
esp->it_shift = it_shift; |
712 |
/* XXX for now until rc4030 has been changed to use DMA enable signal */
|
713 |
esp->dma_enabled = 1;
|
714 |
qdev_init_nofail(dev); |
715 |
s = sysbus_from_qdev(dev); |
716 |
sysbus_connect_irq(s, 0, irq);
|
717 |
sysbus_mmio_map(s, 0, espaddr);
|
718 |
*reset = qdev_get_gpio_in(dev, 0);
|
719 |
*dma_enable = qdev_get_gpio_in(dev, 1);
|
720 |
} |
721 |
|
722 |
static const struct SCSIBusOps esp_scsi_ops = { |
723 |
.complete = esp_command_complete |
724 |
}; |
725 |
|
726 |
static int esp_init1(SysBusDevice *dev) |
727 |
{ |
728 |
ESPState *s = FROM_SYSBUS(ESPState, dev); |
729 |
int esp_io_memory;
|
730 |
|
731 |
sysbus_init_irq(dev, &s->irq); |
732 |
assert(s->it_shift != -1);
|
733 |
|
734 |
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s, |
735 |
DEVICE_NATIVE_ENDIAN); |
736 |
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
737 |
|
738 |
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
|
739 |
|
740 |
scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, &esp_scsi_ops);
|
741 |
return scsi_bus_legacy_handle_cmdline(&s->bus);
|
742 |
} |
743 |
|
744 |
static SysBusDeviceInfo esp_info = {
|
745 |
.init = esp_init1, |
746 |
.qdev.name = "esp",
|
747 |
.qdev.size = sizeof(ESPState),
|
748 |
.qdev.vmsd = &vmstate_esp, |
749 |
.qdev.reset = esp_hard_reset, |
750 |
.qdev.props = (Property[]) { |
751 |
{.name = NULL}
|
752 |
} |
753 |
}; |
754 |
|
755 |
static void esp_register_devices(void) |
756 |
{ |
757 |
sysbus_register_withprop(&esp_info); |
758 |
} |
759 |
|
760 |
device_init(esp_register_devices) |