root / hw / usb-uhci.c @ 5d808245
History | View | Annotate | Download (27.9 kB)
1 |
/*
|
---|---|
2 |
* USB UHCI controller emulation
|
3 |
*
|
4 |
* Copyright (c) 2005 Fabrice Bellard
|
5 |
*
|
6 |
* Copyright (c) 2008 Max Krasnyansky
|
7 |
* Magor rewrite of the UHCI data structures parser and frame processor
|
8 |
* Support for fully async operation and multiple outstanding transactions
|
9 |
*
|
10 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
11 |
* of this software and associated documentation files (the "Software"), to deal
|
12 |
* in the Software without restriction, including without limitation the rights
|
13 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
14 |
* copies of the Software, and to permit persons to whom the Software is
|
15 |
* furnished to do so, subject to the following conditions:
|
16 |
*
|
17 |
* The above copyright notice and this permission notice shall be included in
|
18 |
* all copies or substantial portions of the Software.
|
19 |
*
|
20 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
21 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
22 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
23 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
24 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
25 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
26 |
* THE SOFTWARE.
|
27 |
*/
|
28 |
#include "hw.h" |
29 |
#include "usb.h" |
30 |
#include "pci.h" |
31 |
#include "qemu-timer.h" |
32 |
|
33 |
//#define DEBUG
|
34 |
//#define DEBUG_DUMP_DATA
|
35 |
|
36 |
#define UHCI_CMD_FGR (1 << 4) |
37 |
#define UHCI_CMD_EGSM (1 << 3) |
38 |
#define UHCI_CMD_GRESET (1 << 2) |
39 |
#define UHCI_CMD_HCRESET (1 << 1) |
40 |
#define UHCI_CMD_RS (1 << 0) |
41 |
|
42 |
#define UHCI_STS_HCHALTED (1 << 5) |
43 |
#define UHCI_STS_HCPERR (1 << 4) |
44 |
#define UHCI_STS_HSERR (1 << 3) |
45 |
#define UHCI_STS_RD (1 << 2) |
46 |
#define UHCI_STS_USBERR (1 << 1) |
47 |
#define UHCI_STS_USBINT (1 << 0) |
48 |
|
49 |
#define TD_CTRL_SPD (1 << 29) |
50 |
#define TD_CTRL_ERROR_SHIFT 27 |
51 |
#define TD_CTRL_IOS (1 << 25) |
52 |
#define TD_CTRL_IOC (1 << 24) |
53 |
#define TD_CTRL_ACTIVE (1 << 23) |
54 |
#define TD_CTRL_STALL (1 << 22) |
55 |
#define TD_CTRL_BABBLE (1 << 20) |
56 |
#define TD_CTRL_NAK (1 << 19) |
57 |
#define TD_CTRL_TIMEOUT (1 << 18) |
58 |
|
59 |
#define UHCI_PORT_RESET (1 << 9) |
60 |
#define UHCI_PORT_LSDA (1 << 8) |
61 |
#define UHCI_PORT_ENC (1 << 3) |
62 |
#define UHCI_PORT_EN (1 << 2) |
63 |
#define UHCI_PORT_CSC (1 << 1) |
64 |
#define UHCI_PORT_CCS (1 << 0) |
65 |
|
66 |
#define FRAME_TIMER_FREQ 1000 |
67 |
|
68 |
#define FRAME_MAX_LOOPS 100 |
69 |
|
70 |
#define NB_PORTS 2 |
71 |
|
72 |
#ifdef DEBUG
|
73 |
#define dprintf printf
|
74 |
|
75 |
const char *pid2str(int pid) |
76 |
{ |
77 |
switch (pid) {
|
78 |
case USB_TOKEN_SETUP: return "SETUP"; |
79 |
case USB_TOKEN_IN: return "IN"; |
80 |
case USB_TOKEN_OUT: return "OUT"; |
81 |
} |
82 |
return "?"; |
83 |
} |
84 |
|
85 |
#else
|
86 |
#define dprintf(...)
|
87 |
#endif
|
88 |
|
89 |
#ifdef DEBUG_DUMP_DATA
|
90 |
static void dump_data(const uint8_t *data, int len) |
91 |
{ |
92 |
int i;
|
93 |
|
94 |
printf("uhci: data: ");
|
95 |
for(i = 0; i < len; i++) |
96 |
printf(" %02x", data[i]);
|
97 |
printf("\n");
|
98 |
} |
99 |
#else
|
100 |
static void dump_data(const uint8_t *data, int len) {} |
101 |
#endif
|
102 |
|
103 |
/*
|
104 |
* Pending async transaction.
|
105 |
* 'packet' must be the first field because completion
|
106 |
* handler does "(UHCIAsync *) pkt" cast.
|
107 |
*/
|
108 |
typedef struct UHCIAsync { |
109 |
USBPacket packet; |
110 |
struct UHCIAsync *next;
|
111 |
uint32_t td; |
112 |
uint32_t token; |
113 |
int8_t valid; |
114 |
uint8_t done; |
115 |
uint8_t buffer[2048];
|
116 |
} UHCIAsync; |
117 |
|
118 |
typedef struct UHCIPort { |
119 |
USBPort port; |
120 |
uint16_t ctrl; |
121 |
} UHCIPort; |
122 |
|
123 |
typedef struct UHCIState { |
124 |
PCIDevice dev; |
125 |
uint16_t cmd; /* cmd register */
|
126 |
uint16_t status; |
127 |
uint16_t intr; /* interrupt enable register */
|
128 |
uint16_t frnum; /* frame number */
|
129 |
uint32_t fl_base_addr; /* frame list base address */
|
130 |
uint8_t sof_timing; |
131 |
uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
|
132 |
QEMUTimer *frame_timer; |
133 |
UHCIPort ports[NB_PORTS]; |
134 |
|
135 |
/* Interrupts that should be raised at the end of the current frame. */
|
136 |
uint32_t pending_int_mask; |
137 |
|
138 |
/* Active packets */
|
139 |
UHCIAsync *async_pending; |
140 |
UHCIAsync *async_pool; |
141 |
} UHCIState; |
142 |
|
143 |
typedef struct UHCI_TD { |
144 |
uint32_t link; |
145 |
uint32_t ctrl; /* see TD_CTRL_xxx */
|
146 |
uint32_t token; |
147 |
uint32_t buffer; |
148 |
} UHCI_TD; |
149 |
|
150 |
typedef struct UHCI_QH { |
151 |
uint32_t link; |
152 |
uint32_t el_link; |
153 |
} UHCI_QH; |
154 |
|
155 |
static UHCIAsync *uhci_async_alloc(UHCIState *s)
|
156 |
{ |
157 |
UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync));
|
158 |
if (async) {
|
159 |
memset(&async->packet, 0, sizeof(async->packet)); |
160 |
async->valid = 0;
|
161 |
async->td = 0;
|
162 |
async->token = 0;
|
163 |
async->done = 0;
|
164 |
async->next = NULL;
|
165 |
} |
166 |
|
167 |
return async;
|
168 |
} |
169 |
|
170 |
static void uhci_async_free(UHCIState *s, UHCIAsync *async) |
171 |
{ |
172 |
qemu_free(async); |
173 |
} |
174 |
|
175 |
static void uhci_async_link(UHCIState *s, UHCIAsync *async) |
176 |
{ |
177 |
async->next = s->async_pending; |
178 |
s->async_pending = async; |
179 |
} |
180 |
|
181 |
static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) |
182 |
{ |
183 |
UHCIAsync *curr = s->async_pending; |
184 |
UHCIAsync **prev = &s->async_pending; |
185 |
|
186 |
while (curr) {
|
187 |
if (curr == async) {
|
188 |
*prev = curr->next; |
189 |
return;
|
190 |
} |
191 |
|
192 |
prev = &curr->next; |
193 |
curr = curr->next; |
194 |
} |
195 |
} |
196 |
|
197 |
static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) |
198 |
{ |
199 |
dprintf("uhci: cancel td 0x%x token 0x%x done %u\n",
|
200 |
async->td, async->token, async->done); |
201 |
|
202 |
if (!async->done)
|
203 |
usb_cancel_packet(&async->packet); |
204 |
uhci_async_free(s, async); |
205 |
} |
206 |
|
207 |
/*
|
208 |
* Mark all outstanding async packets as invalid.
|
209 |
* This is used for canceling them when TDs are removed by the HCD.
|
210 |
*/
|
211 |
static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
|
212 |
{ |
213 |
UHCIAsync *async = s->async_pending; |
214 |
|
215 |
while (async) {
|
216 |
async->valid--; |
217 |
async = async->next; |
218 |
} |
219 |
return NULL; |
220 |
} |
221 |
|
222 |
/*
|
223 |
* Cancel async packets that are no longer valid
|
224 |
*/
|
225 |
static void uhci_async_validate_end(UHCIState *s) |
226 |
{ |
227 |
UHCIAsync *curr = s->async_pending; |
228 |
UHCIAsync **prev = &s->async_pending; |
229 |
UHCIAsync *next; |
230 |
|
231 |
while (curr) {
|
232 |
if (curr->valid > 0) { |
233 |
prev = &curr->next; |
234 |
curr = curr->next; |
235 |
continue;
|
236 |
} |
237 |
|
238 |
next = curr->next; |
239 |
|
240 |
/* Unlink */
|
241 |
*prev = next; |
242 |
|
243 |
uhci_async_cancel(s, curr); |
244 |
|
245 |
curr = next; |
246 |
} |
247 |
} |
248 |
|
249 |
static void uhci_async_cancel_all(UHCIState *s) |
250 |
{ |
251 |
UHCIAsync *curr = s->async_pending; |
252 |
UHCIAsync *next; |
253 |
|
254 |
while (curr) {
|
255 |
next = curr->next; |
256 |
|
257 |
uhci_async_cancel(s, curr); |
258 |
|
259 |
curr = next; |
260 |
} |
261 |
|
262 |
s->async_pending = NULL;
|
263 |
} |
264 |
|
265 |
static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
|
266 |
{ |
267 |
UHCIAsync *async = s->async_pending; |
268 |
|
269 |
while (async) {
|
270 |
if (async->td == addr) {
|
271 |
if (async->token == token)
|
272 |
return async;
|
273 |
|
274 |
/*
|
275 |
* TD was reused for a different transfer.
|
276 |
* Invalidate the original one asap.
|
277 |
*/
|
278 |
if (async->valid > 0) { |
279 |
async->valid = 0;
|
280 |
dprintf("husb: bad reuse. td 0x%x\n", async->td);
|
281 |
} |
282 |
} |
283 |
|
284 |
async = async->next; |
285 |
} |
286 |
return NULL; |
287 |
} |
288 |
|
289 |
static void uhci_attach(USBPort *port1, USBDevice *dev); |
290 |
|
291 |
static void uhci_update_irq(UHCIState *s) |
292 |
{ |
293 |
int level;
|
294 |
if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
295 |
((s->status2 & 2) && (s->intr & (1 << 3))) || |
296 |
((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
297 |
((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
298 |
(s->status & UHCI_STS_HSERR) || |
299 |
(s->status & UHCI_STS_HCPERR)) { |
300 |
level = 1;
|
301 |
} else {
|
302 |
level = 0;
|
303 |
} |
304 |
qemu_set_irq(s->dev.irq[3], level);
|
305 |
} |
306 |
|
307 |
static void uhci_reset(UHCIState *s) |
308 |
{ |
309 |
uint8_t *pci_conf; |
310 |
int i;
|
311 |
UHCIPort *port; |
312 |
|
313 |
dprintf("uhci: full reset\n");
|
314 |
|
315 |
pci_conf = s->dev.config; |
316 |
|
317 |
pci_conf[0x6a] = 0x01; /* usb clock */ |
318 |
pci_conf[0x6b] = 0x00; |
319 |
s->cmd = 0;
|
320 |
s->status = 0;
|
321 |
s->status2 = 0;
|
322 |
s->intr = 0;
|
323 |
s->fl_base_addr = 0;
|
324 |
s->sof_timing = 64;
|
325 |
|
326 |
for(i = 0; i < NB_PORTS; i++) { |
327 |
port = &s->ports[i]; |
328 |
port->ctrl = 0x0080;
|
329 |
if (port->port.dev)
|
330 |
uhci_attach(&port->port, port->port.dev); |
331 |
} |
332 |
|
333 |
uhci_async_cancel_all(s); |
334 |
} |
335 |
|
336 |
static void uhci_save(QEMUFile *f, void *opaque) |
337 |
{ |
338 |
UHCIState *s = opaque; |
339 |
uint8_t num_ports = NB_PORTS; |
340 |
int i;
|
341 |
|
342 |
uhci_async_cancel_all(s); |
343 |
|
344 |
pci_device_save(&s->dev, f); |
345 |
|
346 |
qemu_put_8s(f, &num_ports); |
347 |
for (i = 0; i < num_ports; ++i) |
348 |
qemu_put_be16s(f, &s->ports[i].ctrl); |
349 |
qemu_put_be16s(f, &s->cmd); |
350 |
qemu_put_be16s(f, &s->status); |
351 |
qemu_put_be16s(f, &s->intr); |
352 |
qemu_put_be16s(f, &s->frnum); |
353 |
qemu_put_be32s(f, &s->fl_base_addr); |
354 |
qemu_put_8s(f, &s->sof_timing); |
355 |
qemu_put_8s(f, &s->status2); |
356 |
qemu_put_timer(f, s->frame_timer); |
357 |
} |
358 |
|
359 |
static int uhci_load(QEMUFile *f, void *opaque, int version_id) |
360 |
{ |
361 |
UHCIState *s = opaque; |
362 |
uint8_t num_ports; |
363 |
int i, ret;
|
364 |
|
365 |
if (version_id > 1) |
366 |
return -EINVAL;
|
367 |
|
368 |
ret = pci_device_load(&s->dev, f); |
369 |
if (ret < 0) |
370 |
return ret;
|
371 |
|
372 |
qemu_get_8s(f, &num_ports); |
373 |
if (num_ports != NB_PORTS)
|
374 |
return -EINVAL;
|
375 |
|
376 |
for (i = 0; i < num_ports; ++i) |
377 |
qemu_get_be16s(f, &s->ports[i].ctrl); |
378 |
qemu_get_be16s(f, &s->cmd); |
379 |
qemu_get_be16s(f, &s->status); |
380 |
qemu_get_be16s(f, &s->intr); |
381 |
qemu_get_be16s(f, &s->frnum); |
382 |
qemu_get_be32s(f, &s->fl_base_addr); |
383 |
qemu_get_8s(f, &s->sof_timing); |
384 |
qemu_get_8s(f, &s->status2); |
385 |
qemu_get_timer(f, s->frame_timer); |
386 |
|
387 |
return 0; |
388 |
} |
389 |
|
390 |
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
391 |
{ |
392 |
UHCIState *s = opaque; |
393 |
|
394 |
addr &= 0x1f;
|
395 |
switch(addr) {
|
396 |
case 0x0c: |
397 |
s->sof_timing = val; |
398 |
break;
|
399 |
} |
400 |
} |
401 |
|
402 |
static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
403 |
{ |
404 |
UHCIState *s = opaque; |
405 |
uint32_t val; |
406 |
|
407 |
addr &= 0x1f;
|
408 |
switch(addr) {
|
409 |
case 0x0c: |
410 |
val = s->sof_timing; |
411 |
break;
|
412 |
default:
|
413 |
val = 0xff;
|
414 |
break;
|
415 |
} |
416 |
return val;
|
417 |
} |
418 |
|
419 |
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
420 |
{ |
421 |
UHCIState *s = opaque; |
422 |
|
423 |
addr &= 0x1f;
|
424 |
dprintf("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
|
425 |
|
426 |
switch(addr) {
|
427 |
case 0x00: |
428 |
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
429 |
/* start frame processing */
|
430 |
qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
431 |
s->status &= ~UHCI_STS_HCHALTED; |
432 |
} else if (!(val & UHCI_CMD_RS)) { |
433 |
s->status |= UHCI_STS_HCHALTED; |
434 |
} |
435 |
if (val & UHCI_CMD_GRESET) {
|
436 |
UHCIPort *port; |
437 |
USBDevice *dev; |
438 |
int i;
|
439 |
|
440 |
/* send reset on the USB bus */
|
441 |
for(i = 0; i < NB_PORTS; i++) { |
442 |
port = &s->ports[i]; |
443 |
dev = port->port.dev; |
444 |
if (dev) {
|
445 |
usb_send_msg(dev, USB_MSG_RESET); |
446 |
} |
447 |
} |
448 |
uhci_reset(s); |
449 |
return;
|
450 |
} |
451 |
if (val & UHCI_CMD_HCRESET) {
|
452 |
uhci_reset(s); |
453 |
return;
|
454 |
} |
455 |
s->cmd = val; |
456 |
break;
|
457 |
case 0x02: |
458 |
s->status &= ~val; |
459 |
/* XXX: the chip spec is not coherent, so we add a hidden
|
460 |
register to distinguish between IOC and SPD */
|
461 |
if (val & UHCI_STS_USBINT)
|
462 |
s->status2 = 0;
|
463 |
uhci_update_irq(s); |
464 |
break;
|
465 |
case 0x04: |
466 |
s->intr = val; |
467 |
uhci_update_irq(s); |
468 |
break;
|
469 |
case 0x06: |
470 |
if (s->status & UHCI_STS_HCHALTED)
|
471 |
s->frnum = val & 0x7ff;
|
472 |
break;
|
473 |
case 0x10 ... 0x1f: |
474 |
{ |
475 |
UHCIPort *port; |
476 |
USBDevice *dev; |
477 |
int n;
|
478 |
|
479 |
n = (addr >> 1) & 7; |
480 |
if (n >= NB_PORTS)
|
481 |
return;
|
482 |
port = &s->ports[n]; |
483 |
dev = port->port.dev; |
484 |
if (dev) {
|
485 |
/* port reset */
|
486 |
if ( (val & UHCI_PORT_RESET) &&
|
487 |
!(port->ctrl & UHCI_PORT_RESET) ) { |
488 |
usb_send_msg(dev, USB_MSG_RESET); |
489 |
} |
490 |
} |
491 |
port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
492 |
/* some bits are reset when a '1' is written to them */
|
493 |
port->ctrl &= ~(val & 0x000a);
|
494 |
} |
495 |
break;
|
496 |
} |
497 |
} |
498 |
|
499 |
static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
500 |
{ |
501 |
UHCIState *s = opaque; |
502 |
uint32_t val; |
503 |
|
504 |
addr &= 0x1f;
|
505 |
switch(addr) {
|
506 |
case 0x00: |
507 |
val = s->cmd; |
508 |
break;
|
509 |
case 0x02: |
510 |
val = s->status; |
511 |
break;
|
512 |
case 0x04: |
513 |
val = s->intr; |
514 |
break;
|
515 |
case 0x06: |
516 |
val = s->frnum; |
517 |
break;
|
518 |
case 0x10 ... 0x1f: |
519 |
{ |
520 |
UHCIPort *port; |
521 |
int n;
|
522 |
n = (addr >> 1) & 7; |
523 |
if (n >= NB_PORTS)
|
524 |
goto read_default;
|
525 |
port = &s->ports[n]; |
526 |
val = port->ctrl; |
527 |
} |
528 |
break;
|
529 |
default:
|
530 |
read_default:
|
531 |
val = 0xff7f; /* disabled port */ |
532 |
break;
|
533 |
} |
534 |
|
535 |
dprintf("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
|
536 |
|
537 |
return val;
|
538 |
} |
539 |
|
540 |
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
541 |
{ |
542 |
UHCIState *s = opaque; |
543 |
|
544 |
addr &= 0x1f;
|
545 |
dprintf("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
|
546 |
|
547 |
switch(addr) {
|
548 |
case 0x08: |
549 |
s->fl_base_addr = val & ~0xfff;
|
550 |
break;
|
551 |
} |
552 |
} |
553 |
|
554 |
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
555 |
{ |
556 |
UHCIState *s = opaque; |
557 |
uint32_t val; |
558 |
|
559 |
addr &= 0x1f;
|
560 |
switch(addr) {
|
561 |
case 0x08: |
562 |
val = s->fl_base_addr; |
563 |
break;
|
564 |
default:
|
565 |
val = 0xffffffff;
|
566 |
break;
|
567 |
} |
568 |
return val;
|
569 |
} |
570 |
|
571 |
/* signal resume if controller suspended */
|
572 |
static void uhci_resume (void *opaque) |
573 |
{ |
574 |
UHCIState *s = (UHCIState *)opaque; |
575 |
|
576 |
if (!s)
|
577 |
return;
|
578 |
|
579 |
if (s->cmd & UHCI_CMD_EGSM) {
|
580 |
s->cmd |= UHCI_CMD_FGR; |
581 |
s->status |= UHCI_STS_RD; |
582 |
uhci_update_irq(s); |
583 |
} |
584 |
} |
585 |
|
586 |
static void uhci_attach(USBPort *port1, USBDevice *dev) |
587 |
{ |
588 |
UHCIState *s = port1->opaque; |
589 |
UHCIPort *port = &s->ports[port1->index]; |
590 |
|
591 |
if (dev) {
|
592 |
if (port->port.dev) {
|
593 |
usb_attach(port1, NULL);
|
594 |
} |
595 |
/* set connect status */
|
596 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
597 |
|
598 |
/* update speed */
|
599 |
if (dev->speed == USB_SPEED_LOW)
|
600 |
port->ctrl |= UHCI_PORT_LSDA; |
601 |
else
|
602 |
port->ctrl &= ~UHCI_PORT_LSDA; |
603 |
|
604 |
uhci_resume(s); |
605 |
|
606 |
port->port.dev = dev; |
607 |
/* send the attach message */
|
608 |
usb_send_msg(dev, USB_MSG_ATTACH); |
609 |
} else {
|
610 |
/* set connect status */
|
611 |
if (port->ctrl & UHCI_PORT_CCS) {
|
612 |
port->ctrl &= ~UHCI_PORT_CCS; |
613 |
port->ctrl |= UHCI_PORT_CSC; |
614 |
} |
615 |
/* disable port */
|
616 |
if (port->ctrl & UHCI_PORT_EN) {
|
617 |
port->ctrl &= ~UHCI_PORT_EN; |
618 |
port->ctrl |= UHCI_PORT_ENC; |
619 |
} |
620 |
|
621 |
uhci_resume(s); |
622 |
|
623 |
dev = port->port.dev; |
624 |
if (dev) {
|
625 |
/* send the detach message */
|
626 |
usb_send_msg(dev, USB_MSG_DETACH); |
627 |
} |
628 |
port->port.dev = NULL;
|
629 |
} |
630 |
} |
631 |
|
632 |
static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
633 |
{ |
634 |
int i, ret;
|
635 |
|
636 |
dprintf("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
|
637 |
pid2str(p->pid), p->devaddr, p->devep, p->len); |
638 |
if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP)
|
639 |
dump_data(p->data, p->len); |
640 |
|
641 |
ret = USB_RET_NODEV; |
642 |
for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { |
643 |
UHCIPort *port = &s->ports[i]; |
644 |
USBDevice *dev = port->port.dev; |
645 |
|
646 |
if (dev && (port->ctrl & UHCI_PORT_EN))
|
647 |
ret = dev->handle_packet(dev, p); |
648 |
} |
649 |
|
650 |
dprintf("uhci: packet exit. ret %d len %d\n", ret, p->len);
|
651 |
if (p->pid == USB_TOKEN_IN && ret > 0) |
652 |
dump_data(p->data, ret); |
653 |
|
654 |
return ret;
|
655 |
} |
656 |
|
657 |
static void uhci_async_complete(USBPacket * packet, void *opaque); |
658 |
static void uhci_process_frame(UHCIState *s); |
659 |
|
660 |
/* return -1 if fatal error (frame must be stopped)
|
661 |
0 if TD successful
|
662 |
1 if TD unsuccessful or inactive
|
663 |
*/
|
664 |
static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
665 |
{ |
666 |
int len = 0, max_len, err, ret; |
667 |
uint8_t pid; |
668 |
|
669 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
670 |
pid = td->token & 0xff;
|
671 |
|
672 |
ret = async->packet.len; |
673 |
|
674 |
if (td->ctrl & TD_CTRL_IOC)
|
675 |
*int_mask |= 0x01;
|
676 |
|
677 |
if (td->ctrl & TD_CTRL_IOS)
|
678 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
679 |
|
680 |
if (ret < 0) |
681 |
goto out;
|
682 |
|
683 |
len = async->packet.len; |
684 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
685 |
|
686 |
/* The NAK bit may have been set by a previous frame, so clear it
|
687 |
here. The docs are somewhat unclear, but win2k relies on this
|
688 |
behavior. */
|
689 |
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
690 |
|
691 |
if (pid == USB_TOKEN_IN) {
|
692 |
if (len > max_len) {
|
693 |
len = max_len; |
694 |
ret = USB_RET_BABBLE; |
695 |
goto out;
|
696 |
} |
697 |
|
698 |
if (len > 0) { |
699 |
/* write the data back */
|
700 |
cpu_physical_memory_write(td->buffer, async->buffer, len); |
701 |
} |
702 |
|
703 |
if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
704 |
*int_mask |= 0x02;
|
705 |
/* short packet: do not update QH */
|
706 |
dprintf("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
|
707 |
return 1; |
708 |
} |
709 |
} |
710 |
|
711 |
/* success */
|
712 |
return 0; |
713 |
|
714 |
out:
|
715 |
switch(ret) {
|
716 |
case USB_RET_STALL:
|
717 |
td->ctrl |= TD_CTRL_STALL; |
718 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
719 |
return 1; |
720 |
|
721 |
case USB_RET_BABBLE:
|
722 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
723 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
724 |
/* frame interrupted */
|
725 |
return -1; |
726 |
|
727 |
case USB_RET_NAK:
|
728 |
td->ctrl |= TD_CTRL_NAK; |
729 |
if (pid == USB_TOKEN_SETUP)
|
730 |
break;
|
731 |
return 1; |
732 |
|
733 |
case USB_RET_NODEV:
|
734 |
default:
|
735 |
break;
|
736 |
} |
737 |
|
738 |
/* Retry the TD if error count is not zero */
|
739 |
|
740 |
td->ctrl |= TD_CTRL_TIMEOUT; |
741 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
742 |
if (err != 0) { |
743 |
err--; |
744 |
if (err == 0) { |
745 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
746 |
s->status |= UHCI_STS_USBERR; |
747 |
uhci_update_irq(s); |
748 |
} |
749 |
} |
750 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
751 |
(err << TD_CTRL_ERROR_SHIFT); |
752 |
return 1; |
753 |
} |
754 |
|
755 |
static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
756 |
{ |
757 |
UHCIAsync *async; |
758 |
int len = 0, max_len; |
759 |
uint8_t pid; |
760 |
|
761 |
/* Is active ? */
|
762 |
if (!(td->ctrl & TD_CTRL_ACTIVE))
|
763 |
return 1; |
764 |
|
765 |
async = uhci_async_find_td(s, addr, td->token); |
766 |
if (async) {
|
767 |
/* Already submitted */
|
768 |
async->valid = 10;
|
769 |
|
770 |
if (!async->done)
|
771 |
return 1; |
772 |
|
773 |
uhci_async_unlink(s, async); |
774 |
goto done;
|
775 |
} |
776 |
|
777 |
/* Allocate new packet */
|
778 |
async = uhci_async_alloc(s); |
779 |
if (!async)
|
780 |
return 1; |
781 |
|
782 |
async->valid = 10;
|
783 |
async->td = addr; |
784 |
async->token = td->token; |
785 |
|
786 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
787 |
pid = td->token & 0xff;
|
788 |
|
789 |
async->packet.pid = pid; |
790 |
async->packet.devaddr = (td->token >> 8) & 0x7f; |
791 |
async->packet.devep = (td->token >> 15) & 0xf; |
792 |
async->packet.data = async->buffer; |
793 |
async->packet.len = max_len; |
794 |
async->packet.complete_cb = uhci_async_complete; |
795 |
async->packet.complete_opaque = s; |
796 |
|
797 |
switch(pid) {
|
798 |
case USB_TOKEN_OUT:
|
799 |
case USB_TOKEN_SETUP:
|
800 |
cpu_physical_memory_read(td->buffer, async->buffer, max_len); |
801 |
len = uhci_broadcast_packet(s, &async->packet); |
802 |
if (len >= 0) |
803 |
len = max_len; |
804 |
break;
|
805 |
|
806 |
case USB_TOKEN_IN:
|
807 |
len = uhci_broadcast_packet(s, &async->packet); |
808 |
break;
|
809 |
|
810 |
default:
|
811 |
/* invalid pid : frame interrupted */
|
812 |
uhci_async_free(s, async); |
813 |
s->status |= UHCI_STS_HCPERR; |
814 |
uhci_update_irq(s); |
815 |
return -1; |
816 |
} |
817 |
|
818 |
if (len == USB_RET_ASYNC) {
|
819 |
uhci_async_link(s, async); |
820 |
return 2; |
821 |
} |
822 |
|
823 |
async->packet.len = len; |
824 |
|
825 |
done:
|
826 |
len = uhci_complete_td(s, td, async, int_mask); |
827 |
uhci_async_free(s, async); |
828 |
return len;
|
829 |
} |
830 |
|
831 |
static void uhci_async_complete(USBPacket *packet, void *opaque) |
832 |
{ |
833 |
UHCIState *s = opaque; |
834 |
UHCIAsync *async = (UHCIAsync *) packet; |
835 |
|
836 |
dprintf("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
|
837 |
|
838 |
async->done = 1;
|
839 |
|
840 |
uhci_process_frame(s); |
841 |
} |
842 |
|
843 |
static int is_valid(uint32_t link) |
844 |
{ |
845 |
return (link & 1) == 0; |
846 |
} |
847 |
|
848 |
static int is_qh(uint32_t link) |
849 |
{ |
850 |
return (link & 2) != 0; |
851 |
} |
852 |
|
853 |
static int depth_first(uint32_t link) |
854 |
{ |
855 |
return (link & 4) != 0; |
856 |
} |
857 |
|
858 |
/* QH DB used for detecting QH loops */
|
859 |
#define UHCI_MAX_QUEUES 128 |
860 |
typedef struct { |
861 |
uint32_t addr[UHCI_MAX_QUEUES]; |
862 |
int count;
|
863 |
} QhDb; |
864 |
|
865 |
static void qhdb_reset(QhDb *db) |
866 |
{ |
867 |
db->count = 0;
|
868 |
} |
869 |
|
870 |
/* Add QH to DB. Returns 1 if already present or DB is full. */
|
871 |
static int qhdb_insert(QhDb *db, uint32_t addr) |
872 |
{ |
873 |
int i;
|
874 |
for (i = 0; i < db->count; i++) |
875 |
if (db->addr[i] == addr)
|
876 |
return 1; |
877 |
|
878 |
if (db->count >= UHCI_MAX_QUEUES)
|
879 |
return 1; |
880 |
|
881 |
db->addr[db->count++] = addr; |
882 |
return 0; |
883 |
} |
884 |
|
885 |
static void uhci_process_frame(UHCIState *s) |
886 |
{ |
887 |
uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
888 |
uint32_t curr_qh; |
889 |
int cnt, ret;
|
890 |
UHCI_TD td; |
891 |
UHCI_QH qh; |
892 |
QhDb qhdb; |
893 |
|
894 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
895 |
|
896 |
dprintf("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
|
897 |
|
898 |
cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
899 |
le32_to_cpus(&link); |
900 |
|
901 |
int_mask = 0;
|
902 |
curr_qh = 0;
|
903 |
|
904 |
qhdb_reset(&qhdb); |
905 |
|
906 |
for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
907 |
if (is_qh(link)) {
|
908 |
/* QH */
|
909 |
|
910 |
if (qhdb_insert(&qhdb, link)) {
|
911 |
/*
|
912 |
* We're going in circles. Which is not a bug because
|
913 |
* HCD is allowed to do that as part of the BW management.
|
914 |
* In our case though it makes no sense to spin here. Sync transations
|
915 |
* are already done, and async completion handler will re-process
|
916 |
* the frame when something is ready.
|
917 |
*/
|
918 |
dprintf("uhci: detected loop. qh 0x%x\n", link);
|
919 |
break;
|
920 |
} |
921 |
|
922 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); |
923 |
le32_to_cpus(&qh.link); |
924 |
le32_to_cpus(&qh.el_link); |
925 |
|
926 |
dprintf("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
|
927 |
link, qh.link, qh.el_link); |
928 |
|
929 |
if (!is_valid(qh.el_link)) {
|
930 |
/* QH w/o elements */
|
931 |
curr_qh = 0;
|
932 |
link = qh.link; |
933 |
} else {
|
934 |
/* QH with elements */
|
935 |
curr_qh = link; |
936 |
link = qh.el_link; |
937 |
} |
938 |
continue;
|
939 |
} |
940 |
|
941 |
/* TD */
|
942 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
943 |
le32_to_cpus(&td.link); |
944 |
le32_to_cpus(&td.ctrl); |
945 |
le32_to_cpus(&td.token); |
946 |
le32_to_cpus(&td.buffer); |
947 |
|
948 |
dprintf("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
949 |
link, td.link, td.ctrl, td.token, curr_qh); |
950 |
|
951 |
old_td_ctrl = td.ctrl; |
952 |
ret = uhci_handle_td(s, link, &td, &int_mask); |
953 |
if (old_td_ctrl != td.ctrl) {
|
954 |
/* update the status bits of the TD */
|
955 |
val = cpu_to_le32(td.ctrl); |
956 |
cpu_physical_memory_write((link & ~0xf) + 4, |
957 |
(const uint8_t *)&val, sizeof(val)); |
958 |
} |
959 |
|
960 |
if (ret < 0) { |
961 |
/* interrupted frame */
|
962 |
break;
|
963 |
} |
964 |
|
965 |
if (ret == 2 || ret == 1) { |
966 |
dprintf("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
967 |
link, ret == 2 ? "pend" : "skip", |
968 |
td.link, td.ctrl, td.token, curr_qh); |
969 |
|
970 |
link = curr_qh ? qh.link : td.link; |
971 |
continue;
|
972 |
} |
973 |
|
974 |
/* completed TD */
|
975 |
|
976 |
dprintf("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
|
977 |
link, td.link, td.ctrl, td.token, curr_qh); |
978 |
|
979 |
link = td.link; |
980 |
|
981 |
if (curr_qh) {
|
982 |
/* update QH element link */
|
983 |
qh.el_link = link; |
984 |
val = cpu_to_le32(qh.el_link); |
985 |
cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
986 |
(const uint8_t *)&val, sizeof(val)); |
987 |
|
988 |
if (!depth_first(link)) {
|
989 |
/* done with this QH */
|
990 |
|
991 |
dprintf("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
|
992 |
curr_qh, qh.link, qh.el_link); |
993 |
|
994 |
curr_qh = 0;
|
995 |
link = qh.link; |
996 |
} |
997 |
} |
998 |
|
999 |
/* go to the next entry */
|
1000 |
} |
1001 |
|
1002 |
s->pending_int_mask = int_mask; |
1003 |
} |
1004 |
|
1005 |
static void uhci_frame_timer(void *opaque) |
1006 |
{ |
1007 |
UHCIState *s = opaque; |
1008 |
int64_t expire_time; |
1009 |
|
1010 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
1011 |
/* Full stop */
|
1012 |
qemu_del_timer(s->frame_timer); |
1013 |
/* set hchalted bit in status - UHCI11D 2.1.2 */
|
1014 |
s->status |= UHCI_STS_HCHALTED; |
1015 |
|
1016 |
dprintf("uhci: halted\n");
|
1017 |
return;
|
1018 |
} |
1019 |
|
1020 |
/* Complete the previous frame */
|
1021 |
if (s->pending_int_mask) {
|
1022 |
s->status2 |= s->pending_int_mask; |
1023 |
s->status |= UHCI_STS_USBINT; |
1024 |
uhci_update_irq(s); |
1025 |
} |
1026 |
|
1027 |
/* Start new frame */
|
1028 |
s->frnum = (s->frnum + 1) & 0x7ff; |
1029 |
|
1030 |
dprintf("uhci: new frame #%u\n" , s->frnum);
|
1031 |
|
1032 |
uhci_async_validate_begin(s); |
1033 |
|
1034 |
uhci_process_frame(s); |
1035 |
|
1036 |
uhci_async_validate_end(s); |
1037 |
|
1038 |
/* prepare the timer for the next frame */
|
1039 |
expire_time = qemu_get_clock(vm_clock) + |
1040 |
(ticks_per_sec / FRAME_TIMER_FREQ); |
1041 |
qemu_mod_timer(s->frame_timer, expire_time); |
1042 |
} |
1043 |
|
1044 |
static void uhci_map(PCIDevice *pci_dev, int region_num, |
1045 |
uint32_t addr, uint32_t size, int type)
|
1046 |
{ |
1047 |
UHCIState *s = (UHCIState *)pci_dev; |
1048 |
|
1049 |
register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
1050 |
register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
1051 |
register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
1052 |
register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
1053 |
register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
1054 |
register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
1055 |
} |
1056 |
|
1057 |
void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1058 |
{ |
1059 |
UHCIState *s; |
1060 |
uint8_t *pci_conf; |
1061 |
int i;
|
1062 |
|
1063 |
s = (UHCIState *)pci_register_device(bus, |
1064 |
"USB-UHCI", sizeof(UHCIState), |
1065 |
devfn, NULL, NULL); |
1066 |
pci_conf = s->dev.config; |
1067 |
pci_conf[0x00] = 0x86; |
1068 |
pci_conf[0x01] = 0x80; |
1069 |
pci_conf[0x02] = 0x20; |
1070 |
pci_conf[0x03] = 0x70; |
1071 |
pci_conf[0x08] = 0x01; // revision number |
1072 |
pci_conf[0x09] = 0x00; |
1073 |
pci_conf[0x0a] = 0x03; |
1074 |
pci_conf[0x0b] = 0x0c; |
1075 |
pci_conf[0x0e] = 0x00; // header_type |
1076 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
1077 |
pci_conf[0x60] = 0x10; // release number |
1078 |
|
1079 |
for(i = 0; i < NB_PORTS; i++) { |
1080 |
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
1081 |
} |
1082 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1083 |
|
1084 |
uhci_reset(s); |
1085 |
|
1086 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1087 |
to rely on this. */
|
1088 |
pci_register_io_region(&s->dev, 4, 0x20, |
1089 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
1090 |
|
1091 |
register_savevm("uhci", 0, 1, uhci_save, uhci_load, s); |
1092 |
} |
1093 |
|
1094 |
void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1095 |
{ |
1096 |
UHCIState *s; |
1097 |
uint8_t *pci_conf; |
1098 |
int i;
|
1099 |
|
1100 |
s = (UHCIState *)pci_register_device(bus, |
1101 |
"USB-UHCI", sizeof(UHCIState), |
1102 |
devfn, NULL, NULL); |
1103 |
pci_conf = s->dev.config; |
1104 |
pci_conf[0x00] = 0x86; |
1105 |
pci_conf[0x01] = 0x80; |
1106 |
pci_conf[0x02] = 0x12; |
1107 |
pci_conf[0x03] = 0x71; |
1108 |
pci_conf[0x08] = 0x01; // revision number |
1109 |
pci_conf[0x09] = 0x00; |
1110 |
pci_conf[0x0a] = 0x03; |
1111 |
pci_conf[0x0b] = 0x0c; |
1112 |
pci_conf[0x0e] = 0x00; // header_type |
1113 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
1114 |
pci_conf[0x60] = 0x10; // release number |
1115 |
|
1116 |
for(i = 0; i < NB_PORTS; i++) { |
1117 |
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
1118 |
} |
1119 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
1120 |
|
1121 |
uhci_reset(s); |
1122 |
|
1123 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1124 |
to rely on this. */
|
1125 |
pci_register_io_region(&s->dev, 4, 0x20, |
1126 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
1127 |
|
1128 |
register_savevm("uhci", 0, 1, uhci_save, uhci_load, s); |
1129 |
} |