Revision 5dc4b744
| b/hw/mips_r4k.c | ||
|---|---|---|
| 11 | 11 |
|
| 12 | 12 |
#define BIOS_FILENAME "mips_bios.bin" |
| 13 | 13 |
//#define BIOS_FILENAME "system.bin" |
| 14 |
#define KERNEL_LOAD_ADDR SIGN_EXTEND32(0x80010000) |
|
| 15 |
#define INITRD_LOAD_ADDR SIGN_EXTEND32(0x80800000) |
|
| 14 |
#define KERNEL_LOAD_ADDR (int32_t)0x80010000 |
|
| 15 |
#ifdef MIPS_HAS_MIPS64 |
|
| 16 |
#define INITRD_LOAD_ADDR (int64_t)0x80800000 |
|
| 17 |
#else |
|
| 18 |
#define INITRD_LOAD_ADDR (int32_t)0x80800000 |
|
| 19 |
#endif |
|
| 16 | 20 |
|
| 17 |
#define VIRT_TO_PHYS_ADDEND (-SIGN_EXTEND32(0x80000000LL))
|
|
| 21 |
#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
|
|
| 18 | 22 |
|
| 19 | 23 |
static const int ide_iobase[2] = { 0x1f0, 0x170 };
|
| 20 | 24 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
|
| ... | ... | |
| 76 | 80 |
kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); |
| 77 | 81 |
if (kernel_size >= 0) {
|
| 78 | 82 |
if ((entry & ~0x7fffffffULL) == 0x80000000) |
| 79 |
entry = SIGN_EXTEND32(entry);
|
|
| 83 |
entry = (int32_t)entry;
|
|
| 80 | 84 |
env->PC = entry; |
| 81 | 85 |
} else {
|
| 82 | 86 |
kernel_size = load_image(kernel_filename, |
| b/target-mips/cpu.h | ||
|---|---|---|
| 15 | 15 |
typedef unsigned int uint_fast16_t; |
| 16 | 16 |
#endif |
| 17 | 17 |
|
| 18 |
#ifdef MIPS_HAS_MIPS64 |
|
| 19 |
#define SIGN_EXTEND32(val) (((((uint64_t)(val)) & 0xFFFFFFFF) ^ 0x80000000) - 0x80000000) |
|
| 20 | 18 |
/* target_ulong size spec */ |
| 19 |
#ifdef MIPS_HAS_MIPS64 |
|
| 21 | 20 |
#define TLSZ "%016llx" |
| 22 | 21 |
#else |
| 23 |
#define SIGN_EXTEND32(val) (val) |
|
| 24 |
/* target_ulong size spec */ |
|
| 25 | 22 |
#define TLSZ "%08x" |
| 26 | 23 |
#endif |
| 27 | 24 |
|
| b/target-mips/helper.c | ||
|---|---|---|
| 86 | 86 |
#endif |
| 87 | 87 |
if (user_mode && address > 0x7FFFFFFFUL) |
| 88 | 88 |
return TLBRET_BADADDR; |
| 89 |
if (address < SIGN_EXTEND32(0x80000000UL)) {
|
|
| 89 |
if (address < (int32_t)0x80000000UL) {
|
|
| 90 | 90 |
if (!(env->hflags & MIPS_HFLAG_ERL)) {
|
| 91 | 91 |
#ifdef MIPS_USES_R4K_TLB |
| 92 | 92 |
ret = map_address(env, physical, prot, address, rw, access_type); |
| ... | ... | |
| 98 | 98 |
*physical = address; |
| 99 | 99 |
*prot = PAGE_READ | PAGE_WRITE; |
| 100 | 100 |
} |
| 101 |
} else if (address < SIGN_EXTEND32(0xA0000000UL)) {
|
|
| 101 |
} else if (address < (int32_t)0xA0000000UL) {
|
|
| 102 | 102 |
/* kseg0 */ |
| 103 | 103 |
/* XXX: check supervisor mode */ |
| 104 |
*physical = address - SIGN_EXTEND32(0x80000000UL);
|
|
| 104 |
*physical = address - (int32_t)0x80000000UL;
|
|
| 105 | 105 |
*prot = PAGE_READ | PAGE_WRITE; |
| 106 |
} else if (address < SIGN_EXTEND32(0xC0000000UL)) {
|
|
| 106 |
} else if (address < (int32_t)0xC0000000UL) {
|
|
| 107 | 107 |
/* kseg1 */ |
| 108 | 108 |
/* XXX: check supervisor mode */ |
| 109 |
*physical = address - SIGN_EXTEND32(0xA0000000UL);
|
|
| 109 |
*physical = address - (int32_t)0xA0000000UL;
|
|
| 110 | 110 |
*prot = PAGE_READ | PAGE_WRITE; |
| 111 |
} else if (address < SIGN_EXTEND32(0xE0000000UL)) {
|
|
| 111 |
} else if (address < (int32_t)0xE0000000UL) {
|
|
| 112 | 112 |
/* kseg2 */ |
| 113 | 113 |
#ifdef MIPS_USES_R4K_TLB |
| 114 | 114 |
ret = map_address(env, physical, prot, address, rw, access_type); |
| ... | ... | |
| 299 | 299 |
enter_debug_mode: |
| 300 | 300 |
env->hflags |= MIPS_HFLAG_DM; |
| 301 | 301 |
/* EJTAG probe trap enable is not implemented... */ |
| 302 |
env->PC = SIGN_EXTEND32(0xBFC00480);
|
|
| 302 |
env->PC = (int32_t)0xBFC00480;
|
|
| 303 | 303 |
break; |
| 304 | 304 |
case EXCP_RESET: |
| 305 | 305 |
cpu_reset(env); |
| ... | ... | |
| 321 | 321 |
} |
| 322 | 322 |
env->hflags |= MIPS_HFLAG_ERL; |
| 323 | 323 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
| 324 |
env->PC = SIGN_EXTEND32(0xBFC00000);
|
|
| 324 |
env->PC = (int32_t)0xBFC00000;
|
|
| 325 | 325 |
break; |
| 326 | 326 |
case EXCP_MCHECK: |
| 327 | 327 |
cause = 24; |
| ... | ... | |
| 389 | 389 |
env->CP0_Cause &= ~0x80000000; |
| 390 | 390 |
} |
| 391 | 391 |
if (env->CP0_Status & (1 << CP0St_BEV)) {
|
| 392 |
env->PC = SIGN_EXTEND32(0xBFC00200);
|
|
| 392 |
env->PC = (int32_t)0xBFC00200;
|
|
| 393 | 393 |
} else {
|
| 394 |
env->PC = SIGN_EXTEND32(0x80000000);
|
|
| 394 |
env->PC = (int32_t)0x80000000;
|
|
| 395 | 395 |
} |
| 396 | 396 |
env->hflags |= MIPS_HFLAG_EXL; |
| 397 | 397 |
env->CP0_Status |= (1 << CP0St_EXL); |
| b/target-mips/op.c | ||
|---|---|---|
| 328 | 328 |
/* Arithmetic */ |
| 329 | 329 |
void op_add (void) |
| 330 | 330 |
{
|
| 331 |
T0 = SIGN_EXTEND32((int32_t)T0 + (int32_t)T1);
|
|
| 331 |
T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
|
|
| 332 | 332 |
RETURN(); |
| 333 | 333 |
} |
| 334 | 334 |
|
| ... | ... | |
| 342 | 342 |
/* operands of same sign, result different sign */ |
| 343 | 343 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
| 344 | 344 |
} |
| 345 |
T0 = SIGN_EXTEND32(T0);
|
|
| 345 |
T0 = (int32_t)T0;
|
|
| 346 | 346 |
RETURN(); |
| 347 | 347 |
} |
| 348 | 348 |
|
| 349 | 349 |
void op_sub (void) |
| 350 | 350 |
{
|
| 351 |
T0 = SIGN_EXTEND32((int32_t)T0 - (int32_t)T1);
|
|
| 351 |
T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
|
|
| 352 | 352 |
RETURN(); |
| 353 | 353 |
} |
| 354 | 354 |
|
| ... | ... | |
| 362 | 362 |
/* operands of different sign, first operand and result different sign */ |
| 363 | 363 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
| 364 | 364 |
} |
| 365 |
T0 = SIGN_EXTEND32(T0);
|
|
| 365 |
T0 = (int32_t)T0;
|
|
| 366 | 366 |
RETURN(); |
| 367 | 367 |
} |
| 368 | 368 |
|
| 369 | 369 |
void op_mul (void) |
| 370 | 370 |
{
|
| 371 |
T0 = SIGN_EXTEND32((int32_t)T0 * (int32_t)T1);
|
|
| 371 |
T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
|
|
| 372 | 372 |
RETURN(); |
| 373 | 373 |
} |
| 374 | 374 |
|
| 375 | 375 |
void op_div (void) |
| 376 | 376 |
{
|
| 377 | 377 |
if (T1 != 0) {
|
| 378 |
env->LO = SIGN_EXTEND32((int32_t)T0 / (int32_t)T1);
|
|
| 379 |
env->HI = SIGN_EXTEND32((int32_t)T0 % (int32_t)T1);
|
|
| 378 |
env->LO = (int32_t)((int32_t)T0 / (int32_t)T1);
|
|
| 379 |
env->HI = (int32_t)((int32_t)T0 % (int32_t)T1);
|
|
| 380 | 380 |
} |
| 381 | 381 |
RETURN(); |
| 382 | 382 |
} |
| ... | ... | |
| 384 | 384 |
void op_divu (void) |
| 385 | 385 |
{
|
| 386 | 386 |
if (T1 != 0) {
|
| 387 |
env->LO = SIGN_EXTEND32((uint32_t)T0 / (uint32_t)T1);
|
|
| 388 |
env->HI = SIGN_EXTEND32((uint32_t)T0 % (uint32_t)T1);
|
|
| 387 |
env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
|
|
| 388 |
env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
|
|
| 389 | 389 |
} |
| 390 | 390 |
RETURN(); |
| 391 | 391 |
} |
| ... | ... | |
| 497 | 497 |
|
| 498 | 498 |
void op_sll (void) |
| 499 | 499 |
{
|
| 500 |
T0 = SIGN_EXTEND32((uint32_t)T0 << (uint32_t)T1);
|
|
| 500 |
T0 = (int32_t)((uint32_t)T0 << (uint32_t)T1);
|
|
| 501 | 501 |
RETURN(); |
| 502 | 502 |
} |
| 503 | 503 |
|
| 504 | 504 |
void op_sra (void) |
| 505 | 505 |
{
|
| 506 |
T0 = SIGN_EXTEND32((int32_t)T0 >> (uint32_t)T1);
|
|
| 506 |
T0 = (int32_t)((int32_t)T0 >> (uint32_t)T1);
|
|
| 507 | 507 |
RETURN(); |
| 508 | 508 |
} |
| 509 | 509 |
|
| 510 | 510 |
void op_srl (void) |
| 511 | 511 |
{
|
| 512 |
T0 = SIGN_EXTEND32((uint32_t)T0 >> (uint32_t)T1);
|
|
| 512 |
T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1);
|
|
| 513 | 513 |
RETURN(); |
| 514 | 514 |
} |
| 515 | 515 |
|
| ... | ... | |
| 518 | 518 |
target_ulong tmp; |
| 519 | 519 |
|
| 520 | 520 |
if (T1) {
|
| 521 |
tmp = SIGN_EXTEND32((uint32_t)T0 << (0x20 - (uint32_t)T1));
|
|
| 522 |
T0 = SIGN_EXTEND32((uint32_t)T0 >> (uint32_t)T1) | tmp;
|
|
| 521 |
tmp = (int32_t)((uint32_t)T0 << (0x20 - (uint32_t)T1));
|
|
| 522 |
T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1) | tmp;
|
|
| 523 | 523 |
} else |
| 524 | 524 |
T0 = T1; |
| 525 | 525 |
RETURN(); |
| ... | ... | |
| 527 | 527 |
|
| 528 | 528 |
void op_sllv (void) |
| 529 | 529 |
{
|
| 530 |
T0 = SIGN_EXTEND32((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
|
| 530 |
T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
|
| 531 | 531 |
RETURN(); |
| 532 | 532 |
} |
| 533 | 533 |
|
| 534 | 534 |
void op_srav (void) |
| 535 | 535 |
{
|
| 536 |
T0 = SIGN_EXTEND32((int32_t)T1 >> (T0 & 0x1F));
|
|
| 536 |
T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
|
|
| 537 | 537 |
RETURN(); |
| 538 | 538 |
} |
| 539 | 539 |
|
| 540 | 540 |
void op_srlv (void) |
| 541 | 541 |
{
|
| 542 |
T0 = SIGN_EXTEND32((uint32_t)T1 >> (T0 & 0x1F));
|
|
| 542 |
T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
|
|
| 543 | 543 |
RETURN(); |
| 544 | 544 |
} |
| 545 | 545 |
|
| ... | ... | |
| 549 | 549 |
|
| 550 | 550 |
T0 &= 0x1F; |
| 551 | 551 |
if (T0) {
|
| 552 |
tmp = SIGN_EXTEND32((uint32_t)T1 << (0x20 - T0));
|
|
| 553 |
T0 = SIGN_EXTEND32((uint32_t)T1 >> T0) | tmp;
|
|
| 552 |
tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
|
|
| 553 |
T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
|
|
| 554 | 554 |
} else |
| 555 | 555 |
T0 = T1; |
| 556 | 556 |
RETURN(); |
| ... | ... | |
| 842 | 842 |
|
| 843 | 843 |
static inline void set_HILO (uint64_t HILO) |
| 844 | 844 |
{
|
| 845 |
env->LO = SIGN_EXTEND32(HILO & 0xFFFFFFFF);
|
|
| 846 |
env->HI = SIGN_EXTEND32(HILO >> 32);
|
|
| 845 |
env->LO = (int32_t)(HILO & 0xFFFFFFFF);
|
|
| 846 |
env->HI = (int32_t)(HILO >> 32);
|
|
| 847 | 847 |
} |
| 848 | 848 |
|
| 849 | 849 |
void op_mult (void) |
| ... | ... | |
| 1032 | 1032 |
/* CP0 functions */ |
| 1033 | 1033 |
void op_mfc0_index (void) |
| 1034 | 1034 |
{
|
| 1035 |
T0 = SIGN_EXTEND32(env->CP0_index);
|
|
| 1035 |
T0 = (int32_t)(env->CP0_index);
|
|
| 1036 | 1036 |
RETURN(); |
| 1037 | 1037 |
} |
| 1038 | 1038 |
|
| ... | ... | |
| 1062 | 1062 |
|
| 1063 | 1063 |
void op_mfc0_pagemask (void) |
| 1064 | 1064 |
{
|
| 1065 |
T0 = SIGN_EXTEND32(env->CP0_PageMask);
|
|
| 1065 |
T0 = (int32_t)env->CP0_PageMask;
|
|
| 1066 | 1066 |
RETURN(); |
| 1067 | 1067 |
} |
| 1068 | 1068 |
|
| 1069 | 1069 |
void op_mfc0_pagegrain (void) |
| 1070 | 1070 |
{
|
| 1071 |
T0 = SIGN_EXTEND32(env->CP0_PageGrain);
|
|
| 1071 |
T0 = (int32_t)env->CP0_PageGrain;
|
|
| 1072 | 1072 |
RETURN(); |
| 1073 | 1073 |
} |
| 1074 | 1074 |
|
| 1075 | 1075 |
void op_mfc0_wired (void) |
| 1076 | 1076 |
{
|
| 1077 |
T0 = SIGN_EXTEND32(env->CP0_Wired);
|
|
| 1077 |
T0 = (int32_t)env->CP0_Wired;
|
|
| 1078 | 1078 |
RETURN(); |
| 1079 | 1079 |
} |
| 1080 | 1080 |
|
| 1081 | 1081 |
void op_mfc0_hwrena (void) |
| 1082 | 1082 |
{
|
| 1083 |
T0 = SIGN_EXTEND32(env->CP0_HWREna);
|
|
| 1083 |
T0 = (int32_t)env->CP0_HWREna;
|
|
| 1084 | 1084 |
RETURN(); |
| 1085 | 1085 |
} |
| 1086 | 1086 |
|
| ... | ... | |
| 1104 | 1104 |
|
| 1105 | 1105 |
void op_mfc0_compare (void) |
| 1106 | 1106 |
{
|
| 1107 |
T0 = SIGN_EXTEND32(env->CP0_Compare);
|
|
| 1107 |
T0 = (int32_t)env->CP0_Compare;
|
|
| 1108 | 1108 |
RETURN(); |
| 1109 | 1109 |
} |
| 1110 | 1110 |
|
| 1111 | 1111 |
void op_mfc0_status (void) |
| 1112 | 1112 |
{
|
| 1113 |
T0 = SIGN_EXTEND32(env->CP0_Status);
|
|
| 1113 |
T0 = (int32_t)env->CP0_Status;
|
|
| 1114 | 1114 |
if (env->hflags & MIPS_HFLAG_UM) |
| 1115 | 1115 |
T0 |= (1 << CP0St_UM); |
| 1116 | 1116 |
if (env->hflags & MIPS_HFLAG_ERL) |
| ... | ... | |
| 1122 | 1122 |
|
| 1123 | 1123 |
void op_mfc0_intctl (void) |
| 1124 | 1124 |
{
|
| 1125 |
T0 = SIGN_EXTEND32(env->CP0_IntCtl);
|
|
| 1125 |
T0 = (int32_t)env->CP0_IntCtl;
|
|
| 1126 | 1126 |
RETURN(); |
| 1127 | 1127 |
} |
| 1128 | 1128 |
|
| 1129 | 1129 |
void op_mfc0_srsctl (void) |
| 1130 | 1130 |
{
|
| 1131 |
T0 = SIGN_EXTEND32(env->CP0_SRSCtl);
|
|
| 1131 |
T0 = (int32_t)env->CP0_SRSCtl;
|
|
| 1132 | 1132 |
RETURN(); |
| 1133 | 1133 |
} |
| 1134 | 1134 |
|
| 1135 | 1135 |
void op_mfc0_cause (void) |
| 1136 | 1136 |
{
|
| 1137 |
T0 = SIGN_EXTEND32(env->CP0_Cause);
|
|
| 1137 |
T0 = (int32_t)env->CP0_Cause;
|
|
| 1138 | 1138 |
RETURN(); |
| 1139 | 1139 |
} |
| 1140 | 1140 |
|
| ... | ... | |
| 1146 | 1146 |
|
| 1147 | 1147 |
void op_mfc0_prid (void) |
| 1148 | 1148 |
{
|
| 1149 |
T0 = SIGN_EXTEND32(env->CP0_PRid);
|
|
| 1149 |
T0 = (int32_t)env->CP0_PRid;
|
|
| 1150 | 1150 |
RETURN(); |
| 1151 | 1151 |
} |
| 1152 | 1152 |
|
| ... | ... | |
| 1158 | 1158 |
|
| 1159 | 1159 |
void op_mfc0_config0 (void) |
| 1160 | 1160 |
{
|
| 1161 |
T0 = SIGN_EXTEND32(env->CP0_Config0);
|
|
| 1161 |
T0 = (int32_t)env->CP0_Config0;
|
|
| 1162 | 1162 |
RETURN(); |
| 1163 | 1163 |
} |
| 1164 | 1164 |
|
| 1165 | 1165 |
void op_mfc0_config1 (void) |
| 1166 | 1166 |
{
|
| 1167 |
T0 = SIGN_EXTEND32(env->CP0_Config1);
|
|
| 1167 |
T0 = (int32_t)env->CP0_Config1;
|
|
| 1168 | 1168 |
RETURN(); |
| 1169 | 1169 |
} |
| 1170 | 1170 |
|
| 1171 | 1171 |
void op_mfc0_config2 (void) |
| 1172 | 1172 |
{
|
| 1173 |
T0 = SIGN_EXTEND32(env->CP0_Config2);
|
|
| 1173 |
T0 = (int32_t)env->CP0_Config2;
|
|
| 1174 | 1174 |
RETURN(); |
| 1175 | 1175 |
} |
| 1176 | 1176 |
|
| 1177 | 1177 |
void op_mfc0_config3 (void) |
| 1178 | 1178 |
{
|
| 1179 |
T0 = SIGN_EXTEND32(env->CP0_Config3);
|
|
| 1179 |
T0 = (int32_t)env->CP0_Config3;
|
|
| 1180 | 1180 |
RETURN(); |
| 1181 | 1181 |
} |
| 1182 | 1182 |
|
| ... | ... | |
| 1188 | 1188 |
|
| 1189 | 1189 |
void op_mfc0_watchlo0 (void) |
| 1190 | 1190 |
{
|
| 1191 |
T0 = SIGN_EXTEND32(env->CP0_WatchLo);
|
|
| 1191 |
T0 = (int32_t)env->CP0_WatchLo;
|
|
| 1192 | 1192 |
RETURN(); |
| 1193 | 1193 |
} |
| 1194 | 1194 |
|
| 1195 | 1195 |
void op_mfc0_watchhi0 (void) |
| 1196 | 1196 |
{
|
| 1197 |
T0 = SIGN_EXTEND32(env->CP0_WatchHi);
|
|
| 1197 |
T0 = (int32_t)env->CP0_WatchHi;
|
|
| 1198 | 1198 |
RETURN(); |
| 1199 | 1199 |
} |
| 1200 | 1200 |
|
| ... | ... | |
| 1212 | 1212 |
|
| 1213 | 1213 |
void op_mfc0_debug (void) |
| 1214 | 1214 |
{
|
| 1215 |
T0 = SIGN_EXTEND32(env->CP0_Debug);
|
|
| 1215 |
T0 = (int32_t)env->CP0_Debug;
|
|
| 1216 | 1216 |
if (env->hflags & MIPS_HFLAG_DM) |
| 1217 | 1217 |
T0 |= 1 << CP0DB_DM; |
| 1218 | 1218 |
RETURN(); |
| ... | ... | |
| 1226 | 1226 |
|
| 1227 | 1227 |
void op_mfc0_performance0 (void) |
| 1228 | 1228 |
{
|
| 1229 |
T0 = SIGN_EXTEND32(env->CP0_Performance0);
|
|
| 1229 |
T0 = (int32_t)env->CP0_Performance0;
|
|
| 1230 | 1230 |
RETURN(); |
| 1231 | 1231 |
} |
| 1232 | 1232 |
|
| 1233 | 1233 |
void op_mfc0_taglo (void) |
| 1234 | 1234 |
{
|
| 1235 |
T0 = SIGN_EXTEND32(env->CP0_TagLo);
|
|
| 1235 |
T0 = (int32_t)env->CP0_TagLo;
|
|
| 1236 | 1236 |
RETURN(); |
| 1237 | 1237 |
} |
| 1238 | 1238 |
|
| 1239 | 1239 |
void op_mfc0_datalo (void) |
| 1240 | 1240 |
{
|
| 1241 |
T0 = SIGN_EXTEND32(env->CP0_DataLo);
|
|
| 1241 |
T0 = (int32_t)env->CP0_DataLo;
|
|
| 1242 | 1242 |
RETURN(); |
| 1243 | 1243 |
} |
| 1244 | 1244 |
|
| 1245 | 1245 |
void op_mfc0_taghi (void) |
| 1246 | 1246 |
{
|
| 1247 |
T0 = SIGN_EXTEND32(env->CP0_TagHi);
|
|
| 1247 |
T0 = (int32_t)env->CP0_TagHi;
|
|
| 1248 | 1248 |
RETURN(); |
| 1249 | 1249 |
} |
| 1250 | 1250 |
|
| 1251 | 1251 |
void op_mfc0_datahi (void) |
| 1252 | 1252 |
{
|
| 1253 |
T0 = SIGN_EXTEND32(env->CP0_DataHi);
|
|
| 1253 |
T0 = (int32_t)env->CP0_DataHi;
|
|
| 1254 | 1254 |
RETURN(); |
| 1255 | 1255 |
} |
| 1256 | 1256 |
|
| ... | ... | |
| 1262 | 1262 |
|
| 1263 | 1263 |
void op_mfc0_desave (void) |
| 1264 | 1264 |
{
|
| 1265 |
T0 = SIGN_EXTEND32(env->CP0_DESAVE);
|
|
| 1265 |
T0 = (int32_t)env->CP0_DESAVE;
|
|
| 1266 | 1266 |
RETURN(); |
| 1267 | 1267 |
} |
| 1268 | 1268 |
|
| ... | ... | |
| 1276 | 1276 |
{
|
| 1277 | 1277 |
/* Large physaddr not implemented */ |
| 1278 | 1278 |
/* 1k pages not implemented */ |
| 1279 |
env->CP0_EntryLo0 = T0 & SIGN_EXTEND32(0x3FFFFFFFUL);
|
|
| 1279 |
env->CP0_EntryLo0 = T0 & (int32_t)0x3FFFFFFF;
|
|
| 1280 | 1280 |
RETURN(); |
| 1281 | 1281 |
} |
| 1282 | 1282 |
|
| ... | ... | |
| 1284 | 1284 |
{
|
| 1285 | 1285 |
/* Large physaddr not implemented */ |
| 1286 | 1286 |
/* 1k pages not implemented */ |
| 1287 |
env->CP0_EntryLo1 = T0 & SIGN_EXTEND32(0x3FFFFFFFUL);
|
|
| 1287 |
env->CP0_EntryLo1 = T0 & (int32_t)0x3FFFFFFF;
|
|
| 1288 | 1288 |
RETURN(); |
| 1289 | 1289 |
} |
| 1290 | 1290 |
|
| ... | ... | |
| 1334 | 1334 |
|
| 1335 | 1335 |
/* 1k pages not implemented */ |
| 1336 | 1336 |
/* Ignore MIPS64 TLB for now */ |
| 1337 |
val = T0 & SIGN_EXTEND32(0xFFFFE0FF);
|
|
| 1337 |
val = T0 & (int32_t)0xFFFFE0FF;
|
|
| 1338 | 1338 |
old = env->CP0_EntryHi; |
| 1339 | 1339 |
env->CP0_EntryHi = val; |
| 1340 | 1340 |
/* If the ASID changes, flush qemu's TLB. */ |
| ... | ... | |
| 1353 | 1353 |
{
|
| 1354 | 1354 |
uint32_t val, old, mask; |
| 1355 | 1355 |
|
| 1356 |
val = T0 & SIGN_EXTEND32(0xFA78FF01);
|
|
| 1356 |
val = T0 & (int32_t)0xFA78FF01;
|
|
| 1357 | 1357 |
old = env->CP0_Status; |
| 1358 | 1358 |
if (T0 & (1 << CP0St_UM)) |
| 1359 | 1359 |
env->hflags |= MIPS_HFLAG_UM; |
| ... | ... | |
| 1431 | 1431 |
{
|
| 1432 | 1432 |
/* vectored interrupts not implemented */ |
| 1433 | 1433 |
/* Multi-CPU not implemented */ |
| 1434 |
env->CP0_EBase = SIGN_EXTEND32(0x80000000) | (T0 & 0x3FFFF000);
|
|
| 1434 |
env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
|
|
| 1435 | 1435 |
RETURN(); |
| 1436 | 1436 |
} |
| 1437 | 1437 |
|
| ... | ... | |
| 1501 | 1501 |
|
| 1502 | 1502 |
void op_mtc0_taglo (void) |
| 1503 | 1503 |
{
|
| 1504 |
env->CP0_TagLo = T0 & SIGN_EXTEND32(0xFFFFFCF6);
|
|
| 1504 |
env->CP0_TagLo = T0 & (int32_t)0xFFFFFCF6;
|
|
| 1505 | 1505 |
RETURN(); |
| 1506 | 1506 |
} |
| 1507 | 1507 |
|
| b/target-mips/op_helper.c | ||
|---|---|---|
| 167 | 167 |
|
| 168 | 168 |
static inline void set_HILO (uint64_t HILO) |
| 169 | 169 |
{
|
| 170 |
env->LO = SIGN_EXTEND32(HILO & 0xFFFFFFFF);
|
|
| 171 |
env->HI = SIGN_EXTEND32(HILO >> 32);
|
|
| 170 |
env->LO = (int32_t)(HILO & 0xFFFFFFFF);
|
|
| 171 |
env->HI = (int32_t)(HILO >> 32);
|
|
| 172 | 172 |
} |
| 173 | 173 |
|
| 174 | 174 |
void do_mult (void) |
| ... | ... | |
| 305 | 305 |
/* CP0 helpers */ |
| 306 | 306 |
void do_mfc0_random (void) |
| 307 | 307 |
{
|
| 308 |
T0 = SIGN_EXTEND32(cpu_mips_get_random(env));
|
|
| 308 |
T0 = (int32_t)cpu_mips_get_random(env);
|
|
| 309 | 309 |
} |
| 310 | 310 |
|
| 311 | 311 |
void do_mfc0_count (void) |
| 312 | 312 |
{
|
| 313 |
T0 = SIGN_EXTEND32(cpu_mips_get_count(env));
|
|
| 313 |
T0 = (int32_t)cpu_mips_get_count(env);
|
|
| 314 | 314 |
} |
| 315 | 315 |
|
| 316 | 316 |
void do_mtc0_status_debug(uint32_t old, uint32_t val) |
| ... | ... | |
| 433 | 433 |
|
| 434 | 434 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
| 435 | 435 |
tlb = &env->tlb[idx]; |
| 436 |
tlb->VPN = env->CP0_EntryHi & SIGN_EXTEND32(0xFFFFE000);
|
|
| 436 |
tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
|
|
| 437 | 437 |
tlb->ASID = env->CP0_EntryHi & 0xFF; |
| 438 | 438 |
size = env->CP0_PageMask >> 13; |
| 439 | 439 |
size = 4 * (size + 1); |
| ... | ... | |
| 478 | 478 |
uint8_t ASID; |
| 479 | 479 |
int i; |
| 480 | 480 |
|
| 481 |
tag = env->CP0_EntryHi & SIGN_EXTEND32(0xFFFFE000);
|
|
| 481 |
tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
|
|
| 482 | 482 |
ASID = env->CP0_EntryHi & 0xFF; |
| 483 | 483 |
for (i = 0; i < MIPS_TLB_NB; i++) {
|
| 484 | 484 |
tlb = &env->tlb[i]; |
| b/target-mips/translate.c | ||
|---|---|---|
| 1420 | 1420 |
case OPC_J: |
| 1421 | 1421 |
case OPC_JAL: |
| 1422 | 1422 |
/* Jump to immediate */ |
| 1423 |
btarget = ((ctx->pc + 4) & SIGN_EXTEND32(0xF0000000)) | offset;
|
|
| 1423 |
btarget = ((ctx->pc + 4) & (int32_t)0xF0000000) | offset;
|
|
| 1424 | 1424 |
break; |
| 1425 | 1425 |
case OPC_JR: |
| 1426 | 1426 |
case OPC_JALR: |
| ... | ... | |
| 4097 | 4097 |
} else {
|
| 4098 | 4098 |
env->CP0_ErrorEPC = env->PC; |
| 4099 | 4099 |
} |
| 4100 |
env->PC = SIGN_EXTEND32(0xBFC00000);
|
|
| 4100 |
env->PC = (int32_t)0xBFC00000;
|
|
| 4101 | 4101 |
#if defined (MIPS_USES_R4K_TLB) |
| 4102 | 4102 |
env->CP0_random = MIPS_TLB_NB - 1; |
| 4103 | 4103 |
env->tlb_in_use = MIPS_TLB_NB; |
| 4104 | 4104 |
#endif |
| 4105 | 4105 |
env->CP0_Wired = 0; |
| 4106 | 4106 |
/* SMP not implemented */ |
| 4107 |
env->CP0_EBase = SIGN_EXTEND32(0x80000000);
|
|
| 4107 |
env->CP0_EBase = (int32_t)0x80000000;
|
|
| 4108 | 4108 |
env->CP0_Config0 = MIPS_CONFIG0; |
| 4109 | 4109 |
env->CP0_Config1 = MIPS_CONFIG1; |
| 4110 | 4110 |
env->CP0_Config2 = MIPS_CONFIG2; |
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