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1 | 67e999be | bellard | /*
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2 | 67e999be | bellard | * QEMU Sparc32 DMA controller emulation
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3 | 67e999be | bellard | *
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4 | 67e999be | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 67e999be | bellard | *
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6 | 67e999be | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 67e999be | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 67e999be | bellard | * in the Software without restriction, including without limitation the rights
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9 | 67e999be | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 67e999be | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 67e999be | bellard | * furnished to do so, subject to the following conditions:
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12 | 67e999be | bellard | *
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13 | 67e999be | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 67e999be | bellard | * all copies or substantial portions of the Software.
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15 | 67e999be | bellard | *
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16 | 67e999be | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 67e999be | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 67e999be | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 67e999be | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 67e999be | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 67e999be | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 67e999be | bellard | * THE SOFTWARE.
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23 | 67e999be | bellard | */
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24 | 67e999be | bellard | #include "vl.h" |
25 | 67e999be | bellard | |
26 | 67e999be | bellard | /* debug DMA */
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27 | 67e999be | bellard | //#define DEBUG_DMA
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28 | 67e999be | bellard | |
29 | 67e999be | bellard | /*
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30 | 67e999be | bellard | * This is the DMA controller part of chip STP2000 (Master I/O), also
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31 | 67e999be | bellard | * produced as NCR89C100. See
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32 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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33 | 67e999be | bellard | * and
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34 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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35 | 67e999be | bellard | */
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36 | 67e999be | bellard | |
37 | 67e999be | bellard | #ifdef DEBUG_DMA
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38 | 67e999be | bellard | #define DPRINTF(fmt, args...) \
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39 | 67e999be | bellard | do { printf("DMA: " fmt , ##args); } while (0) |
40 | 67e999be | bellard | #else
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41 | 67e999be | bellard | #define DPRINTF(fmt, args...)
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42 | 67e999be | bellard | #endif
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43 | 67e999be | bellard | |
44 | 67e999be | bellard | #define DMA_REGS 8 |
45 | 67e999be | bellard | #define DMA_MAXADDR (DMA_REGS * 4 - 1) |
46 | 67e999be | bellard | |
47 | 67e999be | bellard | #define DMA_VER 0xa0000000 |
48 | 67e999be | bellard | #define DMA_INTR 1 |
49 | 67e999be | bellard | #define DMA_INTREN 0x10 |
50 | 67e999be | bellard | #define DMA_WRITE_MEM 0x100 |
51 | 67e999be | bellard | #define DMA_LOADED 0x04000000 |
52 | 67e999be | bellard | #define DMA_RESET 0x80 |
53 | 67e999be | bellard | |
54 | 67e999be | bellard | typedef struct DMAState DMAState; |
55 | 67e999be | bellard | |
56 | 67e999be | bellard | struct DMAState {
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57 | 67e999be | bellard | uint32_t dmaregs[DMA_REGS]; |
58 | d537cf6c | pbrook | qemu_irq espirq, leirq; |
59 | d537cf6c | pbrook | void *iommu, *esp_opaque, *lance_opaque;
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60 | d537cf6c | pbrook | qemu_irq *pic; |
61 | 67e999be | bellard | }; |
62 | 67e999be | bellard | |
63 | 9b94dc32 | bellard | /* Note: on sparc, the lance 16 bit bus is swapped */
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64 | 9b94dc32 | bellard | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
65 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
66 | 67e999be | bellard | { |
67 | 67e999be | bellard | DMAState *s = opaque; |
68 | 9b94dc32 | bellard | int i;
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69 | 67e999be | bellard | |
70 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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71 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
72 | 9b94dc32 | bellard | addr |= s->dmaregs[7];
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73 | 9b94dc32 | bellard | if (do_bswap) {
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74 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
75 | 9b94dc32 | bellard | } else {
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76 | 9b94dc32 | bellard | addr &= ~1;
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77 | 9b94dc32 | bellard | len &= ~1;
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78 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
79 | 9b94dc32 | bellard | for(i = 0; i < len; i += 2) { |
80 | 9b94dc32 | bellard | bswap16s((uint16_t *)(buf + i)); |
81 | 9b94dc32 | bellard | } |
82 | 9b94dc32 | bellard | } |
83 | 67e999be | bellard | } |
84 | 67e999be | bellard | |
85 | 9b94dc32 | bellard | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
86 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
87 | 67e999be | bellard | { |
88 | 67e999be | bellard | DMAState *s = opaque; |
89 | 9b94dc32 | bellard | int l, i;
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90 | 9b94dc32 | bellard | uint16_t tmp_buf[32];
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91 | 67e999be | bellard | |
92 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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93 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
94 | 9b94dc32 | bellard | addr |= s->dmaregs[7];
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95 | 9b94dc32 | bellard | if (do_bswap) {
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96 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, buf, len); |
97 | 9b94dc32 | bellard | } else {
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98 | 9b94dc32 | bellard | addr &= ~1;
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99 | 9b94dc32 | bellard | len &= ~1;
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100 | 9b94dc32 | bellard | while (len > 0) { |
101 | 9b94dc32 | bellard | l = len; |
102 | 9b94dc32 | bellard | if (l > sizeof(tmp_buf)) |
103 | 9b94dc32 | bellard | l = sizeof(tmp_buf);
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104 | 9b94dc32 | bellard | for(i = 0; i < l; i += 2) { |
105 | 9b94dc32 | bellard | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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106 | 9b94dc32 | bellard | } |
107 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); |
108 | 9b94dc32 | bellard | len -= l; |
109 | 9b94dc32 | bellard | buf += l; |
110 | 9b94dc32 | bellard | addr += l; |
111 | 9b94dc32 | bellard | } |
112 | 9b94dc32 | bellard | } |
113 | 67e999be | bellard | } |
114 | 67e999be | bellard | |
115 | 67e999be | bellard | void espdma_raise_irq(void *opaque) |
116 | 67e999be | bellard | { |
117 | 67e999be | bellard | DMAState *s = opaque; |
118 | 67e999be | bellard | |
119 | d537cf6c | pbrook | DPRINTF("Raise ESP IRQ\n");
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120 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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121 | d537cf6c | pbrook | qemu_irq_raise(s->espirq); |
122 | 67e999be | bellard | } |
123 | 67e999be | bellard | |
124 | 67e999be | bellard | void espdma_clear_irq(void *opaque) |
125 | 67e999be | bellard | { |
126 | 67e999be | bellard | DMAState *s = opaque; |
127 | 67e999be | bellard | |
128 | 67e999be | bellard | s->dmaregs[0] &= ~DMA_INTR;
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129 | d537cf6c | pbrook | DPRINTF("Lower ESP IRQ\n");
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130 | d537cf6c | pbrook | qemu_irq_lower(s->espirq); |
131 | 67e999be | bellard | } |
132 | 67e999be | bellard | |
133 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
134 | 67e999be | bellard | { |
135 | 67e999be | bellard | DMAState *s = opaque; |
136 | 67e999be | bellard | |
137 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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138 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
139 | 67e999be | bellard | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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140 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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141 | 67e999be | bellard | s->dmaregs[1] += len;
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142 | 67e999be | bellard | } |
143 | 67e999be | bellard | |
144 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
145 | 67e999be | bellard | { |
146 | 67e999be | bellard | DMAState *s = opaque; |
147 | 67e999be | bellard | |
148 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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149 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
150 | 67e999be | bellard | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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151 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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152 | 67e999be | bellard | s->dmaregs[1] += len;
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153 | 67e999be | bellard | } |
154 | 67e999be | bellard | |
155 | 67e999be | bellard | static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) |
156 | 67e999be | bellard | { |
157 | 67e999be | bellard | DMAState *s = opaque; |
158 | 67e999be | bellard | uint32_t saddr; |
159 | 67e999be | bellard | |
160 | 67e999be | bellard | saddr = (addr & DMA_MAXADDR) >> 2;
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161 | 67e999be | bellard | DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->dmaregs[saddr]);
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162 | 67e999be | bellard | |
163 | 67e999be | bellard | return s->dmaregs[saddr];
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164 | 67e999be | bellard | } |
165 | 67e999be | bellard | |
166 | 67e999be | bellard | static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
167 | 67e999be | bellard | { |
168 | 67e999be | bellard | DMAState *s = opaque; |
169 | 67e999be | bellard | uint32_t saddr; |
170 | 67e999be | bellard | |
171 | 67e999be | bellard | saddr = (addr & DMA_MAXADDR) >> 2;
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172 | 67e999be | bellard | DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
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173 | 67e999be | bellard | switch (saddr) {
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174 | 67e999be | bellard | case 0: |
175 | d537cf6c | pbrook | if (!(val & DMA_INTREN)) {
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176 | d537cf6c | pbrook | DPRINTF("Lower ESP IRQ\n");
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177 | d537cf6c | pbrook | qemu_irq_lower(s->espirq); |
178 | d537cf6c | pbrook | } |
179 | 67e999be | bellard | if (val & DMA_RESET) {
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180 | 67e999be | bellard | esp_reset(s->esp_opaque); |
181 | 67e999be | bellard | } else if (val & 0x40) { |
182 | 67e999be | bellard | val &= ~0x40;
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183 | 67e999be | bellard | } else if (val == 0) |
184 | 67e999be | bellard | val = 0x40;
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185 | 67e999be | bellard | val &= 0x0fffffff;
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186 | 67e999be | bellard | val |= DMA_VER; |
187 | 67e999be | bellard | break;
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188 | 67e999be | bellard | case 1: |
189 | 67e999be | bellard | s->dmaregs[0] |= DMA_LOADED;
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190 | 67e999be | bellard | break;
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191 | 67e999be | bellard | case 4: |
192 | d537cf6c | pbrook | /* ??? Should this mask out the lance IRQ? The NIC may re-assert
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193 | d537cf6c | pbrook | this IRQ unexpectedly. */
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194 | d537cf6c | pbrook | if (!(val & DMA_INTREN)) {
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195 | d537cf6c | pbrook | DPRINTF("Lower Lance IRQ\n");
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196 | d537cf6c | pbrook | qemu_irq_lower(s->leirq); |
197 | d537cf6c | pbrook | } |
198 | 67e999be | bellard | if (val & DMA_RESET)
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199 | 67e999be | bellard | pcnet_h_reset(s->lance_opaque); |
200 | 67e999be | bellard | val &= 0x0fffffff;
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201 | 67e999be | bellard | val |= DMA_VER; |
202 | 67e999be | bellard | break;
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203 | 67e999be | bellard | default:
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204 | 67e999be | bellard | break;
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205 | 67e999be | bellard | } |
206 | 67e999be | bellard | s->dmaregs[saddr] = val; |
207 | 67e999be | bellard | } |
208 | 67e999be | bellard | |
209 | 67e999be | bellard | static CPUReadMemoryFunc *dma_mem_read[3] = { |
210 | 67e999be | bellard | dma_mem_readl, |
211 | 67e999be | bellard | dma_mem_readl, |
212 | 67e999be | bellard | dma_mem_readl, |
213 | 67e999be | bellard | }; |
214 | 67e999be | bellard | |
215 | 67e999be | bellard | static CPUWriteMemoryFunc *dma_mem_write[3] = { |
216 | 67e999be | bellard | dma_mem_writel, |
217 | 67e999be | bellard | dma_mem_writel, |
218 | 67e999be | bellard | dma_mem_writel, |
219 | 67e999be | bellard | }; |
220 | 67e999be | bellard | |
221 | 67e999be | bellard | static void dma_reset(void *opaque) |
222 | 67e999be | bellard | { |
223 | 67e999be | bellard | DMAState *s = opaque; |
224 | 67e999be | bellard | |
225 | 67e999be | bellard | memset(s->dmaregs, 0, DMA_REGS * 4); |
226 | 67e999be | bellard | s->dmaregs[0] = DMA_VER;
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227 | 67e999be | bellard | s->dmaregs[4] = DMA_VER;
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228 | 67e999be | bellard | } |
229 | 67e999be | bellard | |
230 | 67e999be | bellard | static void dma_save(QEMUFile *f, void *opaque) |
231 | 67e999be | bellard | { |
232 | 67e999be | bellard | DMAState *s = opaque; |
233 | 67e999be | bellard | unsigned int i; |
234 | 67e999be | bellard | |
235 | 67e999be | bellard | for (i = 0; i < DMA_REGS; i++) |
236 | 67e999be | bellard | qemu_put_be32s(f, &s->dmaregs[i]); |
237 | 67e999be | bellard | } |
238 | 67e999be | bellard | |
239 | 67e999be | bellard | static int dma_load(QEMUFile *f, void *opaque, int version_id) |
240 | 67e999be | bellard | { |
241 | 67e999be | bellard | DMAState *s = opaque; |
242 | 67e999be | bellard | unsigned int i; |
243 | 67e999be | bellard | |
244 | 67e999be | bellard | if (version_id != 1) |
245 | 67e999be | bellard | return -EINVAL;
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246 | 67e999be | bellard | for (i = 0; i < DMA_REGS; i++) |
247 | 67e999be | bellard | qemu_get_be32s(f, &s->dmaregs[i]); |
248 | 67e999be | bellard | |
249 | 67e999be | bellard | return 0; |
250 | 67e999be | bellard | } |
251 | 67e999be | bellard | |
252 | 5dcb6b91 | blueswir1 | void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq espirq,
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253 | 5dcb6b91 | blueswir1 | qemu_irq leirq, void *iommu)
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254 | 67e999be | bellard | { |
255 | 67e999be | bellard | DMAState *s; |
256 | 67e999be | bellard | int dma_io_memory;
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257 | 67e999be | bellard | |
258 | 67e999be | bellard | s = qemu_mallocz(sizeof(DMAState));
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259 | 67e999be | bellard | if (!s)
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260 | 67e999be | bellard | return NULL; |
261 | 67e999be | bellard | |
262 | 67e999be | bellard | s->espirq = espirq; |
263 | 67e999be | bellard | s->leirq = leirq; |
264 | 67e999be | bellard | s->iommu = iommu; |
265 | 67e999be | bellard | |
266 | 67e999be | bellard | dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
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267 | 67e999be | bellard | cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory); |
268 | 67e999be | bellard | |
269 | 67e999be | bellard | register_savevm("sparc32_dma", daddr, 1, dma_save, dma_load, s); |
270 | 67e999be | bellard | qemu_register_reset(dma_reset, s); |
271 | 67e999be | bellard | |
272 | 67e999be | bellard | return s;
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273 | 67e999be | bellard | } |
274 | 67e999be | bellard | |
275 | 67e999be | bellard | void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque, |
276 | 67e999be | bellard | void *lance_opaque)
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277 | 67e999be | bellard | { |
278 | 67e999be | bellard | DMAState *s = opaque; |
279 | 67e999be | bellard | |
280 | 67e999be | bellard | s->esp_opaque = esp_opaque; |
281 | 67e999be | bellard | s->lance_opaque = lance_opaque; |
282 | 67e999be | bellard | } |