Archipelago » qemu

#if defined(TARGET_SPARC64)

#define TARGET_PHYS_ADDR_SPACE_BITS 41

#elif defined(TARGET_ALPHA)

#define TARGET_PHYS_ADDR_SPACE_BITS 42

#define TARGET_VIRT_ADDR_SPACE_BITS 42

    s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);

}

{

    ESPState *s;

    int esp_io_memory;

    /* HW */

    qemu_irq irq;

    int dma_chann;

    /* Controller state */

    QEMUTimer *result_timer;

    uint8_t state;

static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)

{

}

static void fdctrl_write_mem (void *opaque, 

                              target_phys_addr_t reg, uint32_t value)

{

}

static CPUReadMemoryFunc *fdctrl_mem_read[3] = {

}

fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, 

                       BlockDriverState **fds)

{

    fdctrl_t *fdctrl;

        io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl);

        cpu_register_physical_memory(io_base, 0x08, io_mem);

    } else {

    }

    register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);

    qemu_register_reset(fdctrl_external_reset, fdctrl);

#define PAGE_MASK	(PAGE_SIZE - 1)

typedef struct IOMMUState {

    uint32_t regs[IOMMU_NREGS];

} IOMMUState;

static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)

{

    IOMMUState *s = opaque;

    saddr = (addr - s->addr) >> 2;

    switch (saddr) {

static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)

{

    IOMMUState *s = opaque;

    saddr = (addr - s->addr) >> 2;

    DPRINTF("write reg[%d] = %x\n", saddr, val);

    case IOMMU_CTRL:

	switch (val & IOMMU_CTRL_RNGE) {

	case IOMMU_RNGE_16MB:

	    break;

	case IOMMU_RNGE_32MB:

	    break;

	case IOMMU_RNGE_64MB:

	    break;

	case IOMMU_RNGE_128MB:

	    break;

	case IOMMU_RNGE_256MB:

	    break;

	case IOMMU_RNGE_512MB:

	    break;

	case IOMMU_RNGE_1GB:

	    break;

	default:

	case IOMMU_RNGE_2GB:

	    break;

	}

	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);

	break;

    case IOMMU_BASE:

    iommu_mem_writew,

};

{

    uint32_t iopte;

    return ldl_phys(iopte);

}

{

    uint32_t tmppte;

    return pa;

}

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,

                           uint8_t *buf, int len, int is_write)

{

    while (len > 0) {

        page = addr & TARGET_PAGE_MASK;

    IOMMUState *s = opaque;

    int i;

    for (i = 0; i < IOMMU_NREGS; i++)

	qemu_put_be32s(f, &s->regs[i]);

}

static int iommu_load(QEMUFile *f, void *opaque, int version_id)

    IOMMUState *s = opaque;

    int i;

        return -EINVAL;

    for (i = 0; i < IOMMU_NREGS; i++)

	qemu_put_be32s(f, &s->regs[i]);

    return 0;

}

    s->regs[0] = IOMMU_VERSION;

}

{

    IOMMUState *s;

    int iommu_io_memory;

    iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);

    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

    qemu_register_reset(iommu_reset, s);

    return s;

}

    /* Hardware parameters */

    qemu_irq IRQ;

    int mem_index;

    uint32_t io_base;

    uint16_t size;

    /* RTC management */

}

/* Initialisation routine */

                       uint32_t io_base, uint16_t size,

                       int type)

{

    m48t59_t *s;

    s = qemu_mallocz(sizeof(m48t59_t));

    if (!s)

void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val);

uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr);

void m48t59_toggle_lock (m48t59_t *NVRAM, int lock);

                       uint32_t io_base, uint16_t size,

                       int type);

    (CPUWriteMemoryFunc *)&pcnet_ioport_writew,

};

{

    PCNetState *d;

    int lance_io_memory;

    s->cpu_envs[cpu] = env;

}

                         const uint32_t *intbit_to_level,

                         qemu_irq **irq)

{

    return 0;

}

{

    int slavio_misc_io_memory;

    MiscState *s;

    // System control

    cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);

    // Power management

    s->irq = irq;

}

{

    int slavio_serial_io_memory, i;

    SerialState *s;

    put_queue(s, 0);

}

{

    int slavio_serial_io_memory, i;

    SerialState *s;

    slavio_timer_irq(s);

}

{

    int slavio_timer_io_memory;

    SLAVIO_TIMERState *s;

    return 0;

}

{

    DMAState *s;

    int dma_io_memory;

#define MAX_CPUS 16

struct hwdef {

    long vram_size, nvram_size;

    // IRQ numbers are not PIL ones, but master interrupt controller register

    // bit numbers

    iommu = iommu_init(hwdef->iommu_base);

    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,

                                       &hwdef->intbit_to_level[0],

                                       &slavio_irq);

    for(i = 0; i < smp_cpus; i++) {

    nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,

                        hwdef->nvram_size, 8);

    for (i = 0; i < MAX_CPUS; i++) {

                          hwdef->clock_irq, 0, i, slavio_intctl);

    }

                      (unsigned int)-1, slavio_intctl);

    slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);

    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device

        }

    }

                                   slavio_irq[hwdef->me_irq]);

        cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);

    sparc32_dma_set_reset_data(dma, main_esp, main_lance);

}

        .dma_base     = 0x78400000,

        .esp_base     = 0x78800000,

        .le_base      = 0x78c00000,

        .vram_size    = 0x00100000,

        .nvram_size   = 0x2000,

        .esp_irq = 18,

    },

    /* SS-10 */

    {

        .cs_base      = -1,

        .vram_size    = 0x00100000,

        .nvram_size   = 0x2000,

        .esp_irq = 18,

                              const char *initrd_filename, const char *cpu_model,

                              unsigned int machine, int max_ram)

{

        fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",

        exit(1);

    }

    sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model);

        cpu_model = "TI SuperSparc II";

    sun4m_common_init(ram_size, boot_device, ds, kernel_filename,

                      kernel_cmdline, initrd_filename, cpu_model,

}

QEMUMachine ss5_machine = {

#define TCX_TEC_NREGS    0x1000

typedef struct TCXState {

    DisplayState *ds;

    uint8_t *vram;

    uint32_t *vram24, *cplane;

{

    TCXState *s = opaque;

    qemu_put_be32s(f, (uint32_t *)&s->vram);

    qemu_put_be32s(f, (uint32_t *)&s->vram24);

    qemu_put_be32s(f, (uint32_t *)&s->cplane);

{

    TCXState *s = opaque;

        return -EINVAL;

    qemu_get_be32s(f, (uint32_t *)&s->vram);

    qemu_get_be32s(f, (uint32_t *)&s->vram24);

    qemu_get_be32s(f, (uint32_t *)&s->cplane);

    tcx_dummy_writel,

};

              unsigned long vram_offset, int vram_size, int width, int height,

              int depth)

{

    // 8-bit plane

    s->vram = vram_base;

    size = vram_size;

    vram_offset += size;

    vram_base += size;

    io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);

    dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,

                                          s);

                                 dummy_memory);

    if (depth == 24) {

        // 24-bit plane

        size = vram_size * 4;

        s->vram24 = (uint32_t *)vram_base;

        s->vram24_offset = vram_offset;

        vram_offset += size;

        vram_base += size;

        size = vram_size * 4;

        s->cplane = (uint32_t *)vram_base;

        s->cplane_offset = vram_offset;

        graphic_console_init(s->ds, tcx24_update_display,

                             tcx24_invalidate_display, tcx24_screen_dump, s);

    } else {

                                     dummy_memory);

        graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,

                             tcx_screen_dump, s);

    }

    // NetBSD writes here even with 8-bit display

                                 dummy_memory);

    qemu_register_reset(tcx_reset, s);

    tcx_reset(s);

    dpy_resize(s->ds, width, height);

int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

void raise_exception(int tt);

                          int is_asi);

#include "cpu-all.h"

    }

    *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);

    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */

    /* Context base + context number */

    /* Even if large ptes, we map only one 4KB page in the cache to

       avoid filling it too fast */

    return error_code;

}

                              int is_user, int is_softmmu)

{

    target_phys_addr_t paddr;

    int error_code = 0, prot, ret = 0, access_index;

    error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);

	vaddr = address & TARGET_PAGE_MASK;

	paddr &= TARGET_PAGE_MASK;

#ifdef DEBUG_MMU

#endif

	ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);

	return ret;

    uint32_t pde;

    /* Context base + context number */

    pde = ldl_phys(pde_ptr);

    switch (pde & PTE_ENTRYTYPE_MASK) {

#ifdef DEBUG_MMU

void dump_mmu(CPUState *env)

{

    uint32_t pde;

    printf("MMU dump:\n");

    pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);

    pde = ldl_phys(pde_ptr);

    for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {

	    pa = cpu_get_phys_page_debug(env, va);

	    for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {

		    pa = cpu_get_phys_page_debug(env, va1);

		    for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {

			    pa = cpu_get_phys_page_debug(env, va2);

			}

		    }

		}

	    break;

        }

	break;

    default:

        do_unassigned_access(T0, 0, 0, 1);

	ret = 0;

            }

	}

	return;

    case 0x31: /* Ross RT620 I-cache flush */

    case 0x36: /* I-cache flash clear */

    case 0x37: /* D-cache flash clear */

        break;

    case 9: /* Supervisor code access, XXX */

    default:

        do_unassigned_access(T0, 1, 0, 1);

	return;

#endif

#ifndef TARGET_SPARC64

                          int is_asi)

{

    CPUState *saved_env;

    env->mmuregs[4] = addr; /* Fault address register */

    if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {

#ifdef DEBUG_UNASSIGNED

               "\n", addr, env->pc);

#endif

        raise_exception(TT_DATA_ACCESS);

    env = saved_env;

}

#else

                          int is_asi)

{

#ifdef DEBUG_UNASSIGNED

       generated code */

    saved_env = env;

    env = cpu_single_env;

           addr, env->pc);

    env = saved_env;

#endif

typedef struct fdctrl_t fdctrl_t;

fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, 

                       BlockDriverState **fds);

int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);

void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);

void pcnet_h_reset(void *opaque);

/* vmmouse.c */

void *vmmouse_init(void *m);

extern QEMUMachine ss5_machine, ss10_machine;

/* iommu.c */

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,

                                 uint8_t *buf, int len, int is_write);

static inline void sparc_iommu_memory_read(void *opaque,

}

/* tcx.c */

              int depth);

/* slavio_intctl.c */

void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);

                         const uint32_t *intbit_to_level,

                         qemu_irq **irq);

void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);

int load_uboot(const char *filename, target_ulong *ep, int *is_linux);

/* slavio_timer.c */

/* slavio_serial.c */

/* slavio_misc.c */

void slavio_set_power_fail(void *opaque, int power_failing);

/* esp.c */

void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);

void esp_reset(void *opaque);

/* sparc32_dma.c */

void ledma_set_irq(void *opaque, int isr);

void ledma_memory_read(void *opaque, target_phys_addr_t addr, 

                       uint8_t *buf, int len, int do_bswap);