Revision 5dcb6b91 hw/iommu.c
| b/hw/iommu.c | ||
|---|---|---|
| 87 | 87 |
#define PAGE_MASK (PAGE_SIZE - 1) |
| 88 | 88 |
|
| 89 | 89 |
typedef struct IOMMUState {
|
| 90 |
uint32_t addr;
|
|
| 90 |
target_phys_addr_t addr;
|
|
| 91 | 91 |
uint32_t regs[IOMMU_NREGS]; |
| 92 |
uint32_t iostart;
|
|
| 92 |
target_phys_addr_t iostart;
|
|
| 93 | 93 |
} IOMMUState; |
| 94 | 94 |
|
| 95 | 95 |
static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) |
| 96 | 96 |
{
|
| 97 | 97 |
IOMMUState *s = opaque; |
| 98 |
uint32_t saddr;
|
|
| 98 |
target_phys_addr_t saddr;
|
|
| 99 | 99 |
|
| 100 | 100 |
saddr = (addr - s->addr) >> 2; |
| 101 | 101 |
switch (saddr) {
|
| ... | ... | |
| 110 | 110 |
static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 111 | 111 |
{
|
| 112 | 112 |
IOMMUState *s = opaque; |
| 113 |
uint32_t saddr;
|
|
| 113 |
target_phys_addr_t saddr;
|
|
| 114 | 114 |
|
| 115 | 115 |
saddr = (addr - s->addr) >> 2; |
| 116 | 116 |
DPRINTF("write reg[%d] = %x\n", saddr, val);
|
| ... | ... | |
| 118 | 118 |
case IOMMU_CTRL: |
| 119 | 119 |
switch (val & IOMMU_CTRL_RNGE) {
|
| 120 | 120 |
case IOMMU_RNGE_16MB: |
| 121 |
s->iostart = 0xff000000;
|
|
| 121 |
s->iostart = 0xffffffffff000000ULL;
|
|
| 122 | 122 |
break; |
| 123 | 123 |
case IOMMU_RNGE_32MB: |
| 124 |
s->iostart = 0xfe000000;
|
|
| 124 |
s->iostart = 0xfffffffffe000000ULL;
|
|
| 125 | 125 |
break; |
| 126 | 126 |
case IOMMU_RNGE_64MB: |
| 127 |
s->iostart = 0xfc000000;
|
|
| 127 |
s->iostart = 0xfffffffffc000000ULL;
|
|
| 128 | 128 |
break; |
| 129 | 129 |
case IOMMU_RNGE_128MB: |
| 130 |
s->iostart = 0xf8000000;
|
|
| 130 |
s->iostart = 0xfffffffff8000000ULL;
|
|
| 131 | 131 |
break; |
| 132 | 132 |
case IOMMU_RNGE_256MB: |
| 133 |
s->iostart = 0xf0000000;
|
|
| 133 |
s->iostart = 0xfffffffff0000000ULL;
|
|
| 134 | 134 |
break; |
| 135 | 135 |
case IOMMU_RNGE_512MB: |
| 136 |
s->iostart = 0xe0000000;
|
|
| 136 |
s->iostart = 0xffffffffe0000000ULL;
|
|
| 137 | 137 |
break; |
| 138 | 138 |
case IOMMU_RNGE_1GB: |
| 139 |
s->iostart = 0xc0000000;
|
|
| 139 |
s->iostart = 0xffffffffc0000000ULL;
|
|
| 140 | 140 |
break; |
| 141 | 141 |
default: |
| 142 | 142 |
case IOMMU_RNGE_2GB: |
| 143 |
s->iostart = 0x80000000;
|
|
| 143 |
s->iostart = 0xffffffff80000000ULL;
|
|
| 144 | 144 |
break; |
| 145 | 145 |
} |
| 146 |
DPRINTF("iostart = %x\n", s->iostart);
|
|
| 146 |
DPRINTF("iostart = %llx\n", s->iostart);
|
|
| 147 | 147 |
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); |
| 148 | 148 |
break; |
| 149 | 149 |
case IOMMU_BASE: |
| ... | ... | |
| 186 | 186 |
iommu_mem_writew, |
| 187 | 187 |
}; |
| 188 | 188 |
|
| 189 |
static uint32_t iommu_page_get_flags(IOMMUState *s, uint32_t addr)
|
|
| 189 |
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
|
|
| 190 | 190 |
{
|
| 191 | 191 |
uint32_t iopte; |
| 192 | 192 |
|
| ... | ... | |
| 196 | 196 |
return ldl_phys(iopte); |
| 197 | 197 |
} |
| 198 | 198 |
|
| 199 |
static uint32_t iommu_translate_pa(IOMMUState *s, uint32_t addr, uint32_t pa) |
|
| 199 |
static target_phys_addr_t iommu_translate_pa(IOMMUState *s, |
|
| 200 |
target_phys_addr_t addr, |
|
| 201 |
uint32_t pte) |
|
| 200 | 202 |
{
|
| 201 | 203 |
uint32_t tmppte; |
| 204 |
target_phys_addr_t pa; |
|
| 205 |
|
|
| 206 |
tmppte = pte; |
|
| 207 |
pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK); |
|
| 208 |
DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
|
|
| 209 |
" (iopte = %x)\n", addr, pa, tmppte); |
|
| 202 | 210 |
|
| 203 |
tmppte = pa; |
|
| 204 |
pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK); |
|
| 205 |
DPRINTF("xlate dva %x => pa %x (iopte = %x)\n", addr, pa, tmppte);
|
|
| 206 | 211 |
return pa; |
| 207 | 212 |
} |
| 208 | 213 |
|
| 209 | 214 |
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
| 210 | 215 |
uint8_t *buf, int len, int is_write) |
| 211 | 216 |
{
|
| 212 |
int l, flags; |
|
| 213 |
target_ulong page, phys_addr; |
|
| 217 |
int l; |
|
| 218 |
uint32_t flags; |
|
| 219 |
target_phys_addr_t page, phys_addr; |
|
| 214 | 220 |
|
| 215 | 221 |
while (len > 0) {
|
| 216 | 222 |
page = addr & TARGET_PAGE_MASK; |
| ... | ... | |
| 239 | 245 |
IOMMUState *s = opaque; |
| 240 | 246 |
int i; |
| 241 | 247 |
|
| 242 |
qemu_put_be32s(f, &s->addr); |
|
| 243 | 248 |
for (i = 0; i < IOMMU_NREGS; i++) |
| 244 | 249 |
qemu_put_be32s(f, &s->regs[i]); |
| 245 |
qemu_put_be32s(f, &s->iostart);
|
|
| 250 |
qemu_put_be64s(f, &s->iostart);
|
|
| 246 | 251 |
} |
| 247 | 252 |
|
| 248 | 253 |
static int iommu_load(QEMUFile *f, void *opaque, int version_id) |
| ... | ... | |
| 250 | 255 |
IOMMUState *s = opaque; |
| 251 | 256 |
int i; |
| 252 | 257 |
|
| 253 |
if (version_id != 1)
|
|
| 258 |
if (version_id != 2)
|
|
| 254 | 259 |
return -EINVAL; |
| 255 | 260 |
|
| 256 |
qemu_get_be32s(f, &s->addr); |
|
| 257 | 261 |
for (i = 0; i < IOMMU_NREGS; i++) |
| 258 | 262 |
qemu_put_be32s(f, &s->regs[i]); |
| 259 |
qemu_get_be32s(f, &s->iostart);
|
|
| 263 |
qemu_get_be64s(f, &s->iostart);
|
|
| 260 | 264 |
|
| 261 | 265 |
return 0; |
| 262 | 266 |
} |
| ... | ... | |
| 270 | 274 |
s->regs[0] = IOMMU_VERSION; |
| 271 | 275 |
} |
| 272 | 276 |
|
| 273 |
void *iommu_init(uint32_t addr)
|
|
| 277 |
void *iommu_init(target_phys_addr_t addr)
|
|
| 274 | 278 |
{
|
| 275 | 279 |
IOMMUState *s; |
| 276 | 280 |
int iommu_io_memory; |
| ... | ... | |
| 284 | 288 |
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s); |
| 285 | 289 |
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory); |
| 286 | 290 |
|
| 287 |
register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
|
|
| 291 |
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
|
|
| 288 | 292 |
qemu_register_reset(iommu_reset, s); |
| 289 | 293 |
return s; |
| 290 | 294 |
} |
Also available in: Unified diff