Revision 5dcb6b91 hw/sun4m.c
| b/hw/sun4m.c | ||
|---|---|---|
| 48 | 48 |
#define MAX_CPUS 16 |
| 49 | 49 |
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| 50 | 50 |
struct hwdef {
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| 51 |
target_ulong iommu_base, slavio_base;
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target_ulong intctl_base, counter_base, nvram_base, ms_kb_base, serial_base;
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target_ulong fd_base;
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target_ulong dma_base, esp_base, le_base;
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target_ulong tcx_base, cs_base;
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target_phys_addr_t iommu_base, slavio_base;
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t dma_base, esp_base, le_base;
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target_phys_addr_t tcx_base, cs_base, power_base;
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| 56 | 56 |
long vram_size, nvram_size; |
| 57 | 57 |
// IRQ numbers are not PIL ones, but master interrupt controller register |
| 58 | 58 |
// bit numbers |
| ... | ... | |
| 289 | 289 |
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iommu = iommu_init(hwdef->iommu_base); |
| 291 | 291 |
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
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hwdef->intctl_base + 0x10000, |
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hwdef->intctl_base + 0x10000ULL,
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&hwdef->intbit_to_level[0], |
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&slavio_irq); |
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for(i = 0; i < smp_cpus; i++) {
|
| ... | ... | |
| 317 | 317 |
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
| 318 | 318 |
hwdef->nvram_size, 8); |
| 319 | 319 |
for (i = 0; i < MAX_CPUS; i++) {
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slavio_timer_init(hwdef->counter_base + i * TARGET_PAGE_SIZE, |
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slavio_timer_init(hwdef->counter_base + |
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(target_phys_addr_t)(i * TARGET_PAGE_SIZE), |
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| 321 | 322 |
hwdef->clock_irq, 0, i, slavio_intctl); |
| 322 | 323 |
} |
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slavio_timer_init(hwdef->counter_base + 0x10000, hwdef->clock1_irq, 2, |
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slavio_timer_init(hwdef->counter_base + 0x10000ULL, hwdef->clock1_irq, 2,
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|
| 324 | 325 |
(unsigned int)-1, slavio_intctl); |
| 325 | 326 |
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]); |
| 326 | 327 |
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
| ... | ... | |
| 336 | 337 |
} |
| 337 | 338 |
} |
| 338 | 339 |
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slavio_misc = slavio_misc_init(hwdef->slavio_base, |
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slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
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| 340 | 341 |
slavio_irq[hwdef->me_irq]); |
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if (hwdef->cs_base != (target_ulong)-1)
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if (hwdef->cs_base != (target_phys_addr_t)-1)
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| 342 | 343 |
cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
| 343 | 344 |
sparc32_dma_set_reset_data(dma, main_esp, main_lance); |
| 344 | 345 |
} |
| ... | ... | |
| 424 | 425 |
.dma_base = 0x78400000, |
| 425 | 426 |
.esp_base = 0x78800000, |
| 426 | 427 |
.le_base = 0x78c00000, |
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.power_base = 0x7a000000, |
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| 427 | 429 |
.vram_size = 0x00100000, |
| 428 | 430 |
.nvram_size = 0x2000, |
| 429 | 431 |
.esp_irq = 18, |
| ... | ... | |
| 443 | 445 |
}, |
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/* SS-10 */ |
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{
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.iommu_base = 0xe0000000, // XXX Actually at 0xfe0000000ULL (36 bits)
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.tcx_base = 0x20000000, // 0xe20000000ULL,
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.iommu_base = 0xfe0000000ULL,
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.tcx_base = 0xe20000000ULL, |
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| 448 | 450 |
.cs_base = -1, |
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.slavio_base = 0xf0000000, // 0xff0000000ULL, |
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.ms_kb_base = 0xf1000000, // 0xff1000000ULL, |
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.serial_base = 0xf1100000, // 0xff1100000ULL, |
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.nvram_base = 0xf1200000, // 0xff1200000ULL, |
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.fd_base = 0xf1700000, // 0xff1700000ULL, |
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.counter_base = 0xf1300000, // 0xff1300000ULL, |
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.intctl_base = 0xf1400000, // 0xff1400000ULL, |
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.dma_base = 0xf0400000, // 0xef0400000ULL, |
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.esp_base = 0xf0800000, // 0xef0800000ULL, |
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.le_base = 0xf0c00000, // 0xef0c00000ULL, |
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.slavio_base = 0xff0000000ULL, |
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.ms_kb_base = 0xff1000000ULL, |
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.serial_base = 0xff1100000ULL, |
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.nvram_base = 0xff1200000ULL, |
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.fd_base = 0xff1700000ULL, |
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.counter_base = 0xff1300000ULL, |
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.intctl_base = 0xff1400000ULL, |
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.dma_base = 0xef0400000ULL, |
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.esp_base = 0xef0800000ULL, |
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.le_base = 0xef0c00000ULL, |
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.power_base = 0xefa000000ULL, |
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| 459 | 462 |
.vram_size = 0x00100000, |
| 460 | 463 |
.nvram_size = 0x2000, |
| 461 | 464 |
.esp_irq = 18, |
| ... | ... | |
| 480 | 483 |
const char *initrd_filename, const char *cpu_model, |
| 481 | 484 |
unsigned int machine, int max_ram) |
| 482 | 485 |
{
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if (ram_size > max_ram) {
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if ((unsigned int)ram_size > (unsigned int)max_ram) {
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fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", |
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ram_size / (1024 * 1024), max_ram / (1024 * 1024)); |
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(unsigned int)ram_size / (1024 * 1024), |
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(unsigned int)max_ram / (1024 * 1024)); |
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| 486 | 490 |
exit(1); |
| 487 | 491 |
} |
| 488 | 492 |
sun4m_hw_init(&hwdefs[machine], ram_size, ds, cpu_model); |
| ... | ... | |
| 515 | 519 |
cpu_model = "TI SuperSparc II"; |
| 516 | 520 |
sun4m_common_init(ram_size, boot_device, ds, kernel_filename, |
| 517 | 521 |
kernel_cmdline, initrd_filename, cpu_model, |
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1, 0x20000000); // XXX tcx overlap, actually first 4GB ok
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1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok
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| 519 | 523 |
} |
| 520 | 524 |
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| 521 | 525 |
QEMUMachine ss5_machine = {
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