Revision 5dcb6b91 target-sparc/helper.c
| b/target-sparc/helper.c | ||
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| 117 | 117 |
} |
| 118 | 118 |
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| 119 | 119 |
*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xfffff000;
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*physical = 0xffffffffffff0000ULL;
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| 121 | 121 |
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */ |
| 123 | 123 |
/* Context base + context number */ |
| ... | ... | |
| 203 | 203 |
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/* Even if large ptes, we map only one 4KB page in the cache to |
| 205 | 205 |
avoid filling it too fast */ |
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*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset; |
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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| 207 | 207 |
return error_code; |
| 208 | 208 |
} |
| 209 | 209 |
|
| ... | ... | |
| 212 | 212 |
int is_user, int is_softmmu) |
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{
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| 214 | 214 |
target_phys_addr_t paddr; |
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unsigned long vaddr;
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target_ulong vaddr;
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int error_code = 0, prot, ret = 0, access_index; |
| 217 | 217 |
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
| ... | ... | |
| 220 | 220 |
vaddr = address & TARGET_PAGE_MASK; |
| 221 | 221 |
paddr &= TARGET_PAGE_MASK; |
| 222 | 222 |
#ifdef DEBUG_MMU |
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printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
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TARGET_FMT_lx "\n", address, paddr, vaddr); |
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#endif |
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu); |
| 226 | 227 |
return ret; |
| ... | ... | |
| 255 | 256 |
uint32_t pde; |
| 256 | 257 |
|
| 257 | 258 |
/* Context base + context number */ |
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
|
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(env->mmuregs[2] << 2); |
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| 259 | 261 |
pde = ldl_phys(pde_ptr); |
| 260 | 262 |
|
| 261 | 263 |
switch (pde & PTE_ENTRYTYPE_MASK) {
|
| ... | ... | |
| 314 | 316 |
#ifdef DEBUG_MMU |
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void dump_mmu(CPUState *env) |
| 316 | 318 |
{
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target_ulong va, va1, va2;
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unsigned int n, m, o;
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target_phys_addr_t pde_ptr, pa;
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
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target_phys_addr_t pde_ptr, pa; |
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uint32_t pde; |
| 321 | 323 |
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printf("MMU dump:\n");
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| 323 | 325 |
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
| 324 | 326 |
pde = ldl_phys(pde_ptr); |
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printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
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printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
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| 326 | 329 |
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
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pde_ptr = mmu_probe(env, va, 2);
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if (pde_ptr) {
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pde = mmu_probe(env, va, 2); |
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va); |
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
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" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
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| 331 | 335 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
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pde_ptr = mmu_probe(env, va1, 1);
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if (pde_ptr) {
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pde = mmu_probe(env, va1, 1); |
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va1); |
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
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" PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
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| 336 | 341 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
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pde_ptr = mmu_probe(env, va2, 0);
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if (pde_ptr) {
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pde = mmu_probe(env, va2, 0); |
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va2); |
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
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printf(" VA: " TARGET_FMT_lx ", PA: "
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TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
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va2, pa, pde); |
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| 341 | 348 |
} |
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} |
| 343 | 350 |
} |
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