Revision 5dcb6b91 target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 223 | 223 |
break; |
| 224 | 224 |
} |
| 225 | 225 |
break; |
| 226 |
case 0x21 ... 0x2f: /* MMU passthrough, unassigned */ |
|
| 226 |
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
|
| 227 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
|
| 228 |
switch(size) {
|
|
| 229 |
case 1: |
|
| 230 |
ret = ldub_phys((target_phys_addr_t)T0 |
|
| 231 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
|
| 232 |
break; |
|
| 233 |
case 2: |
|
| 234 |
ret = lduw_phys((target_phys_addr_t)(T0 & ~1) |
|
| 235 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
|
| 236 |
break; |
|
| 237 |
default: |
|
| 238 |
case 4: |
|
| 239 |
ret = ldl_phys((target_phys_addr_t)(T0 & ~3) |
|
| 240 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
|
| 241 |
break; |
|
| 242 |
case 8: |
|
| 243 |
ret = ldl_phys((target_phys_addr_t)(T0 & ~3) |
|
| 244 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
|
| 245 |
T0 = ldl_phys((target_phys_addr_t)((T0 + 4) & ~3) |
|
| 246 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
|
| 247 |
break; |
|
| 248 |
} |
|
| 249 |
break; |
|
| 250 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ |
|
| 227 | 251 |
default: |
| 228 | 252 |
do_unassigned_access(T0, 0, 0, 1); |
| 229 | 253 |
ret = 0; |
| ... | ... | |
| 360 | 384 |
} |
| 361 | 385 |
} |
| 362 | 386 |
return; |
| 387 |
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ |
|
| 388 |
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ |
|
| 389 |
{
|
|
| 390 |
switch(size) {
|
|
| 391 |
case 1: |
|
| 392 |
stb_phys((target_phys_addr_t)T0 |
|
| 393 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
|
| 394 |
break; |
|
| 395 |
case 2: |
|
| 396 |
stw_phys((target_phys_addr_t)(T0 & ~1) |
|
| 397 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
|
| 398 |
break; |
|
| 399 |
case 4: |
|
| 400 |
default: |
|
| 401 |
stl_phys((target_phys_addr_t)(T0 & ~3) |
|
| 402 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
|
| 403 |
break; |
|
| 404 |
case 8: |
|
| 405 |
stl_phys((target_phys_addr_t)(T0 & ~3) |
|
| 406 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
|
| 407 |
stl_phys((target_phys_addr_t)((T0 + 4) & ~3) |
|
| 408 |
| ((target_phys_addr_t)(asi & 0xf) << 32), T1); |
|
| 409 |
break; |
|
| 410 |
} |
|
| 411 |
} |
|
| 412 |
return; |
|
| 363 | 413 |
case 0x31: /* Ross RT620 I-cache flush */ |
| 364 | 414 |
case 0x36: /* I-cache flash clear */ |
| 365 | 415 |
case 0x37: /* D-cache flash clear */ |
| 366 | 416 |
break; |
| 367 | 417 |
case 9: /* Supervisor code access, XXX */ |
| 368 |
case 0x21 ... 0x2f: /* MMU passthrough, unassigned */
|
|
| 418 |
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
|
|
| 369 | 419 |
default: |
| 370 | 420 |
do_unassigned_access(T0, 1, 0, 1); |
| 371 | 421 |
return; |
| ... | ... | |
| 1035 | 1085 |
#endif |
| 1036 | 1086 |
|
| 1037 | 1087 |
#ifndef TARGET_SPARC64 |
| 1038 |
void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
|
|
| 1088 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
| 1039 | 1089 |
int is_asi) |
| 1040 | 1090 |
{
|
| 1041 | 1091 |
CPUState *saved_env; |
| ... | ... | |
| 1058 | 1108 |
env->mmuregs[4] = addr; /* Fault address register */ |
| 1059 | 1109 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
|
| 1060 | 1110 |
#ifdef DEBUG_UNASSIGNED |
| 1061 |
printf("Unassigned mem access to " TARGET_FMT_lx " from " TARGET_FMT_lx
|
|
| 1111 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
|
|
| 1062 | 1112 |
"\n", addr, env->pc); |
| 1063 | 1113 |
#endif |
| 1064 | 1114 |
raise_exception(TT_DATA_ACCESS); |
| ... | ... | |
| 1066 | 1116 |
env = saved_env; |
| 1067 | 1117 |
} |
| 1068 | 1118 |
#else |
| 1069 |
void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
|
|
| 1119 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
| 1070 | 1120 |
int is_asi) |
| 1071 | 1121 |
{
|
| 1072 | 1122 |
#ifdef DEBUG_UNASSIGNED |
| ... | ... | |
| 1076 | 1126 |
generated code */ |
| 1077 | 1127 |
saved_env = env; |
| 1078 | 1128 |
env = cpu_single_env; |
| 1079 |
printf("Unassigned mem access to " TARGET_FMT_lx " from " TARGET_FMT_lx "\n",
|
|
| 1129 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
|
|
| 1080 | 1130 |
addr, env->pc); |
| 1081 | 1131 |
env = saved_env; |
| 1082 | 1132 |
#endif |
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