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1
/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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25
#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%g0",
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    "%g1",
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    "%g2",
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    "%g3",
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    "%g4",
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    "%g5",
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    "%g6",
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    "%g7",
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    "%o0",
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    "%o1",
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    "%o2",
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    "%o3",
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    "%o4",
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    "%o5",
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    "%o6",
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    "%o7",
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    "%l0",
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    "%l1",
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    "%l2",
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    "%l3",
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    "%l4",
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    "%l5",
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    "%l6",
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    "%l7",
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    "%i0",
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    "%i1",
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    "%i2",
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    "%i3",
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    "%i4",
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    "%i5",
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    "%i6",
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    "%i7",
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};
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#endif
61

    
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_L0,
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    TCG_REG_L1,
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    TCG_REG_L2,
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    TCG_REG_L3,
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    TCG_REG_L4,
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    TCG_REG_L5,
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    TCG_REG_L6,
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    TCG_REG_L7,
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    TCG_REG_I0,
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    TCG_REG_I1,
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    TCG_REG_I2,
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    TCG_REG_I3,
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    TCG_REG_I4,
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};
77

    
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static const int tcg_target_call_iarg_regs[6] = {
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    TCG_REG_O0,
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    TCG_REG_O1,
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    TCG_REG_O2,
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    TCG_REG_O3,
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    TCG_REG_O4,
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    TCG_REG_O5,
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};
86

    
87
static const int tcg_target_call_oarg_regs[2] = {
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    TCG_REG_O0,
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    TCG_REG_O1,
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};
91

    
92
static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
93
{
94
    return (val << ((sizeof(tcg_target_long) * 8 - bits))
95
            >> (sizeof(tcg_target_long) * 8 - bits)) == val;
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}
97

    
98
static inline int check_fit_i32(uint32_t val, unsigned int bits)
99
{
100
    return ((val << (32 - bits)) >> (32 - bits)) == val;
101
}
102

    
103
static void patch_reloc(uint8_t *code_ptr, int type,
104
                        tcg_target_long value, tcg_target_long addend)
105
{
106
    value += addend;
107
    switch (type) {
108
    case R_SPARC_32:
109
        if (value != (uint32_t)value)
110
            tcg_abort();
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        *(uint32_t *)code_ptr = value;
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        break;
113
    case R_SPARC_WDISP22:
114
        value -= (long)code_ptr;
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        value >>= 2;
116
        if (!check_fit_tl(value, 22))
117
            tcg_abort();
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        *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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        break;
120
    case R_SPARC_WDISP19:
121
        value -= (long)code_ptr;
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        value >>= 2;
123
        if (!check_fit_tl(value, 19))
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            tcg_abort();
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        *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
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        break;
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    default:
128
        tcg_abort();
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    }
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}
131

    
132
/* maximum number of register used for input function arguments */
133
static inline int tcg_target_get_call_iarg_regs_count(int flags)
134
{
135
    return 6;
136
}
137

    
138
/* parse target specific constraints */
139
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
140
{
141
    const char *ct_str;
142

    
143
    ct_str = *pct_str;
144
    switch (ct_str[0]) {
145
    case 'r':
146
        ct->ct |= TCG_CT_REG;
147
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
148
        break;
149
    case 'L': /* qemu_ld/st constraint */
150
        ct->ct |= TCG_CT_REG;
151
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
152
        // Helper args
153
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
154
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
155
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
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        break;
157
    case 'I':
158
        ct->ct |= TCG_CT_CONST_S11;
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        break;
160
    case 'J':
161
        ct->ct |= TCG_CT_CONST_S13;
162
        break;
163
    default:
164
        return -1;
165
    }
166
    ct_str++;
167
    *pct_str = ct_str;
168
    return 0;
169
}
170

    
171
/* test if a constant matches the constraint */
172
static inline int tcg_target_const_match(tcg_target_long val,
173
                                         const TCGArgConstraint *arg_ct)
174
{
175
    int ct;
176

    
177
    ct = arg_ct->ct;
178
    if (ct & TCG_CT_CONST)
179
        return 1;
180
    else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
181
        return 1;
182
    else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
183
        return 1;
184
    else
185
        return 0;
186
}
187

    
188
#define INSN_OP(x)  ((x) << 30)
189
#define INSN_OP2(x) ((x) << 22)
190
#define INSN_OP3(x) ((x) << 19)
191
#define INSN_OPF(x) ((x) << 5)
192
#define INSN_RD(x)  ((x) << 25)
193
#define INSN_RS1(x) ((x) << 14)
194
#define INSN_RS2(x) (x)
195
#define INSN_ASI(x) ((x) << 5)
196

    
197
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
198
#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
199
#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
200

    
201
#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
202
#define COND_N     0x0
203
#define COND_E     0x1
204
#define COND_LE    0x2
205
#define COND_L     0x3
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#define COND_LEU   0x4
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#define COND_CS    0x5
208
#define COND_NEG   0x6
209
#define COND_VS    0x7
210
#define COND_A     0x8
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#define COND_NE    0x9
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#define COND_G     0xa
213
#define COND_GE    0xb
214
#define COND_GU    0xc
215
#define COND_CC    0xd
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#define COND_POS   0xe
217
#define COND_VC    0xf
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#define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
219

    
220
#define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
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#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
222
#define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
223
#define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
224
#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
225
#define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
226
#define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
227
#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
228
#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
229
#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
230
#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
231
#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
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#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
233
#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
234
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
236

    
237
#define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
238
#define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
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#define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
240

    
241
#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
242
#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
243
#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
244

    
245
#define RDY        (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
246
#define WRY        (INSN_OP(2) | INSN_OP3(0x30))
247
#define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
248
#define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
249
#define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
250
#define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
251
#define CALL       INSN_OP(1)
252
#define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
253
#define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
254
#define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
255
#define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
256
#define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
257
#define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
258
#define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
259
#define STB        (INSN_OP(3) | INSN_OP3(0x05))
260
#define STH        (INSN_OP(3) | INSN_OP3(0x06))
261
#define STW        (INSN_OP(3) | INSN_OP3(0x04))
262
#define STX        (INSN_OP(3) | INSN_OP3(0x0e))
263
#define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
264
#define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
265
#define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
266
#define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
267
#define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
268
#define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
269
#define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
270
#define STBA       (INSN_OP(3) | INSN_OP3(0x15))
271
#define STHA       (INSN_OP(3) | INSN_OP3(0x16))
272
#define STWA       (INSN_OP(3) | INSN_OP3(0x14))
273
#define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
274

    
275
#ifndef ASI_PRIMARY_LITTLE
276
#define ASI_PRIMARY_LITTLE 0x88
277
#endif
278

    
279
static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
280
                                 int op)
281
{
282
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
283
              INSN_RS2(rs2));
284
}
285

    
286
static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
287
                                  uint32_t offset, int op)
288
{
289
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
290
              INSN_IMM13(offset));
291
}
292

    
293
static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
294
                           int val2, int val2const, int op)
295
{
296
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
297
              | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
298
}
299

    
300
static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
301
{
302
    tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
303
}
304

    
305
static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
306
{
307
    tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
308
}
309

    
310
static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
311
{
312
    tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
313
}
314

    
315
static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
316
{
317
    if (check_fit_tl(arg, 13))
318
        tcg_out_movi_imm13(s, ret, arg);
319
    else {
320
        tcg_out_sethi(s, ret, arg);
321
        if (arg & 0x3ff)
322
            tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
323
    }
324
}
325

    
326
static inline void tcg_out_movi(TCGContext *s, TCGType type,
327
                                int ret, tcg_target_long arg)
328
{
329
    /* All 32-bit constants, as well as 64-bit constants with
330
       no high bits set go through movi_imm32.  */
331
    if (TCG_TARGET_REG_BITS == 32
332
        || type == TCG_TYPE_I32
333
        || (arg & ~(tcg_target_long)0xffffffff) == 0) {
334
        tcg_out_movi_imm32(s, ret, arg);
335
    } else if (check_fit_tl(arg, 13)) {
336
        /* A 13-bit constant sign-extended to 64-bits.  */
337
        tcg_out_movi_imm13(s, ret, arg);
338
    } else if (check_fit_tl(arg, 32)) {
339
        /* A 32-bit constant sign-extended to 64-bits.  */
340
        tcg_out_sethi(s, ret, ~arg);
341
        tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
342
    } else {
343
        tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
344
        tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
345
        tcg_out_movi_imm32(s, ret, arg);
346
        tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
347
    }
348
}
349

    
350
static inline void tcg_out_ld_raw(TCGContext *s, int ret,
351
                                  tcg_target_long arg)
352
{
353
    tcg_out_sethi(s, ret, arg);
354
    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
355
              INSN_IMM13(arg & 0x3ff));
356
}
357

    
358
static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
359
                                  tcg_target_long arg)
360
{
361
    if (!check_fit_tl(arg, 10))
362
        tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
363
    if (TCG_TARGET_REG_BITS == 64) {
364
        tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
365
                  INSN_IMM13(arg & 0x3ff));
366
    } else {
367
        tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
368
                  INSN_IMM13(arg & 0x3ff));
369
    }
370
}
371

    
372
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
373
{
374
    if (check_fit_tl(offset, 13))
375
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
376
                  INSN_IMM13(offset));
377
    else {
378
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
379
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
380
                  INSN_RS2(addr));
381
    }
382
}
383

    
384
static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
385
                                    int offset, int op, int asi)
386
{
387
    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
388
    tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
389
              INSN_ASI(asi) | INSN_RS2(addr));
390
}
391

    
392
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
393
                              int arg1, tcg_target_long arg2)
394
{
395
    if (type == TCG_TYPE_I32)
396
        tcg_out_ldst(s, ret, arg1, arg2, LDUW);
397
    else
398
        tcg_out_ldst(s, ret, arg1, arg2, LDX);
399
}
400

    
401
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
402
                              int arg1, tcg_target_long arg2)
403
{
404
    if (type == TCG_TYPE_I32)
405
        tcg_out_ldst(s, arg, arg1, arg2, STW);
406
    else
407
        tcg_out_ldst(s, arg, arg1, arg2, STX);
408
}
409

    
410
static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
411
{
412
    if (val == 0 || val == -1)
413
        tcg_out32(s, WRY | INSN_IMM13(val));
414
    else
415
        fprintf(stderr, "unimplemented sety %ld\n", (long)val);
416
}
417

    
418
static inline void tcg_out_rdy(TCGContext *s, int rd)
419
{
420
    tcg_out32(s, RDY | INSN_RD(rd));
421
}
422

    
423
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
424
{
425
    if (val != 0) {
426
        if (check_fit_tl(val, 13))
427
            tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
428
        else {
429
            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
430
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
431
        }
432
    }
433
}
434

    
435
static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
436
{
437
    if (val != 0) {
438
        if (check_fit_tl(val, 13))
439
            tcg_out_arithi(s, reg, reg, val, ARITH_AND);
440
        else {
441
            tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
442
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
443
        }
444
    }
445
}
446

    
447
static inline void tcg_out_nop(TCGContext *s)
448
{
449
    tcg_out_sethi(s, TCG_REG_G0, 0);
450
}
451

    
452
static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
453
{
454
    int32_t val;
455
    TCGLabel *l = &s->labels[label_index];
456

    
457
    if (l->has_value) {
458
        val = l->u.value - (tcg_target_long)s->code_ptr;
459
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
460
                      | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
461
    } else {
462
        tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
463
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
464
    }
465
}
466

    
467
#if TCG_TARGET_REG_BITS == 64
468
static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
469
{
470
    int32_t val;
471
    TCGLabel *l = &s->labels[label_index];
472

    
473
    if (l->has_value) {
474
        val = l->u.value - (tcg_target_long)s->code_ptr;
475
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
476
                      (0x5 << 19) |
477
                      INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
478
    } else {
479
        tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
480
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
481
                      (0x5 << 19) | 0));
482
    }
483
}
484
#endif
485

    
486
static const uint8_t tcg_cond_to_bcond[10] = {
487
    [TCG_COND_EQ] = COND_E,
488
    [TCG_COND_NE] = COND_NE,
489
    [TCG_COND_LT] = COND_L,
490
    [TCG_COND_GE] = COND_GE,
491
    [TCG_COND_LE] = COND_LE,
492
    [TCG_COND_GT] = COND_G,
493
    [TCG_COND_LTU] = COND_CS,
494
    [TCG_COND_GEU] = COND_CC,
495
    [TCG_COND_LEU] = COND_LEU,
496
    [TCG_COND_GTU] = COND_GU,
497
};
498

    
499
static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
500
{
501
    tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
502
}
503

    
504
static void tcg_out_brcond_i32(TCGContext *s, int cond,
505
                               TCGArg arg1, TCGArg arg2, int const_arg2,
506
                               int label_index)
507
{
508
    tcg_out_cmp(s, arg1, arg2, const_arg2);
509
    tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
510
    tcg_out_nop(s);
511
}
512

    
513
#if TCG_TARGET_REG_BITS == 64
514
static void tcg_out_brcond_i64(TCGContext *s, int cond,
515
                               TCGArg arg1, TCGArg arg2, int const_arg2,
516
                               int label_index)
517
{
518
    tcg_out_cmp(s, arg1, arg2, const_arg2);
519
    tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
520
    tcg_out_nop(s);
521
}
522
#else
523
static void tcg_out_brcond2_i32(TCGContext *s, int cond,
524
                                TCGArg al, TCGArg ah,
525
                                TCGArg bl, int blconst,
526
                                TCGArg bh, int bhconst, int label_dest)
527
{
528
    int cc, label_next = gen_new_label();
529

    
530
    tcg_out_cmp(s, ah, bh, bhconst);
531

    
532
    /* Note that we fill one of the delay slots with the second compare.  */
533
    switch (cond) {
534
    case TCG_COND_EQ:
535
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
536
        tcg_out_branch_i32(s, cc, label_next);
537
        tcg_out_cmp(s, al, bl, blconst);
538
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
539
        tcg_out_branch_i32(s, cc, label_dest);
540
        break;
541

    
542
    case TCG_COND_NE:
543
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
544
        tcg_out_branch_i32(s, cc, label_dest);
545
        tcg_out_cmp(s, al, bl, blconst);
546
        tcg_out_branch_i32(s, cc, label_dest);
547
        break;
548

    
549
    default:
550
        /* ??? One could fairly easily special-case 64-bit unsigned
551
           compares against 32-bit zero-extended constants.  For instance,
552
           we know that (unsigned)AH < 0 is false and need not emit it.
553
           Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
554
           second branch will never be taken.  */
555
        cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
556
        tcg_out_branch_i32(s, cc, label_dest);
557
        tcg_out_nop(s);
558
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
559
        tcg_out_branch_i32(s, cc, label_next);
560
        tcg_out_cmp(s, al, bl, blconst);
561
        cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
562
        tcg_out_branch_i32(s, cc, label_dest);
563
        break;
564
    }
565
    tcg_out_nop(s);
566

    
567
    tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
568
}
569
#endif
570

    
571
/* Generate global QEMU prologue and epilogue code */
572
void tcg_target_qemu_prologue(TCGContext *s)
573
{
574
    tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
575
              INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
576
    tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
577
              INSN_RS2(TCG_REG_G0));
578
    tcg_out_nop(s);
579
}
580

    
581
#if defined(CONFIG_SOFTMMU)
582

    
583
#include "../../softmmu_defs.h"
584

    
585
static const void * const qemu_ld_helpers[4] = {
586
    __ldb_mmu,
587
    __ldw_mmu,
588
    __ldl_mmu,
589
    __ldq_mmu,
590
};
591

    
592
static const void * const qemu_st_helpers[4] = {
593
    __stb_mmu,
594
    __stw_mmu,
595
    __stl_mmu,
596
    __stq_mmu,
597
};
598
#endif
599

    
600
#if TARGET_LONG_BITS == 32
601
#define TARGET_LD_OP LDUW
602
#else
603
#define TARGET_LD_OP LDX
604
#endif
605

    
606
#if TARGET_PHYS_ADDR_BITS == 32
607
#define TARGET_ADDEND_LD_OP LDUW
608
#else
609
#define TARGET_ADDEND_LD_OP LDX
610
#endif
611

    
612
#ifdef __arch64__
613
#define HOST_LD_OP LDX
614
#define HOST_ST_OP STX
615
#define HOST_SLL_OP SHIFT_SLLX
616
#define HOST_SRA_OP SHIFT_SRAX
617
#else
618
#define HOST_LD_OP LDUW
619
#define HOST_ST_OP STW
620
#define HOST_SLL_OP SHIFT_SLL
621
#define HOST_SRA_OP SHIFT_SRA
622
#endif
623

    
624
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
625
                            int opc)
626
{
627
    int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
628
#if defined(CONFIG_SOFTMMU)
629
    uint32_t *label1_ptr, *label2_ptr;
630
#endif
631

    
632
    data_reg = *args++;
633
    addr_reg = *args++;
634
    mem_index = *args;
635
    s_bits = opc & 3;
636

    
637
    arg0 = TCG_REG_O0;
638
    arg1 = TCG_REG_O1;
639
    arg2 = TCG_REG_O2;
640

    
641
#if defined(CONFIG_SOFTMMU)
642
    /* srl addr_reg, x, arg1 */
643
    tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
644
                   SHIFT_SRL);
645
    /* and addr_reg, x, arg0 */
646
    tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
647
                   ARITH_AND);
648

    
649
    /* and arg1, x, arg1 */
650
    tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
651

    
652
    /* add arg1, x, arg1 */
653
    tcg_out_addi(s, arg1, offsetof(CPUState,
654
                                   tlb_table[mem_index][0].addr_read));
655

    
656
    /* add env, arg1, arg1 */
657
    tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
658

    
659
    /* ld [arg1], arg2 */
660
    tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
661
              INSN_RS2(TCG_REG_G0));
662

    
663
    /* subcc arg0, arg2, %g0 */
664
    tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
665

    
666
    /* will become:
667
       be label1
668
        or
669
       be,pt %xcc label1 */
670
    label1_ptr = (uint32_t *)s->code_ptr;
671
    tcg_out32(s, 0);
672

    
673
    /* mov (delay slot) */
674
    tcg_out_mov(s, arg0, addr_reg);
675

    
676
    /* mov */
677
    tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
678

    
679
    /* XXX: move that code at the end of the TB */
680
    /* qemu_ld_helper[s_bits](arg0, arg1) */
681
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
682
                           - (tcg_target_ulong)s->code_ptr) >> 2)
683
                         & 0x3fffffff));
684
    /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
685
       global registers */
686
    // delay slot
687
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
688
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
689
                 sizeof(long), HOST_ST_OP);
690
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
691
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
692
                 sizeof(long), HOST_LD_OP);
693

    
694
    /* data_reg = sign_extend(arg0) */
695
    switch(opc) {
696
    case 0 | 4:
697
        /* sll arg0, 24/56, data_reg */
698
        tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
699
                       HOST_SLL_OP);
700
        /* sra data_reg, 24/56, data_reg */
701
        tcg_out_arithi(s, data_reg, data_reg,
702
                       (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
703
        break;
704
    case 1 | 4:
705
        /* sll arg0, 16/48, data_reg */
706
        tcg_out_arithi(s, data_reg, arg0,
707
                       (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
708
        /* sra data_reg, 16/48, data_reg */
709
        tcg_out_arithi(s, data_reg, data_reg,
710
                       (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
711
        break;
712
    case 2 | 4:
713
        /* sll arg0, 32, data_reg */
714
        tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
715
        /* sra data_reg, 32, data_reg */
716
        tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
717
        break;
718
    case 0:
719
    case 1:
720
    case 2:
721
    case 3:
722
    default:
723
        /* mov */
724
        tcg_out_mov(s, data_reg, arg0);
725
        break;
726
    }
727

    
728
    /* will become:
729
       ba label2 */
730
    label2_ptr = (uint32_t *)s->code_ptr;
731
    tcg_out32(s, 0);
732

    
733
    /* nop (delay slot */
734
    tcg_out_nop(s);
735

    
736
    /* label1: */
737
#if TARGET_LONG_BITS == 32
738
    /* be label1 */
739
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
740
                   INSN_OFF22((unsigned long)s->code_ptr -
741
                              (unsigned long)label1_ptr));
742
#else
743
    /* be,pt %xcc label1 */
744
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
745
                   (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
746
                              (unsigned long)label1_ptr));
747
#endif
748

    
749
    /* ld [arg1 + x], arg1 */
750
    tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
751
                 offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
752

    
753
#if TARGET_LONG_BITS == 32
754
    /* and addr_reg, x, arg0 */
755
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
756
    tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
757
    /* add arg0, arg1, arg0 */
758
    tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
759
#else
760
    /* add addr_reg, arg1, arg0 */
761
    tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
762
#endif
763

    
764
#else
765
    arg0 = addr_reg;
766
#endif
767

    
768
    switch(opc) {
769
    case 0:
770
        /* ldub [arg0], data_reg */
771
        tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
772
        break;
773
    case 0 | 4:
774
        /* ldsb [arg0], data_reg */
775
        tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
776
        break;
777
    case 1:
778
#ifdef TARGET_WORDS_BIGENDIAN
779
        /* lduh [arg0], data_reg */
780
        tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
781
#else
782
        /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
783
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
784
#endif
785
        break;
786
    case 1 | 4:
787
#ifdef TARGET_WORDS_BIGENDIAN
788
        /* ldsh [arg0], data_reg */
789
        tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
790
#else
791
        /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
792
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
793
#endif
794
        break;
795
    case 2:
796
#ifdef TARGET_WORDS_BIGENDIAN
797
        /* lduw [arg0], data_reg */
798
        tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
799
#else
800
        /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
801
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
802
#endif
803
        break;
804
    case 2 | 4:
805
#ifdef TARGET_WORDS_BIGENDIAN
806
        /* ldsw [arg0], data_reg */
807
        tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
808
#else
809
        /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
810
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
811
#endif
812
        break;
813
    case 3:
814
#ifdef TARGET_WORDS_BIGENDIAN
815
        /* ldx [arg0], data_reg */
816
        tcg_out_ldst(s, data_reg, arg0, 0, LDX);
817
#else
818
        /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
819
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
820
#endif
821
        break;
822
    default:
823
        tcg_abort();
824
    }
825

    
826
#if defined(CONFIG_SOFTMMU)
827
    /* label2: */
828
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
829
                   INSN_OFF22((unsigned long)s->code_ptr -
830
                              (unsigned long)label2_ptr));
831
#endif
832
}
833

    
834
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
835
                            int opc)
836
{
837
    int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
838
#if defined(CONFIG_SOFTMMU)
839
    uint32_t *label1_ptr, *label2_ptr;
840
#endif
841

    
842
    data_reg = *args++;
843
    addr_reg = *args++;
844
    mem_index = *args;
845

    
846
    s_bits = opc;
847

    
848
    arg0 = TCG_REG_O0;
849
    arg1 = TCG_REG_O1;
850
    arg2 = TCG_REG_O2;
851

    
852
#if defined(CONFIG_SOFTMMU)
853
    /* srl addr_reg, x, arg1 */
854
    tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
855
                   SHIFT_SRL);
856

    
857
    /* and addr_reg, x, arg0 */
858
    tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
859
                   ARITH_AND);
860

    
861
    /* and arg1, x, arg1 */
862
    tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
863

    
864
    /* add arg1, x, arg1 */
865
    tcg_out_addi(s, arg1, offsetof(CPUState,
866
                                   tlb_table[mem_index][0].addr_write));
867

    
868
    /* add env, arg1, arg1 */
869
    tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
870

    
871
    /* ld [arg1], arg2 */
872
    tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
873
              INSN_RS2(TCG_REG_G0));
874

    
875
    /* subcc arg0, arg2, %g0 */
876
    tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
877

    
878
    /* will become:
879
       be label1
880
        or
881
       be,pt %xcc label1 */
882
    label1_ptr = (uint32_t *)s->code_ptr;
883
    tcg_out32(s, 0);
884

    
885
    /* mov (delay slot) */
886
    tcg_out_mov(s, arg0, addr_reg);
887

    
888
    /* mov */
889
    tcg_out_mov(s, arg1, data_reg);
890

    
891
    /* mov */
892
    tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
893

    
894
    /* XXX: move that code at the end of the TB */
895
    /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
896
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
897
                           - (tcg_target_ulong)s->code_ptr) >> 2)
898
                         & 0x3fffffff));
899
    /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
900
       global registers */
901
    // delay slot
902
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
903
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
904
                 sizeof(long), HOST_ST_OP);
905
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
906
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
907
                 sizeof(long), HOST_LD_OP);
908

    
909
    /* will become:
910
       ba label2 */
911
    label2_ptr = (uint32_t *)s->code_ptr;
912
    tcg_out32(s, 0);
913

    
914
    /* nop (delay slot) */
915
    tcg_out_nop(s);
916

    
917
#if TARGET_LONG_BITS == 32
918
    /* be label1 */
919
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
920
                   INSN_OFF22((unsigned long)s->code_ptr -
921
                              (unsigned long)label1_ptr));
922
#else
923
    /* be,pt %xcc label1 */
924
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
925
                   (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
926
                              (unsigned long)label1_ptr));
927
#endif
928

    
929
    /* ld [arg1 + x], arg1 */
930
    tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
931
                 offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
932

    
933
#if TARGET_LONG_BITS == 32
934
    /* and addr_reg, x, arg0 */
935
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
936
    tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
937
    /* add arg0, arg1, arg0 */
938
    tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
939
#else
940
    /* add addr_reg, arg1, arg0 */
941
    tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
942
#endif
943

    
944
#else
945
    arg0 = addr_reg;
946
#endif
947

    
948
    switch(opc) {
949
    case 0:
950
        /* stb data_reg, [arg0] */
951
        tcg_out_ldst(s, data_reg, arg0, 0, STB);
952
        break;
953
    case 1:
954
#ifdef TARGET_WORDS_BIGENDIAN
955
        /* sth data_reg, [arg0] */
956
        tcg_out_ldst(s, data_reg, arg0, 0, STH);
957
#else
958
        /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
959
        tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
960
#endif
961
        break;
962
    case 2:
963
#ifdef TARGET_WORDS_BIGENDIAN
964
        /* stw data_reg, [arg0] */
965
        tcg_out_ldst(s, data_reg, arg0, 0, STW);
966
#else
967
        /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
968
        tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
969
#endif
970
        break;
971
    case 3:
972
#ifdef TARGET_WORDS_BIGENDIAN
973
        /* stx data_reg, [arg0] */
974
        tcg_out_ldst(s, data_reg, arg0, 0, STX);
975
#else
976
        /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
977
        tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
978
#endif
979
        break;
980
    default:
981
        tcg_abort();
982
    }
983

    
984
#if defined(CONFIG_SOFTMMU)
985
    /* label2: */
986
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
987
                   INSN_OFF22((unsigned long)s->code_ptr -
988
                              (unsigned long)label2_ptr));
989
#endif
990
}
991

    
992
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
993
                              const int *const_args)
994
{
995
    int c;
996

    
997
    switch (opc) {
998
    case INDEX_op_exit_tb:
999
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1000
        tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1001
                  INSN_IMM13(8));
1002
        tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1003
                      INSN_RS2(TCG_REG_G0));
1004
        break;
1005
    case INDEX_op_goto_tb:
1006
        if (s->tb_jmp_offset) {
1007
            /* direct jump method */
1008
            tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
1009
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1010
                      INSN_IMM13((args[0] & 0x1fff)));
1011
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1012
        } else {
1013
            /* indirect jump method */
1014
            tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1015
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1016
                      INSN_RS2(TCG_REG_G0));
1017
        }
1018
        tcg_out_nop(s);
1019
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1020
        break;
1021
    case INDEX_op_call:
1022
        if (const_args[0])
1023
            tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1024
                                   - (tcg_target_ulong)s->code_ptr) >> 2)
1025
                                 & 0x3fffffff));
1026
        else {
1027
            tcg_out_ld_ptr(s, TCG_REG_I5,
1028
                           (tcg_target_long)(s->tb_next + args[0]));
1029
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1030
                      INSN_RS2(TCG_REG_G0));
1031
        }
1032
        /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1033
           global registers */
1034
        // delay slot
1035
        tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1036
                     TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1037
                     sizeof(long), HOST_ST_OP);
1038
        tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1039
                     TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1040
                     sizeof(long), HOST_LD_OP);
1041
        break;
1042
    case INDEX_op_jmp:
1043
    case INDEX_op_br:
1044
        tcg_out_branch_i32(s, COND_A, args[0]);
1045
        tcg_out_nop(s);
1046
        break;
1047
    case INDEX_op_movi_i32:
1048
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1049
        break;
1050

    
1051
#if TCG_TARGET_REG_BITS == 64
1052
#define OP_32_64(x)                             \
1053
        glue(glue(case INDEX_op_, x), _i32):    \
1054
        glue(glue(case INDEX_op_, x), _i64)
1055
#else
1056
#define OP_32_64(x)                             \
1057
        glue(glue(case INDEX_op_, x), _i32)
1058
#endif
1059
    OP_32_64(ld8u):
1060
        tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1061
        break;
1062
    OP_32_64(ld8s):
1063
        tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1064
        break;
1065
    OP_32_64(ld16u):
1066
        tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1067
        break;
1068
    OP_32_64(ld16s):
1069
        tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1070
        break;
1071
    case INDEX_op_ld_i32:
1072
#if TCG_TARGET_REG_BITS == 64
1073
    case INDEX_op_ld32u_i64:
1074
#endif
1075
        tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1076
        break;
1077
    OP_32_64(st8):
1078
        tcg_out_ldst(s, args[0], args[1], args[2], STB);
1079
        break;
1080
    OP_32_64(st16):
1081
        tcg_out_ldst(s, args[0], args[1], args[2], STH);
1082
        break;
1083
    case INDEX_op_st_i32:
1084
#if TCG_TARGET_REG_BITS == 64
1085
    case INDEX_op_st32_i64:
1086
#endif
1087
        tcg_out_ldst(s, args[0], args[1], args[2], STW);
1088
        break;
1089
    OP_32_64(add):
1090
        c = ARITH_ADD;
1091
        goto gen_arith;
1092
    OP_32_64(sub):
1093
        c = ARITH_SUB;
1094
        goto gen_arith;
1095
    OP_32_64(and):
1096
        c = ARITH_AND;
1097
        goto gen_arith;
1098
    OP_32_64(or):
1099
        c = ARITH_OR;
1100
        goto gen_arith;
1101
    OP_32_64(xor):
1102
        c = ARITH_XOR;
1103
        goto gen_arith;
1104
    case INDEX_op_shl_i32:
1105
        c = SHIFT_SLL;
1106
        goto gen_arith;
1107
    case INDEX_op_shr_i32:
1108
        c = SHIFT_SRL;
1109
        goto gen_arith;
1110
    case INDEX_op_sar_i32:
1111
        c = SHIFT_SRA;
1112
        goto gen_arith;
1113
    case INDEX_op_mul_i32:
1114
        c = ARITH_UMUL;
1115
        goto gen_arith;
1116
    case INDEX_op_div2_i32:
1117
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
1118
        c = ARITH_SDIVX;
1119
        goto gen_arith;
1120
#else
1121
        tcg_out_sety(s, 0);
1122
        c = ARITH_SDIV;
1123
        goto gen_arith;
1124
#endif
1125
    case INDEX_op_divu2_i32:
1126
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
1127
        c = ARITH_UDIVX;
1128
        goto gen_arith;
1129
#else
1130
        tcg_out_sety(s, 0);
1131
        c = ARITH_UDIV;
1132
        goto gen_arith;
1133
#endif
1134

    
1135
    case INDEX_op_brcond_i32:
1136
        tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1137
                           args[3]);
1138
        break;
1139
#if TCG_TARGET_REG_BITS == 32
1140
    case INDEX_op_brcond2_i32:
1141
        tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1142
                            args[2], const_args[2],
1143
                            args[3], const_args[3], args[5]);
1144
        break;
1145
    case INDEX_op_add2_i32:
1146
        tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1147
                       ARITH_ADDCC);
1148
        tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1149
                       ARITH_ADDX);
1150
        break;
1151
    case INDEX_op_sub2_i32:
1152
        tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1153
                       ARITH_SUBCC);
1154
        tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1155
                       ARITH_SUBX);
1156
        break;
1157
    case INDEX_op_mulu2_i32:
1158
        tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1159
                       ARITH_UMUL);
1160
        tcg_out_rdy(s, args[1]);
1161
        break;
1162
#endif
1163

    
1164
    case INDEX_op_qemu_ld8u:
1165
        tcg_out_qemu_ld(s, args, 0);
1166
        break;
1167
    case INDEX_op_qemu_ld8s:
1168
        tcg_out_qemu_ld(s, args, 0 | 4);
1169
        break;
1170
    case INDEX_op_qemu_ld16u:
1171
        tcg_out_qemu_ld(s, args, 1);
1172
        break;
1173
    case INDEX_op_qemu_ld16s:
1174
        tcg_out_qemu_ld(s, args, 1 | 4);
1175
        break;
1176
    case INDEX_op_qemu_ld32u:
1177
        tcg_out_qemu_ld(s, args, 2);
1178
        break;
1179
    case INDEX_op_qemu_ld32s:
1180
        tcg_out_qemu_ld(s, args, 2 | 4);
1181
        break;
1182
    case INDEX_op_qemu_st8:
1183
        tcg_out_qemu_st(s, args, 0);
1184
        break;
1185
    case INDEX_op_qemu_st16:
1186
        tcg_out_qemu_st(s, args, 1);
1187
        break;
1188
    case INDEX_op_qemu_st32:
1189
        tcg_out_qemu_st(s, args, 2);
1190
        break;
1191

    
1192
#if TCG_TARGET_REG_BITS == 64
1193
    case INDEX_op_movi_i64:
1194
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1195
        break;
1196
    case INDEX_op_ld32s_i64:
1197
        tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1198
        break;
1199
    case INDEX_op_ld_i64:
1200
        tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1201
        break;
1202
    case INDEX_op_st_i64:
1203
        tcg_out_ldst(s, args[0], args[1], args[2], STX);
1204
        break;
1205
    case INDEX_op_shl_i64:
1206
        c = SHIFT_SLLX;
1207
        goto gen_arith;
1208
    case INDEX_op_shr_i64:
1209
        c = SHIFT_SRLX;
1210
        goto gen_arith;
1211
    case INDEX_op_sar_i64:
1212
        c = SHIFT_SRAX;
1213
        goto gen_arith;
1214
    case INDEX_op_mul_i64:
1215
        c = ARITH_MULX;
1216
        goto gen_arith;
1217
    case INDEX_op_div2_i64:
1218
        c = ARITH_SDIVX;
1219
        goto gen_arith;
1220
    case INDEX_op_divu2_i64:
1221
        c = ARITH_UDIVX;
1222
        goto gen_arith;
1223

    
1224
    case INDEX_op_brcond_i64:
1225
        tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1226
                           args[3]);
1227
        break;
1228
    case INDEX_op_qemu_ld64:
1229
        tcg_out_qemu_ld(s, args, 3);
1230
        break;
1231
    case INDEX_op_qemu_st64:
1232
        tcg_out_qemu_st(s, args, 3);
1233
        break;
1234

    
1235
#endif
1236
    gen_arith:
1237
        tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
1238
        break;
1239

    
1240
    default:
1241
        fprintf(stderr, "unknown opcode 0x%x\n", opc);
1242
        tcg_abort();
1243
    }
1244
}
1245

    
1246
static const TCGTargetOpDef sparc_op_defs[] = {
1247
    { INDEX_op_exit_tb, { } },
1248
    { INDEX_op_goto_tb, { } },
1249
    { INDEX_op_call, { "ri" } },
1250
    { INDEX_op_jmp, { "ri" } },
1251
    { INDEX_op_br, { } },
1252

    
1253
    { INDEX_op_mov_i32, { "r", "r" } },
1254
    { INDEX_op_movi_i32, { "r" } },
1255
    { INDEX_op_ld8u_i32, { "r", "r" } },
1256
    { INDEX_op_ld8s_i32, { "r", "r" } },
1257
    { INDEX_op_ld16u_i32, { "r", "r" } },
1258
    { INDEX_op_ld16s_i32, { "r", "r" } },
1259
    { INDEX_op_ld_i32, { "r", "r" } },
1260
    { INDEX_op_st8_i32, { "r", "r" } },
1261
    { INDEX_op_st16_i32, { "r", "r" } },
1262
    { INDEX_op_st_i32, { "r", "r" } },
1263

    
1264
    { INDEX_op_add_i32, { "r", "r", "rJ" } },
1265
    { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1266
    { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
1267
    { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
1268
    { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1269
    { INDEX_op_and_i32, { "r", "r", "rJ" } },
1270
    { INDEX_op_or_i32, { "r", "r", "rJ" } },
1271
    { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1272

    
1273
    { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1274
    { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1275
    { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1276

    
1277
    { INDEX_op_brcond_i32, { "r", "rJ" } },
1278
#if TCG_TARGET_REG_BITS == 32
1279
    { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
1280
    { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1281
    { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1282
    { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
1283
#endif
1284

    
1285
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1286
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1287
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1288
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1289
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1290
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1291

    
1292
    { INDEX_op_qemu_st8, { "L", "L" } },
1293
    { INDEX_op_qemu_st16, { "L", "L" } },
1294
    { INDEX_op_qemu_st32, { "L", "L" } },
1295

    
1296
#if TCG_TARGET_REG_BITS == 64
1297
    { INDEX_op_mov_i64, { "r", "r" } },
1298
    { INDEX_op_movi_i64, { "r" } },
1299
    { INDEX_op_ld8u_i64, { "r", "r" } },
1300
    { INDEX_op_ld8s_i64, { "r", "r" } },
1301
    { INDEX_op_ld16u_i64, { "r", "r" } },
1302
    { INDEX_op_ld16s_i64, { "r", "r" } },
1303
    { INDEX_op_ld32u_i64, { "r", "r" } },
1304
    { INDEX_op_ld32s_i64, { "r", "r" } },
1305
    { INDEX_op_ld_i64, { "r", "r" } },
1306
    { INDEX_op_st8_i64, { "r", "r" } },
1307
    { INDEX_op_st16_i64, { "r", "r" } },
1308
    { INDEX_op_st32_i64, { "r", "r" } },
1309
    { INDEX_op_st_i64, { "r", "r" } },
1310
    { INDEX_op_qemu_ld64, { "L", "L" } },
1311
    { INDEX_op_qemu_st64, { "L", "L" } },
1312

    
1313
    { INDEX_op_add_i64, { "r", "r", "rJ" } },
1314
    { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1315
    { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
1316
    { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
1317
    { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1318
    { INDEX_op_and_i64, { "r", "r", "rJ" } },
1319
    { INDEX_op_or_i64, { "r", "r", "rJ" } },
1320
    { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1321

    
1322
    { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1323
    { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1324
    { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1325

    
1326
    { INDEX_op_brcond_i64, { "r", "rJ" } },
1327
#endif
1328
    { -1 },
1329
};
1330

    
1331
void tcg_target_init(TCGContext *s)
1332
{
1333
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1334
#if TCG_TARGET_REG_BITS == 64
1335
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1336
#endif
1337
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1338
                     (1 << TCG_REG_G1) |
1339
                     (1 << TCG_REG_G2) |
1340
                     (1 << TCG_REG_G3) |
1341
                     (1 << TCG_REG_G4) |
1342
                     (1 << TCG_REG_G5) |
1343
                     (1 << TCG_REG_G6) |
1344
                     (1 << TCG_REG_G7) |
1345
                     (1 << TCG_REG_O0) |
1346
                     (1 << TCG_REG_O1) |
1347
                     (1 << TCG_REG_O2) |
1348
                     (1 << TCG_REG_O3) |
1349
                     (1 << TCG_REG_O4) |
1350
                     (1 << TCG_REG_O5) |
1351
                     (1 << TCG_REG_O7));
1352

    
1353
    tcg_regset_clear(s->reserved_regs);
1354
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1355
#if TCG_TARGET_REG_BITS == 64
1356
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1357
#endif
1358
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1359
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1360
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1361
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1362
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1363
    tcg_add_target_add_op_defs(sparc_op_defs);
1364
}